Patent Application
20240355552
The present invention relates to multilayer ceramic capacitors.
Conventionally, in order to mount each multilayer ceramic capacitor on a wiring board, external electrodes electrically connected to internal electrode layers are provided on a surface of a ceramic element body in which the internal electrode layers are embedded (for example, refer to Japanese Unexamined Patent Application, Publication No. H8-102425). Each of the external electrodes usually includes a base electrode layer including an electrically conductive metal and glass, and in order to prevent erosion by solder used in mounting on an electric circuit, the surface of the base electrode layer is covered with a Ni plated layer or a Sn plated layer.
An electrolytic plating method is generally used to form a plated layer. In the electrolytic plating method, a plated layer is formed so as to cover the base electrode layer by depositing and growing a plating film with an electrically conductive metal exposed on the surface of the base electrode layer as a core, but if the deposited plating film is uneven, a uniform plated layer will not be formed, and when the multilayer body is mounted on a wiring board, the multilayer body will be damaged by erosion of solder, resulting in failure of the multilayer ceramic capacitor.
On the other hand, although it is conceivable to form a thick plating film in order to improve the film-forming property of the plating film, the increase in the current in electrolytic plating and the extension of the electrolytic plating treatment time tend to cause variations in the thickness of the plated layer in mass production, making it difficult to maintain the quality constant. In addition, in order to maintain the dimensions of the multilayer ceramic capacitor within the standard dimensions, it is necessary to further reduce the thickness of the ceramic body by the thickness of the plating film. As a result, the thickness of the ceramic element body is further reduced, and thus the capacitance of the multilayer ceramic capacitor decreases.
Example embodiments of the present invention provide multilayer ceramic capacitors each including an external electrode that is able to reliably cover the surface of a base electrode layer with a plated layer.
The inventors of example embodiments of the present invention have discovered that deposition and growth of a plating film smoothly proceed by providing a region in which Sn is deposited on a surface of a base electrode layer of an external electrode.
An example embodiment of the present invention provides a multilayer ceramic capacitor that includes a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately laminated, and external electrodes each on a corresponding one of two end surfaces opposed to each other in a length direction perpendicular or substantially perpendicular to a lamination direction of the multilayer body, the external electrodes each being connected to the plurality of internal electrode layers. Each of the external electrodes includes a stack including a base electrode layer on a corresponding one of the two end surfaces, a Ni plated layer on the base electrode layer, and a Sn plated layer on the Ni plated layer, and each of the external electrodes includes a region in which Sn is deposited between the base electrode layer and the Ni plated layer.
According to example embodiments of the present invention, it is possible to provide multilayer ceramic capacitors each including an external electrode that is able to reliably cover the surface of a base electrode layer with a plated layer.
The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the example embodiments with reference to the attached drawings.
Hereinafter, multilayer ceramic capacitors according to example embodiments of the present invention will be described. However, the present invention is not limited thereto. In addition, the drawings may be schematically simplified and drawn in order to explain the contents of example embodiments of the present invention, and the drawn components or the ratio of the dimensions between the components may not coincide with the ratio of the dimensions described in the specification. In addition, components described in the specification may be omitted in the drawings or may be drawn with the number of components omitted.
The multilayer ceramic capacitor 1 has a rectangular or substantially rectangular parallelepiped shape and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 6 including a plurality of sets of dielectric layers 4 and internal electrode layers 5.
Among the six outer surfaces of the multilayer body 2, a pair of outer surfaces opposed to each other in the lamination direction T is defined as a first main surface A1 and a second main surface A2, a pair of outer surfaces opposed to each other in the width direction W is defined as a first lateral surface B1 and a second lateral surface B2, and a pair of outer surfaces opposed to each other in the length direction L is defined as a first end surface C1 and a second end surface C2.
The first main surface A1 and the second main surface A2 are collectively referred to as a main surface A, the first lateral surface B1 and the second lateral surface B2 are collectively referred to as a lateral surface B, and the first end surface C1 and the second end surface C2 are collectively referred to as an end surface C.
The multilayer body 2 includes an inner layer portion 6, outer layer portions 7 that sandwich the inner layer portion 6 and are provided adjacent to the main surfaces A, and side gap portions 8. In the multilayer body 2, it is preferable that ridge portions E are rounded. Each of the ridge portions E refers to a portion where the two surfaces of the multilayer body 2, that is, the main surface A and the lateral surface B, the main surface A and the end surface C, or the lateral surface B and the end surface C intersect with each other, and also includes corner portions where the main surface A, the lateral surface B, and the end surface C intersect with each other.
The inner layer portion 6 includes a plurality of sets of dielectric layers 4 and internal electrode layers 5 alternately laminated along the lamination direction T.
Each of the dielectric layers 4 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic including BaTiO3 as a main component is used. Further, as the ceramic material, a material obtained by adding at least one subcomponent such as, for example, a Mn compound, a Fe compound, a Cr compound, a Co compound, and a Ni compound to these main components may be used.
Each of the internal electrode layers 5 is preferably made of a metal material such as, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.
The internal electrode layers 5 include a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layers 5A and the second internal electrode layers 5B are alternately provided. When it is not necessary to particularly distinguish between the first internal electrode layer 5A and the second internal electrode layer 5B, they are collectively described as the internal electrode layer 5.
Each of the internal electrode layers 5 includes a counter portion 52 that is opposed to each other between the first internal electrode layer 5A and the second internal electrode layer 5B, and an extension portion 51 that is not opposed to each other between the first internal electrode layer 5A and the second internal electrode layer 5B. Each of the extension portions 51 extends from the counter portion 52 toward a corresponding one of the end surfaces C, and is exposed at a corresponding one of the end surfaces C. Each of the extension portions 51 includes an end portion that is exposed at the end surface C and is electrically connected to the external electrode 3. The directions in which the extension portions 51 extend differ between the first internal electrode layers 5A and the second internal electrode layers 5B, and the extension portions extend alternately toward the first end surface C1 and the second end surface C2 and are exposed at them. Charges are accumulated between the counter portions 52 of the first internal electrode layers 5A and the second internal electrode layers 5B adjacent to one another in the lamination direction T, and define and function as a capacitor.
The outer layer portions 7 sandwich the inner layer portion 6 and are provided adjacent to both main surfaces A. The outer layer portions 7 are made of the same material as the dielectric layers 4 of the inner layer portion 6.
The side gap portions 8 sandwich the inner layer portion 6 and are provided adjacent to both lateral surfaces B of the multilayer body 2. The side gap portion 8 is integrally made of the same material as the dielectric layers 4.
The external electrodes 3 are provided on both end surfaces C of the multilayer body 2. Each of the external electrodes 3 covers not only the end surface C, but also a portion of the main surface A and a portion of the lateral surface B adjacent to the end surface C. Each of the external electrodes 3 includes a base electrode layer 30 and a plated layer 31 provided on the surface of the base electrode layer 30.
The base electrode layer 30 is electrically connected to each of the end portions of the extension portions 51 of the internal electrode layers 5 exposed at the end surface C. The base electrode layer preferably includes an electrically conductive metal and either glass or ceramic, or both glass and ceramic. In the present example embodiment, the base electrode layer 30 includes an electrically conductive metal and glass, for example. With such a configuration, the adhesion between the end surface C of the multilayer body 2 and the base electrode layer 30 is improved, and infiltration of moisture into the multilayer body 2 can be reduced or prevented.
The electrically conductive metal for manufacturing the base electrode layer includes, for example, at least one of Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.
The glass for manufacturing the base electrode layer 30 includes at least one of B, Si, Ba, Mg, Al, or Li, or the like. In a case of including a ceramic component, a ceramic component of the same type as the dielectric layer or a ceramic component of a different type may be used as the ceramic component.
A region R in which Sn is deposited is provided on the surface of the electrically conductive metal exposed on the surface of the base electrode layer 30. The region R is provided, for example, by depositing Sn, an alloy of Sn and Ni, or the like by an electroless plating method or the like described later.
The plated layer 31 includes, for example, a Ni plated layer 31a provided so as to cover the surface of the base electrode layer 30 and the region R, and a Sn plated layer 31b provided so as to cover the Ni plated layer 31a. The Ni plated layer 31a is formed by, for example, plating Ni or an alloy including Ni. The Ni plated layer 31a prevents the base electrode layer 30 from being eroded by solder. The Sn plated layer 31b is formed by, for example, plating Sn or an alloy including Sn. The formation of the Sn plated layer 31b improves the wettability of solder when the multilayer ceramic capacitor 1 is mounted on a wiring board, which facilitates mounting.
The molar ratio of Sn to Ni (Sn/Ni) in the region R measured by energy dispersive X-ray spectroscopy (EDX) is, for example, preferably about 0.2 or more and about 0.4 or less. By providing the region R with such a molar ratio (Sn/Ni), it is possible to stably provide the region R during mass production, and it is also possible to smoothly laminate the Ni plated layer 31a on the surface of the base electrode layer 30.
Next, an example of a method of manufacturing the multilayer ceramic capacitor 1 according to the present example embodiment will be described.
First, in the multilayer body manufacturing step S1, a material sheet is prepared in which a pattern of the internal electrode layers 5 is printed with an electrical conductor paste on a ceramic green sheet for lamination in which a ceramic slurry is formed into a sheet shape. Then, the plurality of material sheets are laminated so that the internal electrode patterns are shifted by about a half pitch in the length direction between the adjacent material sheets. Further, ceramic green sheets for manufacturing the outer layer portions are laminated on both sides of the plurality of laminated material sheets, respectively, and the resulting product is subjected to, for example, thermocompression bonding to form a mother block member. A plurality of multilayer chips are manufactured by dividing the mother block member along cutting lines corresponding to the dimensions of the multilayer body. Thereafter, the multilayer chip is, for example, barrel-polished to round corner portions and ridge portions, and then fired. Thus, the ceramic material and the metal material included in the multilayer chip are fired to form the multilayer body 2 including the plurality of dielectric layers 4 and the plurality of internal electrode layers 5.
Next, in the base electrode layer forming step S2, the base electrode layer 30 is formed on both end portions of the multilayer body 2. The base electrode layer 30 is formed by, for example, applying an electrically conductive paste including an electrically conductive metal and glass to both end portions of the multilayer body 2, and firing the resulting product. The base electrode layer may be formed by simultaneously firing the multilayer chip and the electrically conductive paste applied to the multilayer chip, or may be formed by firing the multilayer chip to obtain the multilayer body 2, and then applying the electrically conductive paste to the multilayer body 2 and firing the resulting product. As shown in
The region R can be formed by, for example, electroless
plating by immersion. The multilayer body 2 on which the base electrode layers 30 are formed is immersed in a plating bath to deposit Sn on the surfaces of the electrically conductive metal exposed on the surfaces of the base electrode layers 30. The metal to be deposited may not only be Sn, but, for example, also an alloy of Sn and Ni. These metals are supplied as cationic species in the plating bath. In the plating bath, although both the metal salt and the reducing agent are present in the bath, the metal layer is deposited by the action of the reducing agent added to the aqueous solution of the metal salt and covers the surfaces of the electrically conductive metal exposed on the surfaces of the base electrode layers. The region R can also be formed by, for example, electrolytic plating or other plating.
In the Ni plated layer forming step S3, the Ni plated layer 31a is formed to cover the surface of each of the base electrode layers 30 in which the region R is formed. The Ni plated layer 31a is preferably formed by, for example, electrolytic plating. Barrel plating, for example, can be used as the plating method.
Sn Plated Layer Forming Step S5
Next, the Sn plated layer 31b is formed to cover the Ni plated layer 31a. The Sn plated layer 31b is preferably formed by, for example, electrolytic plating. Barrel plating, for example, can be used as the plating method.
Through the above steps, the multilayer ceramic capacitor 1 in which the external electrodes 3 are formed on the multilayer body 2 is manufactured.
While example embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-139915 | Sep 2022 | JP | national |
This application claims the benefit of priority to Japanese Patent Application No. 2022-139915 filed on Sep. 2, 2022 and is a Continuation Application of PCT Application No. PCT/JP2023/020144 filed on May 30, 2023. The entire contents of each application are hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/020144 | May 2023 | WO |
| Child | 18760090 | US |
