Clock circuits details

Industry

CPC
G01R31/318552

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318552Clock circuits details

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Test-time optimization with few slow scan pads
- Patent number 12,203,985
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 12,203,984
- Issue date Jan 21, 2025
- STMicroelectronics S.r.l.
- Marco Casarsa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data correction and phase optimization in high-speed receivers
- Patent number 12,181,523
- Issue date Dec 31, 2024
- Diodes Incorporated
- Yu-Wei Lin
- G01 - MEASURING TESTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Registers
- Patent number 12,158,499
- Issue date Dec 3, 2024
- Nordic Semiconductor ASA
- Matti Samuli Leinonen
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Clock gating circuits and methods for dual-edge-triggered applications
- Patent number 12,146,912
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
Calibration data generation circuit and associated method
- Patent number 12,032,020
- Issue date Jul 9, 2024
- Realtek Semiconductor Corporation
- Chun-Yi Kuo
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,025,649
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Power-sensitive scan-chain testing
- Patent number 12,025,661
- Issue date Jul 2, 2024
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Detection system for SlimSAS slot and method thereof
- Patent number 11,953,549
- Issue date Apr 9, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Kai Zou
- G01 - MEASURING TESTING
Information Patent Grant
Hold time improved low area flip-flop architecture
- Patent number 11,946,973
- Issue date Apr 2, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
Using scan chains to read out data from integrated sensors during s...
- Patent number 11,921,160
- Issue date Mar 5, 2024
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,899,064
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Ring transport employing clock wake suppression
- Patent number 11,829,196
- Issue date Nov 28, 2023
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built in self test (BIST) for clock generation circuitry
- Patent number 11,821,946
- Issue date Nov 21, 2023
- NXP USA, INC.
- Jorge Arturo Corso Sarmiento
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split-scan sense amplifier flip-flop
- Patent number 11,789,075
- Issue date Oct 17, 2023
- Advanced Micro Devices, Inc.
- Nur Mohammad Baksh
- G01 - MEASURING TESTING
Information Patent Grant
Scan test device and scan test method
- Patent number 11,789,073
- Issue date Oct 17, 2023
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Pseudo-random binary sequences (PRBS) generator for performing on-c...
- Patent number 11,774,496
- Issue date Oct 3, 2023
- INDIAN INSTITUTE OF TECHNOLOGY
- Mahendra Sakare
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for timing-annotated scan-chain testing using...
- Patent number 11,768,239
- Issue date Sep 26, 2023
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
3D TAP and scan port architectures
- Patent number 11,762,014
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 11,747,398
- Issue date Sep 5, 2023
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device and semiconductor device examination method
- Patent number 11,740,287
- Issue date Aug 29, 2023
- Kioxia Corporation
- Isao Ooigawa
- G01 - MEASURING TESTING
Information Patent Grant
Localization of multiple scan chain defects per scan chain
- Patent number 11,740,288
- Issue date Aug 29, 2023
- Synopsys, Inc.
- Emil I. Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,726,135
- Issue date Aug 15, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for scan testing
- Patent number 11,714,131
- Issue date Aug 1, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Transition fault testing of functionally asynchronous paths in an i...
- Patent number 11,709,203
- Issue date Jul 25, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Signal toggling detection and correction circuit
- Patent number 11,686,769
- Issue date Jun 27, 2023
- NXP B.V.
- Shikhar Makkar
- G01 - MEASURING TESTING
Information Patent Grant
Falling clock edge JTAG bus routers
- Patent number 11,680,985
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING
- Publication number 20250027992
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G01 - MEASURING TESTING
Information Patent Application
TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS
- Publication number 20250027994
- Publication date Jan 23, 2025
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20250027995
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSION-BASED SCAN TEST SYSTEM
- Publication number 20240393393
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20240361384
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
SCAN CLOCK GATING CONTROLLER AND METHOD FOR PERFORMING STUCK-AT FAU...
- Publication number 20240353489
- Publication date Oct 24, 2024
- Realtek Semiconductor Corp.
- Dong-Zhen Li
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING MULTI-CYCLE PATHS USING SCAN TEST
- Publication number 20240329135
- Publication date Oct 3, 2024
- ADVANCED MICRO DEVICES, INC.
- James A. Wingfield
- G01 - MEASURING TESTING
Information Patent Application
HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE
- Publication number 20240210472
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
META-STABILITY-FREE TWO-CLOCK-DOMAIN SYNCHRONOUS LATCH
- Publication number 20240146285
- Publication date May 2, 2024
- VIETTEL GROUP
- Thai Ha Le
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20240133951
- Publication date Apr 25, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORA...
- Publication number 20240112713
- Publication date Apr 4, 2024
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. ALAM
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME
- Publication number 20240110979
- Publication date Apr 4, 2024
- MEDIATEK INC.
- Anshul Varma
- G01 - MEASURING TESTING
Information Patent Application
REGISTERS
- Publication number 20240003971
- Publication date Jan 4, 2024
- NORDIC SEMICONDUCTOR ASA
- Matti Samuli Leinonen
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
USING SCAN CHAINS TO READ OUT DATA FROM INTEGRATED SENSORS DURING S...
- Publication number 20230393199
- Publication date Dec 7, 2023
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE AND SCAN TESTING METHOD
- Publication number 20230384378
- Publication date Nov 30, 2023
- RENESAS ELECTRONICS CORPORATION
- Yucong ZHANG
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BUILDING DATA PLATFORM WITH DIGITAL TWIN DIAGNOSTICS
- Publication number 20230359176
- Publication date Nov 9, 2023
- Johnson Controls Tyco IP Holdings LLP
- Rajiv Ramanasankaran
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD
- Publication number 20230358806
- Publication date Nov 9, 2023
- STMicroelectronics S.r.l.
- Marco CASARSA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS
- Publication number 20230314510
- Publication date Oct 5, 2023
- Diodes Incorporated
- Yu-Wei Lin
- G01 - MEASURING TESTING
Information Patent Application
CALIBRATION DATA GENERATION CIRCUIT AND ASSOCIATED METHOD
- Publication number 20230236246
- Publication date Jul 27, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- CHUN-YI KUO
- G01 - MEASURING TESTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20230221368
- Publication date Jul 13, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SIGNAL TOGGLING DETECTION AND CORRECTION CIRCUIT
- Publication number 20230213580
- Publication date Jul 6, 2023
- NXP B.V.
- Shikhar Makkar
- G01 - MEASURING TESTING
Information Patent Application
Data Gating Using Scan Enable Pin
- Publication number 20230194606
- Publication date Jun 22, 2023
- Apple Inc.
- FNU Rajeev Kumar
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Clock circuits details

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test-time optimization with few slow scan pads

Scan chain circuit and corresponding method

Data correction and phase optimization in high-speed receivers

3D tap and scan port architectures

Registers

Commanded JTAG test access port operations

TVF transition coverage with self-test and production-test time red...

Clock gating circuits and methods for dual-edge-triggered applications

Calibration data generation circuit and associated method

Integrated circuit die test architecture

Power-sensitive scan-chain testing

Detection system for SlimSAS slot and method thereof

Hold time improved low area flip-flop architecture

Using scan chains to read out data from integrated sensors during s...

Scan architecture for interconnect testing in 3D integrated circuits

Ring transport employing clock wake suppression

Built in self test (BIST) for clock generation circuitry

Split-scan sense amplifier flip-flop

Scan test device and scan test method

Pseudo-random binary sequences (PRBS) generator for performing on-c...

Method and apparatus for timing-annotated scan-chain testing using...

3D TAP and scan port architectures

Scan chain circuit and corresponding method

Semiconductor device and semiconductor device examination method

Localization of multiple scan chain defects per scan chain

Integrated circuit die test architecture

Circuit and method for scan testing

Transition fault testing of functionally asynchronous paths in an i...

Signal toggling detection and correction circuit

Falling clock edge JTAG bus routers

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

COMPRESSION-BASED SCAN TEST SYSTEM

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

SCAN CLOCK GATING CONTROLLER AND METHOD FOR PERFORMING STUCK-AT FAU...

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

TESTING MULTI-CYCLE PATHS USING SCAN TEST

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

META-STABILITY-FREE TWO-CLOCK-DOMAIN SYNCHRONOUS LATCH

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORA...

DYNAMIC VOLTAGE FREQUENCY SCALING TO REDUCE TEST TIME

REGISTERS

3D TAP & SCAN PORT ARCHITECTURES

USING SCAN CHAINS TO READ OUT DATA FROM INTEGRATED SENSORS DURING S...

SEMICONDUCTOR DEVICE AND SCAN TESTING METHOD

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

BUILDING DATA PLATFORM WITH DIGITAL TWIN DIAGNOSTICS

SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD

FALLING CLOCK EDGE JTAG BUS ROUTERS

DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS

CALIBRATION DATA GENERATION CIRCUIT AND ASSOCIATED METHOD

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

SIGNAL TOGGLING DETECTION AND CORRECTION CIRCUIT

Data Gating Using Scan Enable Pin

3D TAP & SCAN PORT ARCHITECTURES