Multiplier and arithmetic unit

Abstract

A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand. The effective figures depend on the format of the multiplier and the multiplicand. The partial product control circuit controls the status of the enable signal according to a multiplication command designating the format. The multiplication array is constituted by a dynamic circuit. The dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal. When the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the configuration of a vector multiplier according to an embodiment of the present invention;

FIG. 2 is a diagram for explaining a multiplication circuit according to the embodiment of the present invention;

FIG. 3 is a diagram schematically showing a 64-bit fixed-point format;

FIG. 4 is a diagram schematically showing a multiplication array in the case of 64-bit fixed-point multiplication;

FIG. 5 is a diagram schematically showing a 32-bit fixed-point format;

FIG. 6 is a diagram schematically showing a multiplication array in the case of 32-bit fixed-point multiplication;

FIG. 7 is a diagram schematically showing a double-precision floating-point format;

FIG. 8 is a diagram schematically showing a multiplication array in the case of double-precision floating-point multiplication;

FIG. 9 is a diagram schematically showing a single-precision floating-point format;

FIG. 10 is a diagram schematically showing a multiplication array in the case of single-precision floating-point multiplication;

FIG. 11 is a diagram showing an enable signal according to the embodiment;

FIG. 12 is a circuit diagram showing the configuration of a dynamic circuit in an initial stage of the multiplication array; and

FIG. 13 is a block diagram showing the configuration of a vector-operation arithmetic unit according to the embodiment of the present invention.

Claims

1. A multiplier comprising: a multiplication array in which partial products are generated by performing multiplication between an n-bit multiplier (n: a natural number) and an n-bit multiplicand;an adder which adds the generated partial products together; anda partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand,wherein the effective figures depend on a format of the multiplier and the multiplicand, and the partial product control circuit controls a status of the enable signal according to a multiplication command designating the format.

2. The multiplier according to claim 1, wherein the multiplication array is constituted by a dynamic circuit; the dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal; and, when the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.

3. The multiplier according to claim 1, wherein the enable signal comprises a first enable signal by which a first region in the multiplication array is activated and a second enable signal by which a second region in the multiplication array is activated; if the format of the multiplier and the multiplicand is a first format, the effective region is the first region and the partial product control circuit sets the first enable signal effective and sets the second enable signal ineffective; and, if the format of the multiplier and the multiplicand is a second format, the effective region is the first region and the second region and the partial product control circuit sets the first and second enable signals effective.

4. The multiplier according to claim 1, wherein the format comprises a single-precision floating-point form, a double-precision floating-point form, a 32-bit fixed-point format and a 64-bit fixed-point form.

5. The multiplier according to claim 1, further comprising a mask register storing a mask bit designating effectiveness/ineffectiveness of the multiplication, wherein the partial product control circuit controls the status of the enable signal on the basis of the multiplication command and the mask bit, and sets the entire enable signal ineffective if the mask bit designates ineffectiveness.

6. The multiplier according to claim 5, further comprising: a first register in which a first operand is stored;a second register in which a second operand is stored;a first preprocessing circuit; anda second preprocessing circuit,wherein the first preprocessing circuit divides the first operand into an exponential part and a mantissa part according to the multiplication command, and outputs the mantissa part of the first operand as the multiplier to the multiplication array; and the second preprocessing circuit divides the second operand into an exponential part and a mantissa part according to the multiplication command, and outputs the mantissa part of the second operand as the multiplicand to the multiplication array.

7. The multiplier according to claim 6, wherein the first register, the second register and the mask register are vector registers in which vector data is stored; the first operand is each of items of first vector data stored in the first register; the second operand is each of items of second vector data stored in the second register; and the mask bit is each of items of vector mask data stored in the mask register and associated with the first operand and the second operand.

8. The multiplier according to claim 6, further comprising a selection circuit which receives an output from the adder and the mask bit, wherein the selection circuit generates result data indicating the result of multiplication between the first operand and the second operand on the basis of the output from the adder, and sets a value of the result data to 0 if the mask bit designates ineffectiveness.

9. The multiplier according to claim 8, wherein the adder comprises a fixed-point adder which adds together the partial products in fixed-point form, and a floating-point adder which adds together the partial products in floating-point form, wherein the selection circuit further receives the multiplication command, selects one of outputs from the fixed-point adder and the floating-point adder according to the multiplication command if the mask bit designates effectiveness, and generates the result data on the basis of the selected output.

10. A multiplier comprising: a multiplication array which is constituted by a dynamic circuit, and in which partial products are generated by performing multiplication between a multiplier and a multiplicand;an adder which adds the generated partial products together;a mask register storing a mask bit designating effectiveness/ineffectiveness of the multiplication; anda partial product control circuit which controls the status of an enable signal for activating the multiplication array on the basis of the mask bit,wherein the partial product control circuit sets the enable signal ineffective if the mask bit designates ineffectiveness; the dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal; and, when the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.

11. The multiplier according to claim 10, further comprising: a first register in which a first operand is stored;a second register in which a second operand is stored;a first preprocessing circuit which outputs a mantissa part of the first operand as the multiplier to the multiplication array; anda second preprocessing circuit which outputs a mantissa part of the second operand as the multiplicand to the multiplication array,wherein the first register, the second register and the mask register are vector registers in which vector data is stored; the first operand is each of items of first vector data stored in the first register; the second operand is each of items of second vector data stored in the second register; and the mask bit is each of items of vector mask data stored in the mask register and associated with the first operand and the second operand.

12. An arithmetic unit comprising: a first register in which a first operand is stored;a second register in which a second operand is stored;an arithmetic device which performs an operation by using the first operand and the second operand; andan operation control circuit which generates an enable signal for activating an effective region in the arithmetic device corresponding to effective figures of the first operand and the second operand,wherein the effective figures depend on the format of the first operand and the second operand, and the operation control circuit controls the status of the enable signal according to an operation command designating the format.

13. The arithmetic unit according to claim 12, wherein the arithmetic device is constituted by a dynamic circuit; the dynamic circuit in an initial stage of the arithmetic device has a switch which is turned on/off by the enable signal; and, when the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.

14. The arithmetic unit according to claim 12, further comprising a mask register storing a mask bit designating effectiveness/ineffectiveness of the operation, wherein the operation control circuit controls the status of the enable signal on the basis of the operation command and the mask bit, and sets the enable signal ineffective if the mask bit designates ineffectiveness.

15. The arithmetic unit according to claim 14, wherein the first register, the second register and the mask register are vector registers in which vector data is stored; the first operand is each of items of first vector data stored in the first register; the second operand is each of items of second vector data stored in the second register; and the mask bit is each of items of vector mask data stored in the mask register and associated with the first operand and the second operand.