Precharge of output to prevent leakage

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G06F2207/3872

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F2207/3872Precharge of output to prevent leakage

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Patents Grantslast 30 patents

Information Patent Grant
Arithmetic circuit and method of driving the same
- Patent number 10,090,333
- Issue date Oct 2, 2018
- Semiconductor Energy Laboratory Co., Ltd.
- Kiyoshi Kato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused booth encoder multiplexer
- Patent number 9,274,751
- Issue date Mar 1, 2016
- International Business Machines Corporation
- Wendy Ann Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast dynamic register with transparent latch
- Patent number 8,860,463
- Issue date Oct 14, 2014
- Via Technologies, Inc.
- Imran Qureshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Arithmetic circuit and method of driving the same
- Patent number 8,779,798
- Issue date Jul 15, 2014
- Semiconductor Energy Laboratory Co., Ltd.
- Kiyoshi Kato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused booth encoder multiplexer
- Patent number 8,229,992
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Wendy Ann Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier and arithmetic unit
- Patent number 8,041,758
- Issue date Oct 18, 2011
- NEC Computer Techno, Ltd.
- Takashi Osada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic unit of arbitrary precision, operation method for proces...
- Patent number 7,844,654
- Issue date Nov 30, 2010
- Seiko Epson Corporation
- Nobuo Karaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for converting, and adder circuit
- Patent number 7,613,763
- Issue date Nov 3, 2009
- Infineon Technologies AG
- Astrid Elbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric cascaded domino carry generate circuit
- Patent number 7,428,568
- Issue date Sep 23, 2008
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder structure with midcycle latch for power reduction
- Patent number 7,406,495
- Issue date Jul 29, 2008
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascaded domino four-to-two reducer circuit and method
- Patent number 7,392,277
- Issue date Jun 24, 2008
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure and fast calculating unit
- Patent number 7,282,983
- Issue date Oct 16, 2007
- Infineon Technologies AG
- Norbert Janssen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused booth encoder multiplexer
- Patent number 7,272,624
- Issue date Sep 18, 2007
- International Business Machines Corporation
- Wendy Ann Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing addition of PKG recoded numbers
- Patent number 7,231,414
- Issue date Jun 12, 2007
- Hewlett-Packard Development Company, L.P.
- Glenn T Colon-Bonet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid carry look ahead/carry select adder including carry logic ge...
- Patent number 7,206,802
- Issue date Apr 17, 2007
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed, universal polarity full adder which consumes minimal po...
- Patent number 7,185,042
- Issue date Feb 27, 2007
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priority circuit
- Patent number 7,106,608
- Issue date Sep 12, 2006
- Matsushita Electric Industrial Co., Ltd.
- Yorimasa Funahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic adder with reduced logic
- Patent number 7,085,796
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Stephen V. Kosonocky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wide adder with critical path of three gates
- Patent number 6,990,510
- Issue date Jan 24, 2006
- International Business Machines Corporation
- David Michael Friend
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ultra-fast adder
- Patent number 6,957,245
- Issue date Oct 18, 2005
- Sun Microsystems, Inc.
- Honkai Tam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sense-amp based adder with source follower evaluation tree
- Patent number 6,789,099
- Issue date Sep 7, 2004
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a hazard-free multi-bit comparison
- Patent number 6,765,410
- Issue date Jul 20, 2004
- Sun Microsystems, Inc.
- Thomas L. Meneghini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic popcount/shift circuit
- Patent number 6,754,685
- Issue date Jun 22, 2004
- Sun Microsystems, Inc.
- Matthew E. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zipper domino carry generate cell for fast adders
- Patent number 6,580,294
- Issue date Jun 17, 2003
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a 5:2 carry-save-adder (CSA)
- Patent number 6,567,835
- Issue date May 20, 2003
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
6-to-3 carry-save adder
- Patent number 6,345,286
- Issue date Feb 5, 2002
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing noise tolerance in dynamic silic...
- Patent number 6,326,814
- Issue date Dec 4, 2001
- International Business Machines Corporation
- Daniel Lawrence Stasiak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamic partitionable saturating adder/sub...
- Patent number 6,301,600
- Issue date Oct 9, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for saturation in an N-NARY adder/subtractor
- Patent number 6,301,597
- Issue date Oct 9, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous sensing differential logic (ASDL) circuit
- Patent number 6,211,704
- Issue date Apr 3, 2001
- Hyundai Electronics Industries Co., Ltd.
- Bai-Sun Kong
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCANNABLE FAST DYNAMIC REGISTER
- Publication number 20140320188
- Publication date Oct 30, 2014
- VIA TECHNOLOGIES, INC.
- Imran Qureshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST DYNAMIC REGISTER WITH TRANSPARENT LATCH
- Publication number 20140320164
- Publication date Oct 30, 2014
- VIA TECHNOLOGIES, INC.
- Imran Qureshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME
- Publication number 20140284600
- Publication date Sep 25, 2014
- Kiyoshi Kato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME
- Publication number 20120297220
- Publication date Nov 22, 2012
- Semiconductor Energy Laboratory Co., Ltd.
- Kiyoshi KATO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED BOOTH ENCODER MULTIPLEXER
- Publication number 20080010333
- Publication date Jan 10, 2008
- International Business Machines Corporation
- Wendy Ann Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED BOOTH ENCODER MULTIPLEXER
- Publication number 20070244954
- Publication date Oct 18, 2007
- Wendy A. Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiplier and arithmetic unit
- Publication number 20070203964
- Publication date Aug 30, 2007
- NEC Corporation
- Takashi Osada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure and fast calculating unit
- Publication number 20070063742
- Publication date Mar 22, 2007
- Infineon Technologies AG
- Norbert Janssen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Carry-ripple adder
- Publication number 20060294178
- Publication date Dec 28, 2006
- Marc Bernhardt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arithmetic unit of arbitrary precision, operation method for proces...
- Publication number 20060106903
- Publication date May 18, 2006
- SEIKO EPSON CORPORATION
- Nobuo Karaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for converting, and adder circuit
- Publication number 20050193052
- Publication date Sep 1, 2005
- Infineon Technologies AG
- Astrid Elbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Novel adder structure with midcycle latch for power reduction
- Publication number 20050138103
- Publication date Jun 23, 2005
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fused booth encoder multiplexer
- Publication number 20050080834
- Publication date Apr 14, 2005
- International Business Machines Corporation
- Wendy Ann Belluomini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Priority circuit
- Publication number 20050066098
- Publication date Mar 24, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Yorimasa Funahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power adder circuit utilizing both static and dynamic logic
- Publication number 20040220994
- Publication date Nov 4, 2004
- Intel Corporation
- Sanu K. Mathew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sense-amp based adder with source follower evaluation tree
- Publication number 20040073592
- Publication date Apr 15, 2004
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid carry look ahead/carry select adder including carry logic ge...
- Publication number 20040073593
- Publication date Apr 15, 2004
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ultra-fast adder
- Publication number 20030145034
- Publication date Jul 31, 2003
- Honkai Tam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wide adder with critical path of three gates
- Publication number 20030140080
- Publication date Jul 24, 2003
- International Business Machines Corporation
- David Michael Friend
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symmetric cascaded domino carry generate circuit
- Publication number 20030126179
- Publication date Jul 3, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for performing a hazard-free multi-bit comparsion
- Publication number 20030117170
- Publication date Jun 26, 2003
- SUN MICROSYSTEMS, INC.
- Thomas L. Meneghini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZIPPER DOMINO CARRY GENERATE CELL FOR FAST ADDERS
- Publication number 20030112036
- Publication date Jun 19, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cascaded domino four-to-two reducer circuit and method
- Publication number 20030014459
- Publication date Jan 16, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic popcount/shift circuit
- Publication number 20020083106
- Publication date Jun 27, 2002
- Matthew E. Becker
- G06 - COMPUTING CALCULATING COUNTING

Precharge of output to prevent leakage

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Arithmetic circuit and method of driving the same

Fused booth encoder multiplexer

Fast dynamic register with transparent latch

Arithmetic circuit and method of driving the same

Fused booth encoder multiplexer

Multiplier and arithmetic unit

Arithmetic unit of arbitrary precision, operation method for proces...

Apparatus and method for converting, and adder circuit

Symmetric cascaded domino carry generate circuit

Adder structure with midcycle latch for power reduction

Cascaded domino four-to-two reducer circuit and method

Secure and fast calculating unit

Fused booth encoder multiplexer

Apparatus and method for performing addition of PKG recoded numbers

Hybrid carry look ahead/carry select adder including carry logic ge...

High speed, universal polarity full adder which consumes minimal po...

Priority circuit

Dynamic adder with reduced logic

Wide adder with critical path of three gates

Ultra-fast adder

Sense-amp based adder with source follower evaluation tree

Method and apparatus for performing a hazard-free multi-bit comparison

Dynamic popcount/shift circuit

Zipper domino carry generate cell for fast adders

Method and apparatus for a 5:2 carry-save-adder (CSA)

6-to-3 carry-save adder

Method and apparatus for enhancing noise tolerance in dynamic silic...

Method and apparatus for dynamic partitionable saturating adder/sub...

Method and apparatus for saturation in an N-NARY adder/subtractor

Asynchronous sensing differential logic (ASDL) circuit

Patents Applicationslast 30 patents

SCANNABLE FAST DYNAMIC REGISTER

FAST DYNAMIC REGISTER WITH TRANSPARENT LATCH

ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME

ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME

FUSED BOOTH ENCODER MULTIPLEXER

FUSED BOOTH ENCODER MULTIPLEXER

Multiplier and arithmetic unit

Secure and fast calculating unit

Carry-ripple adder

Arithmetic unit of arbitrary precision, operation method for proces...

Apparatus and method for converting, and adder circuit

Novel adder structure with midcycle latch for power reduction

Fused booth encoder multiplexer

Priority circuit

Low power adder circuit utilizing both static and dynamic logic

Sense-amp based adder with source follower evaluation tree

Hybrid carry look ahead/carry select adder including carry logic ge...

Ultra-fast adder

Wide adder with critical path of three gates

Symmetric cascaded domino carry generate circuit

Method and apparatus for performing a hazard-free multi-bit comparsion

ZIPPER DOMINO CARRY GENERATE CELL FOR FAST ADDERS

Cascaded domino four-to-two reducer circuit and method

Dynamic popcount/shift circuit