Claims
- 1. A NAND type compound semiconductor memory comprising:
- a substrate;
- a p type fifth semiconductor layer formed on said substrate,
- a first semiconductor layer formed on said fifth semiconductor layer, a channel being formed by said first semiconductor layer,
- a plurality of devices formed on said substrate and connected in series to one another, each device including,
- a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer,
- an n type third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer,
- a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer,
- a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel,
- a source electrode formed on the first semiconductor layer and electrically connected to said channel, and
- a drain electrode formed on the first semiconductor layer and electrically connected to said channel;
- a switch element, connected in series to the plurality of devices, for transferring an externally supplied potential to said devices, and
- a first control electrode electrically connected to said fifth semiconductor layer.
- 2. The semiconductor memory according to claim 1, wherein said second semiconductor layer has an impurity concentration of approximately 1.times.10.sup.17 to 1.times.10.sup.20 cm.sup.-3.
- 3. The semiconductor memory according to claim 2, wherein said fourth semiconductor layer has an impurity concentration of approximately 1.times.10.sup.10 to 1.times.10.sup.17 cm.sup.-3.
- 4. The semiconductor memory according to claim 1, wherein an electron affinity of said second semiconductor layer is substantially constant in a thickness direction of said second semiconductor layer.
- 5. A NOR type compound semiconductor memory comprising:
- a substrate;
- a first semiconductor layer formed on the substrate, a channel being formed by said first semiconductor layer,
- a plurality of devices formed on said first semiconductor layer and connected in series to one another, each device including,
- a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer,
- an n-type third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer,
- a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer,
- a gate electrode, formed on said fourth semiconductor layer and electrically connected to said channel,
- a source electrode, formed on said first semiconductor layer and electrically connected to said channel, and
- a drain electrode, formed on said first semiconductor layer and electrically connected to said channel; and
- a switch element, connected in series to said plurality of devices, for transferring an externally supplied potential to said devices,
- a plurality of series circuits, each comprising said plurality of devices and said switch element connected in series being arranged and connected in parallel to one another,
- wherein said second semiconductor layer has an impurity concentration of approximately 1.times.10.sup.17 to 1.times.10.sup.20 cm.sup.-3.
- 6. The semiconductor memory according to claim 5, wherein said fourth semiconductor layer has an impurity concentration of approximately 1.times.10.sup.10 to 1.times.10.sup.17 cm.sup.-3.
- 7. A NOR type compound semiconductor memory comprising:
- a substrate;
- a first semiconductor layer formed on the substrate, a channel being formed by said first semiconductor layer,
- a plurality of devices formed on said first semiconductor layer and connected in series to one another, each device including,
- a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer,
- an n-type third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer,
- a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer,
- a gate electrode, formed on said fourth semiconductor layer and electrically connected to said channel,
- a source electrode, formed on said first semiconductor layer and electrically connected to said channel, and
- a drain electrode, formed on said first semiconductor layer and electrically connected to said channel; and
- a switch element, connected in series to said plurality of devices, for transferring an externally supplied potential to said devices,
- a plurality of series circuits, each comprising said plurality of devices and said switch element connected in series, being arranged and connected in parallel to one another,
- wherein an electron affinity of said second semiconductor layer is substantially constant in a thickness direction of said second semiconductor layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-196082 |
Jul 1995 |
JPX |
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Parent Case Info
This is a divisional of application Ser. No. 08/677,347 filed Jul. 2, 1996.
US Referenced Citations (4)
Foreign Referenced Citations (3)
Number |
Date |
Country |
61-7666 |
Jan 1986 |
JPX |
2-35471 |
Feb 1990 |
JPX |
4-23476 |
Jan 1992 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
677347 |
Jul 1996 |
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