Patent Application
20250204269
The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to neuromorphic devices.
Modern developments in computing architecture for implementing artificial neural networks seek to move from the traditional von Neumann architecture to neuromorphic computing. Neuromorphic chips employ neuromorphic devices and are able to mimic the human brain to deal with complex tasks.
Current magnetic random access memory (MRAM) devices use a magnetic tunnel junction (MTJ) as a storage element. A simple MTJ is a tri-layer structure containing two magnetic layers separated by a tunnel barrier layer. The magnetic state of one of the layers is switched using Spin Transfer Torque (STT). Thus, current MRAMs are three-layer devices employing a magnetic tunnel junction (MTJ). They typically include a reference layer magnet, a tunnel barrier, and a storage or free magnetic layer. The magnetic layer can either be a ferromagnet or a ferrimagnet. Current is passed through the device and the resistance is measured. The resistance changes based on the magnetic orientation of the two magnetic layers, and the relative change in resistance is referred to as the tunnel magnetoresistance (TMR), which is related to the spin polarization (i.e., high spin polarization implies high TMR). High spin polarization, and thus high TMR, is desirable (higher TMR provides a higher ON/OFF ratio). Low switching current is also desirable.
In a parallel configuration (e.g., storing a zero), the magnetic layers have their magnetizations aligned with each other; the resistance is typically lower in this state relative to the anti-parallel configuration (e.g., storing a one). In the anti-parallel state, the magnetic layers do not have their magnetizations aligned with each other; the resistance is typically higher in this state relative to the parallel configuration. The magnetic state of the MTJ is changed by passing a current through it. The current delivers spin angular momentum, so that once a threshold current is exceeded, the direction of the memory layer moment is switched. Since these MRAM devices are switched using STT, they are referred to as STT-MRAM. The magnitude of the switching current that is required is less when the magnetization of the electrodes is oriented perpendicular to the layers. The magnetic layers have magnetization perpendicular to the film surface (i.e. have perpendicular magnetic anisotropy (PMA)) as smaller switching currents are needed than for in-plane magnetized MTJs. MTJs with magnetic layers having PMA need smaller switching current than for in-plane magnetized layers.
Current MRAM devices employ alloys of cobalt, iron, and boron for the magnetic layers and these layers are ferromagnetic (such current devices do not scale well to smaller sizes). Heusler compounds are magnetic intermetallics with a face-centered cubic (FCC) crystal structure and a composition of X2YZ (full-Heuslers or simply “Heuslers”), where X and Y are transition metals and Z is in the p-block (or main group) of the periodic table. Half Heuslers have the composition XYZ. Reference herein to Heusler or Heuslers without the term “half” is intended to reference full-Heuslers. Heusler compounds have four interpenetrating FCC sublattices. CoFeB devices typically rely on interfacial (surface) anisotropy for PMA, while Heusler compounds typically have volume anisotropy for PMA.
Recent work has shown that magnetic tunnel junctions can be used for neuromorphic operation as well as for MRAM (CoFeB-based MTJ devices have been demonstrated for neuromorphic applications).
Principles of the invention provide techniques for neuromorphic devices of Heusler alloy based spin-transfer-torque magnetic tunnel junctions. In one aspect, an exemplary neuromorphic computing array includes a plurality of horizontal lines; a plurality of vertical lines intersecting the plurality of horizontal lines at a plurality of cell locations; and a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations. Each of the magnetic tunnel junction cells is electrically connected to a corresponding one of the horizontal lines and to a corresponding one of the vertical lines. Each of the plurality of magnetic tunnel junction cells includes: a substrate; a seed layer overlying the substrate; a nitride layer, overlying the seed layer, and optionally having a thickness greater than 5 Angstroms; a templating layer, outward of the nitride layer, including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms; a magnetic layer overlying the templating layer, the magnetic layer including a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA); a tunnel barrier outward of the magnetic layer; and a magnetic layer outward of the tunnel barrier.
In another aspect a magnetic tunnel junction device includes a substrate; a seed layer overlying the substrate; a nitride layer, overlying the seed layer, and optionally having a thickness greater than 5 Angstroms; a templating layer, outward of the nitride layer, including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms; a magnetic layer overlying the templating layer, the magnetic layer including a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA); a tunnel barrier outward of the magnetic layer; and a magnetic layer outward of the tunnel barrier.
In still another aspect, a method of training a neuromorphic computing array includes: providing a neuromorphic computing array, as described; simultaneously applying input voltage signals along the plurality of horizontal lines during a forward training pass; obtaining output current signals along the plurality of vertical lines during the forward training pass; and applying input voltage signals, corresponding to difference between the output current signals and predicted values, along the plurality of vertical lines during a backward training pass.
In a further aspect, a method of forming a magnetic tunnel junction device includes providing a substrate; forming a seed layer overlying the substrate; forming a nitride layer, overlying the seed layer, and optionally having a nitride layer thickness greater than 5 Angstroms; providing a templating layer, outward of the nitride layer, and including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms; epitaxially growing a magnetic layer on the templating layer, the magnetic layer including a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA); forming a tunnel barrier outward of the magnetic layer; and forming a magnetic layer outward of the tunnel barrier.
In yet a further aspect, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium. The HDL design structure includes elements that when processed in a computer-aided design system generate a machine-executable representation of a magnetic tunnel junction device and/or a neuromorphic computing array, as described.
As used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on one processor might facilitate an action carried out by semiconductor processing equipment, by sending appropriate data or commands to cause or aid the action to be performed. Where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
Techniques as disclosed herein can provide substantial beneficial technical effects, as will be discussed further below. Features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
Principles of inventions described herein will be in the context of illustrative embodiments. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claims. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
Given the discussion herein (reference characters refer to the drawings discussed below), it will be appreciated that, in general terms, an exemplary magnetic tunnel junction device (e.g., for neuromorphic computing applications or other applications such as, e.g., FLASH memory) includes a substrate 1401; a seed layer 1403 overlying the substrate; a nitride layer 1403A, overlying the seed layer, and optionally having a thickness greater than 5 Angstroms; and a templating layer 1403B, outward of the nitride layer. The templating layer includes a binary alloy having an alternating layer lattice structure, and has a thickness greater than 50 Angstroms. Also included is a magnetic layer 1405 overlying the templating layer. The magnetic layer includes a Heusler compound and exhibits perpendicular magnetic anisotropy (PMA). A tunnel barrier 1409 is outward of the magnetic layer, and a magnetic layer 1411 is outward of the tunnel barrier. This provides the benefit of a Heusler-based MTJ device with multi-state Heusler based free layer ideal for neuromorphic applications.
In one or more embodiments, the device size is greater than 50 nm. As noted above, any of the MTJ devices fabricated from any of the structures described herein can be, for example, >50 nm in diameter, or even >60 nm in diameter, or even >80 nm in diameter, or even >90 nm in diameter, or even >100 nm in diameter (these are all non-limiting examples; see
In another aspect, a neuromorphic computing array includes a plurality of horizontal lines 1302; a plurality of vertical lines 1303 intersecting the plurality of horizontal lines at a plurality of cell locations; and a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations. Each of the magnetic tunnel junction cells is electrically connected to a corresponding one of the horizontal lines and to a corresponding one of the vertical lines. Each of the plurality of magnetic tunnel junction cells includes a magnetic tunnel junction device for neuromorphic computing applications as described. This provides the benefit of an array of Heusler-based MTJ devices with multi-state Heusler based free layer ideal for neuromorphic applications.
In one or more embodiments, each of the plurality of magnetic tunnel junction cells is directly coupled to the corresponding one of the horizontal lines and to the corresponding one of the vertical lines without the use of a transistor. This provides the benefit of simplicity.
One or more embodiments further include peripheral circuitry 1397 coupled to the plurality of horizontal lines and the plurality of vertical lines; a power supply 1395; and a controller 1393 coupled to the power supply and the peripheral circuitry. This provides the benefit of controlling operation of the array.
In one or more embodiments, the peripheral circuitry, the power supply, and the controller are cooperatively configured to: simultaneously apply input voltage signals along the plurality of horizontal lines during a forward training pass; obtain output current signals along the plurality of vertical lines during the forward training pass; and apply input voltage signals, corresponding to difference between the output current signals and predicted values, along the plurality of vertical lines during a backward training pass. This provides the benefit of carrying out processing with the array.
In a magnetic tunnel junction device, whether taken individually or as part of an array, in one or more embodiments, the layer that includes the Heusler compound is a free layer; and the magnetic layer is a pinned layer. The Heusler compound can, for example, be selected from the group consisting of Mn3Ge, Mn3Sn, Mn3Sb, Mn2CoSn, Mn2FeSb, Mn2CoAl, Mn2CoGe, Mn2CoSi, Mn2CuSi, Co2CrAl, Co2CrSi, Co2MnSb, and Co2MnSi. In one or more embodiments, the Heusler compound includes Mn3Ge. In one or more embodiments, the Heusler layer has a thickness of less than 5 nm.
In one or more embodiments, in the magnetic tunnel junction device, whether taken individually or as part of an array, the tunnel barrier is selected from the group consisting of magnesium oxide and magnesium aluminum oxide. In one or more embodiments, the tunnel barrier is magnesium oxide. In some instances, the tunnel barrier includes Mg1-zAl2+(2/3)zO4, wherein −0.5<z<0.5. In some instances, the binary alloy is represented by A1-xEx, wherein A is a transition metal element and E is a main group element including at least one of aluminum and gallium, and x is in the range from 0.42 to 0.55. In some cases, the binary alloy includes CoAl. These features provide the benefit of a tunnel barrier that can be fabricated with the MgO material and devices where multiple step characteristics can be tuned by adjusting the size and shape of the device and by type and thickness of the seed layer
In one or more embodiments, in the magnetic tunnel junction device, whether taken individually or as part of an array, the alternating layer lattice structure of the templating layer includes a cesium chloride structure. This provides the benefit of an effective seed layer.
Referring to
In another aspect, an exemplary method of training a neuromorphic computing array includes providing a neuromorphic computing array, as described. Further steps include simultaneously apply input voltage signals along the plurality of horizontal lines during a forward training pass; obtaining output current signals along the plurality of vertical lines during the forward training pass; and applying input voltage signals, corresponding to difference between the output current signals and predicted values, along the plurality of vertical lines during a backward training pass. This provides the benefit of training the array for effective operation.
In yet another aspect, referring to
It will be appreciated that the diffusion of the Heusler material's component atoms can be tuned or amplified by several methods: use of high temperature anneal; appropriate choice of seed layers, e.g. Ta/Ru/Ta instead of Ta; by external techniques such as ion bombardment, and the like. This provides the benefit of enabling fabrication of devices where multiple step characteristics can be tuned by adjusting the size and shape of the device and by type and thickness of the seed layer.
Typically, for neuromorphic computing applications, the capping layer 1415 of the device indicated in
In one or more embodiments, the templating layer has a templating layer in-plane lattice constant, and the Heusler in-plane lattice constant substantially matches the templating layer in-plane lattice constant. As used herein, the Heusler in-plane lattice constant “substantially matches” the templating layer in-plane lattice constant when it matches the templating layer in-plane lattice constant or when the in-plane lattice constant of the tetragonal Heusler material has moved towards the in-plane lattice constant of the templating material from the in-plane lattice constant of the cubic Heusler material. In some cases, the Heusler in-plane lattice constant matches the templating layer in-plane lattice constant within +/−10%. In some cases, the Heusler in-plane lattice constant matches the templating layer in-plane lattice constant within +/−5%. The half metallic Heusler material has, for example, a magnetization substantially perpendicular to the half metallic Heusler layer. When magnetic layers have magnetization perpendicular to the film surface (i.e. have perpendicular magnetic anisotropy (PMA)), smaller switching currents are needed than for in-plane magnetized MTJs.
Techniques as disclosed herein can provide substantial beneficial technical effects. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. By way of example only and without limitation, one or more embodiments may provide one or more of:
It is worth noting that current MRAM devices use magnetic tunnel junction (MTJ) as a storage element. A simple MTJ is a tri-layer structure containing two magnetic layers separated by tunnel barrier layer. Current MTJs using Cobalt Iron Boron (Co/Fe/B) are able to provide magnetic layers which have magnetization perpendicular to the film surface (i.e. exhibit perpendicular magnetic anisotropy (PMA), which is desirable). The perpendicular magnetic anisotropy (PMA) of Co—Fe—B layers arises from the interfaces between these layers and the tunnel barrier and/or the underlayer on which the Co—Fe—B layer is deposited.
It is also worth noting that, for MRAM, it is desirable that magnetic materials have volume PMA rather than surface (interfacial) PMA, as this enables scaling of devices to smaller sizes (typically smaller diameter). As device size is reduced, the devices become less thermally stable. However, for devices with volume anisotropy, it is advantageously possible to compensate for the lowering of thermal stability by increasing the magnetic layer thickness. The switching current is proportional to the product (Ms V Hk) where Ms is saturation magnetization, V is volume, and Hk is the anisotropy field. Low moment (i.e., low Ms) Heusler compounds need lower switching currents than high moment materials (such as CoFe alloys) with the same thermal energy barrier, unless the increase in Hk overwhelms the lower Ms.
Typically, Heusler compounds tend to be cubic. Thus, for a thin film of cubic Heusler the magnetic moment will be in the plane of the layer. For an MTJ for MRAM applications, it is highly desirable for the magnetic moments of the magnetic layer to be perpendicular to the layer.
We have found that Heusler compounds can be grown on an underlayer (e.g., CoAl) for use in MRAM applications.
One or more embodiments make use of a templating layer (in a non-limiting example, a chemical templating layer (CTL)). Referring to
Referring to the crystal structure in
Referring now to
The in-plane lattice constant of the Heusler compound is similar to that of the CoAl CTL. It is possible to strain the Heusler to a differing extent with an appropriate choice of CTL. We have found that even ternary Heusler compounds can be ordered by the CTL. As illustrated, the Mn (generally, X) grows on the Al and the Ge (generally, Z) grows on the Co. Note the atomic step 405. The Heusler material can be strained and thus adopts the in-plane lattice constant of the template material. One or more embodiments impose the lattice constant of the templating layer onto the Heusler layer. In view 423, note that CoAl 401 includes Al layers 409 and Co layers 411 and the MnSb 403 includes MnMn layer 413 and MnSb layer 415. Note the MgO tunnel barrier 407. The three most prominent tetragonal Heusler compounds are Mn3Ge, Mn3Sn, and Mn3Sb, and Mn3Sb has a larger difference in atomic number between Mn and Sb and thus is easier to see in the TEM image 423.
As noted, recent work has shown that magnetic tunnel junctions can be used for neuromorphic operation as well as for MRAM. Referring to
We have found that intermediate states can be observed in Heusler free layer stacks on Si substrates. Referring to
Refer now to
Sample 1 (square data points): 50 Å Ta, 250 Å Ru, 100 Å Ta, 5 Å (CoFe)80B20, 200 Å MnxN, 4 Å MgO, 150 Å CoAl, 50 Å IrAl, 150 Å CoAl, 20.5 Å Mn3Ge annealed at 342° C., 12.5 Å MgO, 6 Å (CoFe)70B30-6.5 Å (CoFe)80B20, 2.9 Å Ta, SAF, 100 Å Ru.
Sample 2 (circle data points): 50 Å Ta, 250 Å Ru, 100 Å Ta, 5 Å (CoFe)80B20, 300 Å MnxN, 850 Å CoAl, 50 Å IrAl, 150 Å CoAl, 17 Å Mn3Ge annealed at 342° C., 12.5 Å MgO, 6 Å (CoFe)70B30-26 Å (CoFe)80B20, 3.0 Å MgO, 4 Å Ta (IBE clean), SAF, 100 Å Ru.
Sample 3 (triangle data points): 50 Å Ta, 250 Å Ru, 100 Å Ta, 5 Å (CoFe)80B20, 300 Å MnxN, 650 Å CoAl, 50 Å IrAl, 150 Å CoAl, 19 Å Mn3Ge annealed at 342° C., 11.5 Å MgO, 6 Å (CoFe)70B30-7.5 Å (CoFe)80B20, 2.8 Å Ta, SAF, 100 Å Ru.
Referring to
Refer now to
Input voltage signals are applied along the horizontal lines (e.g., 1302) simultaneously. This corresponds to the forward pass. According to the Ohm's law and Kirchhoff's law, the output current signals are obtained through the vertical lines (e.g. 1303) by multiplication of input voltage with the weights (tunneling conductances), as indicated in summation 1399. This process updates the weights by spin-transfer-torque. The outputs are compared with the predicted numbers. The difference between the outputs and the predicted numbers is applied in voltage through the vertical lines. This corresponds to the backward pass. During the backward pass, the weights are updated as well by spin-transfer-torque. A large array of memory devices can be implemented on a single chip. An arbitrarily large number of cells can be employed, within the limits of the manufacturing processes and design specifications.
Referring again to summation 1399, synaptic weights Wjk are represented by MTJ tunnel conductance Gjk. and the weights are updated by backpropagation feedbacks (machine learning from the deep neural networks). By repeating these processes, the neural networks become trained such that the outputs are close to the predicted ones. Once training is complete, the trained array can be used to carry out inferencing.
One or more embodiments include appropriate peripheral circuitry 1397 and a suitable controller 1393 and power supply 1395 (can be controlled by the controller to supply appropriate voltages as described, can be part of controller 1393 or a separate unit). These elements are cooperatively configured for input/output, training, and so on. The peripheral circuitry 1397 can include one or more input vector peripheral circuits that input the voltages, an output buffer or the like to hold the results of the summations, and the like. Given the teachings herein, the skilled artisan will be able to provide any additional desired/required peripheral circuitry, voltage/power supply, elements to interface with peripheral circuitry, and the controller by adapting known techniques, e.g., summer circuits based on an op-amp and capacitor, digital logic circuitry, field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) or specific macro on a memory chip, and the like. To implement any of the digital circuitry described herein, computer-aided semiconductor integrated circuit (IC) logic design, simulation, test, layout, and/or manufacture can be employed. The computerized design process can represent functional and/or structural design features in a design structure generated using electronic computer-aided design (ECAD). A suitable hardware-description language (HDL) can be employed. The skilled artisan can synthesize digital logic circuits to carry out desired control and other functionality, using known computer-aided design techniques such as shown in
One or more embodiments provide 2-terminal devices that are smaller than prior-art three-terminal racetrack type devices, but are larger than devices used for MRAM applications (which are about 35 nm). We have found that multiple states in field-driven and STT-MTJ devices can result from pinning sites in different grains or diffusion of Heusler alloy components (i.e., Mn and Ge) into the underlying chemical templating layer along grain boundaries. This diffusion leads to non-uniformities in the Heusler free layer, resulting in multiple states. Non-uniformity in Heusler films gives rise to multiple regions within the Heusler free layer, displaying non-uniform magnetic properties such as coercivities and current-induced switching of magnetization. The diffusion of the Heusler material's component atoms can be tuned or amplified by several methods: use of high temperature anneal; appropriate choice of seed layers, e.g. Ta/Ru/Ta instead of Ta; by external techniques such as ion bombardment; and the like. We have found that the number of intermediate states for an MTJ device increases with its size. As discussed, in testing we found that every device showed multiple states for device sizes of 100 nm or above for the material stacks studied. The multiple states can be accessed either by external field or current that flows through the MTJ with Heusler films as the free layer. The multiple state devices can be used for artificial neural network applications due to their analog device features.
We have found that there are a number of advantages in using Heusler-based MTJ devices for neuromorphic applications. Indeed, a multi-state Heusler based free layer is ideally suited for neuromorphic applications. Advantageously, the switching between these multiple states is reproducible, and the switching times are compatible with neuromorphic time scales. No specialized device fabrication processing is necessary to access multi-state devices. We have found that the MTJ device size for neuromorphic applications can be close to 100 nm, making it easier to fabricate than typically smaller 35 nm MRAM devices. Moreover, these 100 nm MTJ devices are significantly smaller than the typical racetrack MTJ devices. Hence, a higher area density should be achievable, as compared to prior-art lateral racetrack devices. Further, the endurance of the Heusler-based MTJs where there is switching of magnetic state of the storage layer is better than that of prior-art devices.
It is worth noting that a device RA (product of resistance and area) of ˜10 Ωμm2 is a design point for MRAM MTJ devices where stability of dielectric breakdown has been established. Advantageously, the device RA of one or more embodiments is not limited to ˜10Ωμm2, which improves stability towards dielectric breakdown by permitting a thicker MgO barrier layer (increasing barrier thickness enhances stability and lowers the chance of dielectric breakdown). One or more exemplary embodiments of a neuromorphic MTJ provide a 2-terminal device which has advantages over the prior-art 3-terminal devices (racetrack devices) since it can be scaled up more readily. An exemplary MTJ device has advantages over resistive devices and phase change devices, as the MTJ devices have symmetric operation and threshold behavior. Since the intermediate states from the MTJs based on Heusler alloys are determined by internal nanostructures such as grains, significantly smaller devices can exhibit the corresponding analog functionalities as compared to DW-based neuromorphic devices. These types of devices advantageously provide the ability to construct spiking neurons which are analogous to biological neurons, but at sub-nanosecond speeds (almost up to 107 times faster). We have found that by tuning the size and shape and the seed layer thickness (e.g., dusting layer thickness between 1 Å to 10 Å), this multiple step characteristic can be easily tuned.
A layer is referred to as “interfacial” or “sub-monolayer” or “dusting” herein when it is not a complete layer, i.e., it is not even a monolayer. A thin layer, less than a monolayer, can be discontinuous (i.e., a monolayer with holes) or sparse (material forming the layer reacts with or undergoes adsorption onto the layer underneath). Thus, the terminology “interfacial or dusting layer.” Note, as used herein, including the claims, a “sub-monolayer layer” (e.g., sub-monolayer nitride layer) is intended to define a layer having a sub-monolayer thickness on average, and to include both discontinuous such layers (i.e., having local monolayer thickness and holes) and layers with reaction/adsorption.
Refer again to the discussion of Sample 1, Sample 2, Sample 3, and the discussion of
Seed layer 1403 can include the 50 Å Ta, 250 Å Ru, 100 Å Ta, and 5 Å (CoFe)80B20.
The nitride layer 1403A includes the 300 Å MnxN.
The templating layer 1403B atop the nitride layer includes the 850 Å CoAl, 50 Å IrAl, and 150 Å CoAl.
The Heusler layer 1405 includes the 17 Å Mn3Ge annealed at 342° C.
The tunnel barrier 1409 includes the 12.5 Å MgO.
The magnetic layer 1411 includes the 6 Å (CoFe)70B30-26 Å (CoFe)80B20, 3.0 Å MgO, and 4 Å Ta (IBE clean)(IBE=ion beam etch).
The cap layer 1415 includes 100 Å Ru.
It will thus be appreciated that one or more embodiments provide a structure including a substrate 1401 and a seed layer 1403 overlying the substrate. The seed layer includes, for example, Ta or Ta/Ru/Ta. A nitride layer 1403A is formed with Mn, Sc, Ti, Cr, V, or the like overlying the seed layer 1403; in one or more embodiments, this nitride layer thickness is greater than 5 Å. A templating layer 1403B atop the nitride layer includes a binary alloy having a cesium chloride (CsCl) structure with a thickness of greater than 50 Å. A magnetic layer 1405 overlies the templating layer; the magnetic layer includes a Heusler compound whose magnetization is substantially perpendicular to the layer and is annealed at a temperature greater than 300° C.
In one or more embodiments, the Heusler compound is Mn3Ge. In one or more such embodiments, the Heusler layer has a thickness of less than 5 nm.
In one or more embodiments, the binary alloy with CsCl structure is represented by A1-xEx, where A is a transition metal element and E is a main group element. For example, A includes Co and E includes at least aluminum or gallium and possibly traces of other elements (e.g., Al or Ga; or Al alloyed with Ga, Ge, Sn, or any combination thereof, such as AlSn, AlGe, AlGaGe, AlGaSn, AlGeSn, and AlGaGeSn), and x is in the range from 0.42 to 0.55.
One or more such embodiments further include a tunnel barrier 1409 in contact with the Heusler layer 1405. The tunnel barrier can be, for example, MgO.
In one or more embodiments, the Heusler compound is selected from the group consisting of Mn3Sn, Mn3Sb, Mn2CoSn, Mn2FeSb, Mn2CoAl, Mn2CoGe, Mn2CoSi, Mn2CuSi, Co2CrAl, Co2CrSi, Co2MnSb, and Co2MnSi. In one or more such embodiments, the Heusler layer has a thickness of less than 5 nm.
In one or more embodiments, the binary alloy with CsCl structure is represented by A1-xEx, where A is a transition metal element and E is a main group element. For example, A includes Co and E includes at least aluminum or gallium and possibly traces of other elements (e.g., Al or Ga; or Al alloyed with Ga, Ge, Sn, or any combination thereof, such as AlSn, AlGe, AlGaGe, AlGaSn, AlGeSn, and AlGaGeSn), and x is in the range from 0.42 to 0.55.
One or more such embodiments further include a tunnel barrier 1409 in contact with the Heusler layer 1405. The tunnel barrier can be, for example, MgAl2O4, which can be used as a tunnel barrier whose lattice spacing can be tuned (engineered) by controlling the Mg—Al composition to result in better lattice matching with the Heusler compounds (e.g., the composition of this tunnel barrier can be represented as Mg1-zAl2+(2/3)zO4, wherein −0.5<z<0.5).
Any of the MTJ devices fabricated from any of the structures described herein can be, for example, >50 nm in diameter, or even >60 nm in diameter, or even >80 nm in diameter, or even >90 nm in diameter, or even >100 nm in diameter (these are all non-limiting examples; see
One or more embodiments thus provide a material stack with a Heusler compound as a free layer in a Magnetic tunnel junction (MTJ) device for neuromorphic application. The magnetic layers of the MTJs have their magnetization along a direction perpendicular to the thickness of the film. During switching of the Heusler free layer within the chosen material stack, several intermediates are observed. These states correspond to switching of a region within the free layer. These intermediate states are reproducible and controllable and show analog functionality needed in a neuromorphic device. Furthermore, the switching time is compatible with neuromorphic time scale. The Heusler MTJ based device is two terminal device as opposed to previously demonstrated racetrack based Spintronic devices.
One or more embodiments provide a nitride seed layer that facilitates the requisite texture in the chemical templating layers. Chemical templating layers (CTL) promote the growth of ordered Heusler compounds. In one or more embodiments, the CTL should have a (001) orientation to induce perpendicular magnetic anisotropy (PMA) in the Heusler compound. The CTLs have an alternating layer structure.
As noted, the Heusler layer can be produced via growth on a suitable templating layer. By way of review, in a templating concept a templating layer is grown and another layer (e.g., Heusler compound) is grown on top of it. Templating essentially means that the layer being grown on the templating layer grows to the lattice constant a of the underlayer/seed layer. The material seeks to conserve its unit cell volume. Referring again to
In some cases, the tunnel barrier is MgAl2O4, which can be used as a tunnel barrier whose lattice spacing can be tuned (engineered) by controlling the Mg—Al composition to result in better lattice matching with the Heusler compounds (e.g., the composition of this tunnel barrier can be represented as Mg1-zAl2+(2/3)zO4, wherein −0.5<z<0.5).
As will be appreciated by the skilled artisan, typically, the magnetization is not fixed, but rather, the magnetization precesses like a spinning top at a non-zero temperature. This can change depending on temperature. In view of this precession, perpendicularity, as used herein, refers to perpendicularity of the time integral/average of the path of the magnetization. The time integral/average of the path of the magnetization could be, for example, “exactly” perpendicular, perpendicular within +/−5%, or perpendicular within +/−10%.
In some such cases, the templating layer or chemical templating layer which is a binary alloy is represented by A1-xEx, where A is a transition metal element and E is a main group element. For example, A includes Co and E includes at least aluminum or gallium and possibly traces of other elements (e.g., Al or Ga; or Al alloyed with Ga, Ge, Sn, or any combination thereof, such as AlSn, AlGe, AlGaGe, AlGaSn, AlGeSn, and AlGaGeSn), and x is in the range from 0.42 to 0.55. In some such cases, a tunnel barrier 1409 is located in contact with the Heusler layer; the tunnel barrier can include, for example, MgO (magnesium aluminum oxide is a suitable alternative to MgO with magnesium aluminum oxide having the form Mg1-zAl2+(2/3)zO4, wherein −0.5<z<0.5).
It should be noted that the Heusler compounds are indicated by stoichiometric formulas, and this does not preclude small variations of up to several % from the nominal values.
Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, ion milling, and reactive ion etching (RIE), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.
Although the overall fabrication method, including the epitaxial growth of the Heusler material on the templating layer, and the structures formed thereby, are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products that benefit from neuromorphic devices of Heusler alloy based spin-transfer-torque magnetic tunnel junctions and the like.
An integrated circuit in accordance with aspects of the present inventions can be employed in essentially any application and/or electronic system where neuromorphic devices of Heusler alloy based spin-transfer-torque magnetic tunnel junctions and the like would be beneficial. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments disclosed herein.
Reference should now be had to
Various aspects of the present disclosure are described by narrative text, flowcharts, block diagrams of computer systems and/or block diagrams of the machine logic included in computer program product (CPP) embodiments. With respect to any flowcharts, depending upon the technology involved, the operations can be performed in a different order than what is shown in a given flowchart. For example, again depending upon the technology involved, two operations shown in successive flowchart blocks may be performed in reverse order, as a single integrated step, concurrently, or in a manner at least partially overlapping in time.
A computer program product embodiment (“CPP embodiment” or “CPP”) is a term used in the present disclosure to describe any set of one, or more, storage media (also called “mediums”) collectively included in a set of one, or more, storage devices that collectively include machine readable code corresponding to instructions and/or data for performing computer operations specified in a given CPP claim. A “storage device” is any tangible device that can retain and store instructions for use by a computer processor. Without limitation, the computer readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these mediums include: diskette, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as punch cards or pits/lands formed in a major surface of a disc) or any suitable combination of the foregoing. A computer readable storage medium, as that term is used in the present disclosure, is not to be construed as storage in the form of transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through a fiber optic cable, electrical signals communicated through a wire, and/or other transmission media. As will be understood by those of skill in the art, data is typically moved at some occasional points in time during normal operations of a storage device, such as during access, de-fragmentation or garbage collection, but this does not render the storage device as transitory because the data is not transitory while it is stored.
Computing environment 100 contains an example of an environment for the execution of at least some of the computer code involved in performing the inventive methods, such as a system 200 for semiconductor design and/or control of semiconductor fabrication (see
COMPUTER 101 may take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer or any other form of computer or mobile device now known or to be developed in the future that is capable of running a program, accessing a network or querying a database, such as remote database 130. As is well understood in the art of computer technology, and depending upon the technology, performance of a computer-implemented method may be distributed among multiple computers and/or between multiple locations. On the other hand, in this presentation of computing environment 100, detailed discussion is focused on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 may be located in a cloud, even though it is not shown in a cloud in
PROCESSOR SET 110 includes one, or more, computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed over multiple packages, for example, multiple, coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and/or multiple processor cores. Cache 121 is memory that is located in the processor chip package(s) and is typically used for data or code that should be available for rapid access by the threads or cores running on processor set 110. Cache memories are typically organized into multiple levels depending upon relative proximity to the processing circuitry. Alternatively, some, or all, of the cache for the processor set may be located “off chip.” In some computing environments, processor set 110 may be designed for working with qubits and performing quantum computing.
Computer readable program instructions are typically loaded onto computer 101 to cause a series of operational steps to be performed by processor set 110 of computer 101 and thereby effect a computer-implemented method, such that the instructions thus executed will instantiate the methods specified in flowcharts and/or narrative descriptions of computer-implemented methods included in this document (collectively referred to as “the inventive methods”). These computer readable program instructions are stored in various types of computer readable storage media, such as cache 121 and the other storage media discussed below. The program instructions, and associated data, are accessed by processor set 110 to control and direct performance of the inventive methods. In computing environment 100, at least some of the instructions for performing the inventive methods may be stored in block 200 in persistent storage 113.
COMMUNICATION FABRIC 111 is the signal conduction path that allows the various components of computer 101 to communicate with each other. Typically, this fabric is made of switches and electrically conductive paths, such as the switches and electrically conductive paths that make up busses, bridges, physical input/output ports and the like. Other types of signal communication paths may be used, such as fiber optic communication paths and/or wireless communication paths.
VOLATILE MEMORY 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 112 is characterized by random access, but this is not required unless affirmatively indicated. In computer 101, the volatile memory 112 is located in a single package and is internal to computer 101, but, alternatively or additionally, the volatile memory may be distributed over multiple packages and/or located externally with respect to computer 101.
PERSISTENT STORAGE 113 is any form of non-volatile storage for computers that is now known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained regardless of whether power is being supplied to computer 101 and/or directly to persistent storage 113. Persistent storage 113 may be a read only memory (ROM), but typically at least a portion of the persistent storage allows writing of data, deletion of data and re-writing of data. Some familiar forms of persistent storage include magnetic disks and solid state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open source Portable Operating System Interface-type operating systems that employ a kernel. The code included in block 200 typically includes at least some of the computer code involved in performing the inventive methods.
PERIPHERAL DEVICE SET 114 includes the set of peripheral devices of computer 101. Data communication connections between the peripheral devices and the other components of computer 101 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insertion-type connections (for example, secure digital (SD) card), connections made through local area communication networks and even connections made through wide area networks such as the internet. In various embodiments, UI device set 123 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smart watches), keyboard, mouse, printer, touchpad, game controllers, and haptic devices. Storage 124 is external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 124 may be persistent and/or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (for example, where computer 101 locally stores and manages a large database) then this storage may be provided by peripheral storage devices designed for storing very large amounts of data, such as a storage area network (SAN) that is shared by multiple, geographically distributed computers. IoT sensor set 125 is made up of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.
NETWORK MODULE 115 is the collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers through WAN 102. Network module 115 may include hardware, such as modems or Wi-Fi signal transceivers, software for packetizing and/or de-packetizing data for communication network transmission, and/or web browser software for communicating data over the internet. In some embodiments, network control functions and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (for example, embodiments that utilize software-defined networking (SDN)), the control functions and the forwarding functions of network module 115 are performed on physically separate devices, such that the control functions manage several different network hardware devices. Computer readable program instructions for performing the inventive methods can typically be downloaded to computer 101 from an external computer or external storage device through a network adapter card or network interface included in network module 115.
WAN 102 is any wide area network (for example, the internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or to be developed in the future. In some embodiments, the WAN 102 may be replaced and/or supplemented by local area networks (LANs) designed to communicate data between devices located in a local area, such as a Wi-Fi network. The WAN and/or LANs typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and edge servers.
END USER DEVICE (EUD) 103 is any computer system that is used and controlled by an end user (for example, a customer of an enterprise that operates computer 101), and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives helpful and useful data from the operations of computer 101. For example, in a hypothetical case where computer 101 is designed to provide a recommendation to an end user, this recommendation would typically be communicated from network module 115 of computer 101 through WAN 102 to EUD 103. In this way, EUD 103 can display, or otherwise present, the recommendation to an end user. In some embodiments, EUD 103 may be a client device, such as thin client, heavy client, mainframe computer, desktop computer and so on.
REMOTE SERVER 104 is any computer system that serves at least some data and/or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents the machine(s) that collect and store helpful and useful data for use by other computers, such as computer 101. For example, in a hypothetical case where computer 101 is designed and programmed to provide a recommendation based on historical data, then this historical data may be provided to computer 101 from remote database 130 of remote server 104.
PUBLIC CLOUD 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and/or other computer capabilities, especially data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically leverages sharing of resources to achieve coherence and economies of scale. The direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and/or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments that run on various computers making up the computers of host physical machine set 142, which is the universe of physical computers in and/or available to public cloud 105. The virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and/or containers from container set 144. It is understood that these VCEs may be stored as images and may be transferred among and between the various physical machine hosts, either as images or after instantiation of the VCE. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs and manages active instantiations of VCE deployments. Gateway 140 is the collection of computer software, hardware, and firmware that allows public cloud 105 to communicate through WAN 102.
Some further explanation of virtualized computing environments (VCEs) will now be provided. VCEs can be stored as “images.” A new active instance of the VCE can be instantiated from the image. Two familiar types of VCEs are virtual machines and containers. A container is a VCE that uses operating-system-level virtualization. This refers to an operating system feature in which the kernel allows the existence of multiple isolated user-space instances, called containers. These isolated user-space instances typically behave as real computers from the point of view of programs running in them. A computer program running on an ordinary operating system can utilize all resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and devices assigned to the container, a feature which is known as containerization.
PRIVATE CLOUD 106 is similar to public cloud 105, except that the computing resources are only available for use by a single enterprise. While private cloud 106 is depicted as being in communication with WAN 102, in other embodiments a private cloud may be disconnected from the internet entirely and only accessible through a local/private network. A hybrid cloud is a composition of multiple clouds of different types (for example, private, community or public cloud types), often respectively implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technology that enables orchestration, management, and/or data/application portability between the multiple constituent clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.
Exemplary Design Process Used in Semiconductor Design, Manufacture, and/or Test
One or more embodiments make use of computer-aided semiconductor integrated circuit design simulation, test, layout, and/or manufacture. In this regard,
Design flow 700 may vary depending on the type of representation being designed. For example, a design flow 700 for building an application specific IC (ASIC) may differ from a design flow 700 for designing a standard component or from a design flow 700 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 710 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of components, circuits, devices, or logic structures to generate a Netlist 780 which may contain design structures such as design structure 720. Netlist 780 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 780 may be synthesized using an iterative process in which netlist 780 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a nonvolatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or other suitable memory.
Design process 710 may include hardware and software modules for processing a variety of input data structure types including Netlist 780. Such data structure types may reside, for example, within library elements 730 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 740, characterization data 750, verification data 760, design rules 770, and test data files 785 which may include input test patterns, output test results, and other testing information. Design process 710 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 710 without deviating from the scope and spirit of the invention. Design process 710 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 710 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 720 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 790. Design structure 790 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 720, design structure 790 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more IC designs or the like. In one embodiment, design structure 790 may comprise a compiled, executable HDL simulation model that functionally simulates the devices to be analyzed.
Design structure 790 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 790 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described herein (e.g., .lib files). Design structure 790 may then proceed to a stage 795 where, for example, design structure 790: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
The illustrations of embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. It should also be noted that, in some alternative implementations, some of the steps of the exemplary methods may occur out of the order noted in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may sometimes be executed in the reverse order, depending upon the functionality involved. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Terms such as “bottom”, “top”, “above”, “over”, “under” and “below” are used to indicate relative positioning of elements or structures to each other as opposed to relative elevation. If a layer of a structure is described herein as “over” another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. If a layer is described as “directly on” another layer, direct contact of the two layers is indicated. Generally, layers depicted in the drawings as directly touching may be directly contacting as just described, or may have intervening layers. As the term is used herein and in the appended claims, “about” means within plus or minus ten percent.
The corresponding structures, materials, acts, and equivalents of any means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit thereof. The embodiments were chosen and described in order to best explain principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.76(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, the claimed subject matter may lie in less than all features of a single embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
