Patent Application
20170104064
Nitride semiconductors often are used for manufacture of power devices with high breakdown voltages because of inherent advantages from this material. A typical nitride semiconductor may be represented by the formula Aluminum-x Indium-y Gallium1-x-y Nitride (0<=x<=1, 0<=y<=1, 0<=x+y<=1), and includes for example gallium nitride (GaN), an aluminum nitride (AlN), and indium nitride (InN). A particularly useful type of nitride semiconductor device often is a high electron mobility transistor, wherein a hetero-junction surface is formed in the interface between a carrier running layer, which consists of a nitride semiconductor which differs in bandgap energy mutually, and a carrier feed layer. In this example, a two-dimensional carrier gas layer as a current path (channel) is formed in the carrier running layer near the hetero-junction surface.
A recent electrode configuration arrangement for a transistor is the tandem-type structure in which the source diffusion area and the drain diffusion region mutually intermingle in an opposing comb structure. The tandom structure of a drain diffusion region and a source diffusion area in interleaving fingers provides several advantages. For example, this has been proposed to lengthen the drift region length near the electrical tip of the teeth of a comb and thereby increase the breakdown voltage of the horizontal-type semiconductor device arranged in the shape of an intersection finger. See JP2001-7339A, the contents of which, and particularly the structural and chemical details for fabrication of High Electron Mobility Transistor (HEMT) devices taught therein, are particularly incorporated by reference in its entirety.
This reference describes changing the form of a diffusion region of a HEMT transistor structure. The proposed design, which makes a two-dimensional carrier gas layer a channel, as described therein, has a thematic voltage limitation. The HEMT has a two-dimensional carrier gas layer as a channel and lacks an ability to control the withstand voltage by varying the shape of the diffusion region.
To improve device performance, an increase in gate-drain reverse breakdown voltage is generally sought. Various technologies have been developed in this aim, including insulated gate, recessed gate, overlapping gate and field plate over an insulator.
In the field of HEMT construction, field plate development has been active. Saito et al demonstrated that higher breakdown voltages could be achieved by connecting a field plate to the source electrode, for example (IEDM Tech. Dig. 2003 pp. 587-590). Also see Xing et al. review of field plate potentiated increase in breakdown voltage (IEEE Electron Device Letters, Vol. 25. No. 4 April 2004. However, these teachings emphasize square electrodes and symmetrical field plates. See for example U.S. Pat. No. 8,754,496. which teaches the desirability of positioning a gate field plate equadistantly from the source electrode and the drain electrode.
The problem of controlling the withstand voltage in interdigitated electrode structures has been addressed in JP publication 2013-98222. This publication concerns a HEMT structure that provides some relaxation of the electric field, and thereby increases the breakdown voltage. Source and drain electrodes of the comb are arranged in the exchanged interdigital structure as shown therein and as represented as
Maximum operation voltage is often an important constraint in this field and anything that allows an increased voltage during use would provide significant benefits.
An object of embodiments is to provide semiconductor devices with greater withstand voltage by having interdigitated source electrode and a drain electrode tip structures, which provide improved electric field gradients at the tips. It was found that arranging source electrode tips with greater radius of curvature than that of the drain source electrode tips allows improved withstand voltage performance. This astonishing structural feature can provide much higher device withstand voltage performance, which is particularly useful for higher voltage or power applications. As a result, this structure alleviates many of the problems mentioned above in the art. This embodiment can prevent concentration of electric field at the arc portion, which leads to voltage breakdown of the device. In addition, because the opposing electrode side can be thin, the embodiment improves the area efficiency.
An embodiment is a semiconductor device, comprising a substrate base; a nitride semiconductor layer on the substrate base, comprising a laminated carrier supply layer and carrier transit layer region with a formed heterojunction therefrom; an insulating film disposed on the nitride semiconductor layer; a source electrode of a comb shape having a plurality of teeth portions with tips, disposed on the nitride semiconductor layer; a drain electrode of a comb shape having a plurality of teeth portions with tips disposed on the nitride semiconductor and interdigitated with the source electrode; and a gate electrode disposed on the nitride semiconductor layer between the source electrode and the drain electrode, wherein the tips of the source electrode and the tips of the drain electrode are semi-circular shaped, and the radius of curvatures of the source electrode tips are larger than the radius of curvatures of the drain electrode tips. In an embodiment the curvature radius of the source electrodes are from 1.5 to 6 times the radius of curvature of the drain electrodes. In an embodiment the curvature radius of the source electrodes are from 2 to 4 times the radius of curvature of the drain electrodes. In an embodiment the vertical thickness of the drain electrodes is from 1.5 to 6 times the vertical thickness of the source electrodes. In an embodiment the vertical thickness of the drain electrodes is from 2 to 4 times the vertical thickness of the source electrodes. In an embodiment the average width of the source electrodes is between 1.5 and 6 times the average width of the drain electrodes. In an embodiment the average width of the source electrodes is between 2 and 4 times the average width of the drain electrodes. In an embodiment the sides of the tips of the source electrodes are beveled at a slope of at least 10 degrees. In an embodiment the ratio of length to average width of the source electrodes is between 3 and 10. In an embodiment the average width of the drain electrodes is less than 4 mm. In an embodiment the average width of the drain electrodes is 2 mm or less. In an embodiment the device has a breakdown voltage that exceeds 600 volts.
An embodiment is a semiconductor device, comprising: a semiconductor heterojunction layer; an insulating film disposed on the heterojunction layer; a source electrode of a comb shape having a plurality of teeth portions with tips, disposed on the heterojunction layer: a drain electrode of a comb shape having a plurality of teeth portions with tips disposed on the heterojunction layer and interdigitated with the source electrode; and a gate electrode disposed on the heterojunction layer between the source electrode and the drain electrode, wherein the tips of the source electrode and the tips of the drain electrode are semi-circular shaped, and the radius of curvatures of the source electrode tips are larger than the radius of curvatures of the drain electrode tips.
Another embodiment is a HEMT semiconductor device, comprising: a semiconductor heterojunction layer: an insulating film disposed on the heterojunction layer: a source electrode of a comb shape having a plurality of teeth portions with tips, disposed on the heterojunction layer; a drain electrode of a comb shape having a plurality of teeth portions with tips disposed on the heterojunction layer and interdigitated with the source electrode; a gate electrode disposed on the heterojunction layer between the source electrode and the drain electrode, and a gate electrode field plate extending asymmetrically preferentially towards the drain electrode regions of the tips of the drain electrode; wherein the tips of the source electrode and the tips of the drain electrode are semi-circular shaped, and the radius of curvatures of the source electrode tips are larger than the radius of curvatures of the drain electrode tips.
Other embodiments will become apparent to a skilled reader.
Basic Structure: Interdigitated Drain Electrodes with Source Electrodes Having Larger Curved Tips
A basic structure is an electric field device such as a FET that has a drain, a source and a gate. For higher current, such devices often have interdigitated (comb-like) source and gate structures. A preferred embodiment is a high electron mobility transistor (“HEMT”) having curved tip structures to relax the electric field impressed by the source (in electron emission as N-doped) onto the semiconductor. The source electrode and drain electrode are comb-shaped and arranged in an interdigital configuration as shown in
Preferably the drain and source electrode tips are curved and each has a radius of curvature. For example drain tip 13 and source tip 14 shown in
In most preferred embodiments, the radius of curvature of the drain electrode tip is smaller than the radius of curvature of the source electrode tip. If the source is an inverse (concave surface) arc, curvature may be small because the electric field is not that concentrated.
Without wishing to be bound by any one theory for operation of this embodiment, it is believed that advantageous effects of withstand voltage arise from the fact that the electric field (from electrons of a source in a typical HEMT or from a source in an N-type MOSFET) concentrate on the gate end. The electric field is stronger on the arcuate portion than in the straight portion and tends to protrude as a spike from the end. It is seen that increasing the arcuate curvature contributes to relaxation in the electric field. The gate electrode is close to the source electrode and relaxation of the electric field improves high voltage performance by limiting the electric field intensity.
Embodiments particularly pertain to interdigitated source and drain electrodes with tips that impress electric field gradients at their ends. A large variety of field sensitive devices are contemplated to take advantage of this surprising new discovery. In particular the HEMT structure benefits from the discovery of the asymmetric tip electrode radius structures. The HEMT is described herein to exemplify embodiments but the invention is not necessarily limited to this and can be used, with varying degrees of success with other field sensitive devices that are known or will be developed.
Virtually any contemplated or future HEMT device having interdigitated electrodes as described herein can benefit via higher withstand voltage from embodiments. In an embodiment with interdigitated source and drain tips, the source tip radius is larger than the drain tip radius. In another embodiment a source field plate is used and the source field plate radius is interdigitated with a larger tip radius in a similar manner as the source electrode tips. In embodiments the radius measurements and area sizes referred to are parallel to the main two dimensional axis plane of the hetero-junction as will be appreciated from inspection of the figures.
In an embodiment the source field plate is larger than and outside the footprint of the source electrode, such as seen from an above (perpendicular to the heterojunction plane) plan view shown in drawings 1, 2, 4 and 5. In another embodiment the source field plate is approximately (within 20%) of the surface area (seen in plan view) of the source electrode. In yet another embodiment the source field plate area is at least 25% larger (as seen from plan view perpendicular to the interdigitated structure) than the source electrode area.
Desirable embodiments comprise a substrate base having a semiconductor layer on the base as described for example in JP 2013-98222. The contents of this reference pertaining to materials and construction of HEMT devices are particularly incorporated by reference in their entireties. Although the heterojunction nitride semiconductor is described as formed on the base substrate, with insulator on top, other configurations are contemplated and will work. For example, as shown in U.S. Pat. No. 9,123,740 entitled “High electron mobility transistors and methods of manufacturing the same,” the channel supply layer may be disposed on an insulation layer that is on a substrate, with a channel layer thereupon. The contents, and particularly the materials and methods described in U.S. Pat. No. 9,123,740 are incorporated by reference herein and constitute representative ways of carrying out embodiments described herein.
In preferred embodiments, source, gate and drain electrodes are formed over a hetero-junction that is made on a substrate. A variety of materials may be used for this and related constructions as follows:
Substrate: The substrate may be for example a silicon (Si) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, sapphire, a direct bonded copper (DBC) substrate, and a metal substrate. However, a type of the substrate is not limited thereto, and may vary.
Insulation layer. The insulation layer may be formed of any insulation material, such as at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum nitride, and aluminum oxide. Also, the insulation layer ID may be formed of an insulative polymer.
Electrodes: A drain electrode, a gate electrode, and a source electrode may be disposed spaced apart from each other in the insulation layer, on the insulation layer, in between insulation layers etc. The drain electrode, gate electrode, and source electrode may be metals or metal compounds, but example embodiments are not limited thereto. For example, source and drain electrodes can be a lamination of a Ti layer that is in contact with the active layer and a layer of alloy Al and Si formed on the Ti layer. A wide variety of gate electrode materials are known such as laminations of for example Ni and
Au.
Heterojunction: For HEMT embodiments, the structure incorporates a junction between two materials with different band gaps (that is, a heterojunction) as the channel instead of a doped region (as is generally the case for a MOSFET). A desirable material combination is GaAs with AlGaAs. However a wide variation of materials are useful, dependent on the application. For example, devices incorporating indium may be used for improved high-frequency performance
The heterojunction exists as a channel supply layer that may be in contact with the gate electrode. The channel layer includes a two-dimensional electron gas (2DEG) induced by the channel supply layer, an effective channel region contacting the channel supply layer, and a high resistivity region on the effective channel region. The high resistivity region is a region in which impurities are (typically) ion-implanted, although chemical vapor deposition and other techniques can be used. The impurities may include for example at least one of neon (Ne), argon (Ar), carbon (C), iron (Fe), and vanadium (V). The impurities may be ion-implanted at a concentration of about 1015/cm3 to about 1021/cm3 in the high resistivity region. The high resistivity region may have a resistivity equal to or greater than about 107 ohm cm. The high resistivity region may extend throughout a top portion of the channel layer. The channel region preferably is about 50 nm to about 200 nm but may be bigger or smaller. The channel layer may include a gallium nitride (GaN)-based material. For example, the channel layer may include GaN.
The channel supply layer may exist as a single or a multi-layer structure. The channel supply layer preferentially includes a nitride that contains at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B). For example, the channel supply layer may include a single and multi-layer structure that includes at least one of AlGaN, AlInN, AlN, AlInGaN, and the like. The channel supply layer, CS1, may induce a two-dimensional electron gas (2DEG) (not shown), in a channel layer, C1, which is formed on the channel supply layer CS1. The channel supply layer, CS1, may include a material having higher polarizability and/or larger energy bandgap than the channel layer, C1. For example, the channel supply layer, CS1, may have a single or multi-layer structure including at least one material selected from among nitrides including at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B). In detail, the channel supply layer CS1 may have a single or multi-layer structure including at least one of various materials consisting of AlGaN, AlInN, AlN, AlInGaN, BN, and so on. The thickness of the channel supply layer, CS1, may be equal to or less than about several tens of nm. For example, the thickness of the channel supply layer, CS1, may be equal to or less than about 50 nm.
The channel layer, C1, may be disposed on the channel supply layer, CS1. The channel layer, C1, may include a material having smaller polarizability and/or energy bandgap than the channel supply layer, CS1. For example, the channel layer, C1, may include a GaN-based material, such as GaN. A 2DEG (not shown) induced by the channel supply layer, CS1, may exist in the channel layer, C1. The 2DEG may be formed in a portion of the channel layer, C1, adjacent to the interface between the channel layer, C1, and the channel supply layer, CS1. The thickness of the channel layer, C1, may be thicker than that of the channel supply layer, CS1. For example, the thickness of the channel layer, C1, may be from about 2 nanometers to about 3 nanometers. However, in some cases, the thickness of the channel layer, C1, may be greater than about 3 nanometers.
In an embodiment, a gate field plate is combined with a larger source electrode radius tip end to synergistically limit peak electric field. In an embodiment the gate field plate shape corresponds (follows the contour of) the source electrode. “Corresponds” in this context means to follow the shape within 50%, preferably within 80% and more preferably within 90%. In an embodiment the gate field plate extends laterally over the heterojunction plane at least 10%, preferably at least 20% and more preferably at least 30% from the area of the underlying gate electrode and asserts such beneficial effect thereby. The percentages referred to here are percent area of the uncovered surface area between the gate electrode and the drain electrode.
Desirably the gate field plate covers at least 10% of the area between the gate electrode and the drain electrode and has a radius that is larger when matched with a source electrode tip inside the interdigitated finger than when matched with a drain electrode tip inside the interdigitated finger. In other words, in an embodiment the gate field electrode has a semi-circular shape with a defined radius of curvature that follows either the gate electrode contours or the drain electrode contours.
The curvature radius of the gate field electrode is greater when surrounding the source electrode than when the gate field electrode is surrounding the drain electrode, as seen in plan view of the interdigitated structure. In an embodiment the asymmetric semi-circular gate field plate as described above is paired with asymmetric semi-circular source electrodes so that an enlarged field gate exists near the tip of the source electrode and a smaller (or no) field electrode exists near the tip of the drain electrode.
In an embodiment source field electrodes are used which are larger at a source electrode tip ends than at the drain electrode tip ends.
Prior art structures often emphasized sharp edged interdigitated electrodes for economy of space reasons and teach away from inventive concepts apprehended by the inventor. For example U.S. Pat. No. 9,123,740 teaches the desirability of squared off interdigitated electrodes in combination with trench structures for HEMT devices. See for example
Preferably the basic interdigitated structure is prepared and used as described in JP publication 2013-98222. However a large variety of devices can utilize the embodiments exemplified here and recited in the claims.
pHEMT embodiments In practice, desirable materials such as AlGaAs on GaAs have lattice constants that generally slightly differ. This results in crystal defects. Embodiments employ a pHEMT or pseudomorphic HEMT wherein this rule is violated by using an extremely thin layer of one of the materials—so thin that the crystal lattice simply stretches to fit the other material. Skilled artisans can readily construct pHEMT devices according to embodiments taught herein and such embodiments and are included.
mHEMT embodiments These include devices that utilize materials of different lattice constants with a buffer layer between them. In a preferred embodiment the buffer layer is made of AlInAs, with the indium concentration graded so that it can match the lattice constant of both the GaAs substrate and the GaInAs channel. This potentiates use of practically any Indium concentration in the channel. Thus devices can be optimized for different applications such as low indium concentration devices that provide low noise performance and high indium concentration devices that provide high gain performance.
Induced HEMT embodiments In contrast to a modulation-doped HEMT, an induced high electron mobility transistor provides the flexibility to tune different electron densities with a top gate, since the charge carriers are “induced” to the 2DEG plane rather than created by dopants. The absence of a doped layer enhances the electron mobility significantly when compared to their modulation-doped counterparts. These induced HEMT devices are intended embodiments as well.
HEMTs and related devices having interdigitated electrode structures can benefit from the asymmetric source and drain electrodes. Examples provided below relate to a wide range of devices. These examples illustrate equipment and methods for materializing the technical idea of embodiments. The technical idea of this invention as recited in the claims does not specify the form of component parts, structure, arrangement, etc. except as illustrated by the following and by what a skilled artisan naturally can determine.
A preferred basic construction is taught in JP publication 2013-98222. See
A nitride semiconductor device is provided with a gate electrode 5 arranged between source electrode 3 and drain electrode 4. This configures a tandem-type form having multiple gear-tooth portions mutually extended in a vertical direction toward a side as shown in
Each electrode region is a “linear” region or an end “proximal” region. A “linear” region is defined as the region where the gear-tooth portions of the source electrode 3 and the drain electrode 4 are linearly co-parallel. A “proximal” region, otherwise termed a “point” herein, is the region of a point, of the gear-tooth portions of the source electrode 3 and the drain electrode 4 whose outer edge is a curve.
Notably, the distances between regions preferably may be altered as described in JP 2013-98222. Looking at a cross section via
The nitride semiconductor device is further provided with gate field plate 50 electrically connected with gate electrode 5, and source field plate 30 electrically connected with source electrode 3. This arrangement of gate field plate 50 and source field plate 30 between gate electrode 5 and drain electrode 4 controls curvature of the depletion layer of the drain side end of the gate electrode 5. Also this eases the concentration of the bias electric fields at the end on the drain electrode side of the gate electrode 5 (herein termed “drain side end”.)
As shown in
As shown in
The shapes of the tip of source electrode 3, the tip of drain electrode 4, and the source field plate 30 are semicircular. Each semicircular shape has a characteristic radius that is easily measured from the respective cross section edges. Most importantly, the semicircular radius of the source electrode is larger than the semicircular radius of the drain electrode. In other optional embodiments, the shapes depart from strictly semicircular, but preferably the ends are curved. Preferably the average width of the source electrodes is at least 50% greater than the average width of the drain electrodes, regardless of the exact shape. More preferably the average width is at least twice the average width of the drain electrodes.
In the source proximal region, the outer edge of the handle portion between the gear-tooth portions of the drain electrode 4 has become depressed in a preferred semicircular shapes along the tip of the source electrode 3. Similarly, in the drain proximal region, the outer edge of the handle portion between the gear-tooth portions of the source electrode 3 has become depressed in preferably semicircular shapes along the tip of the drain electrode 4. For this reason, the gate electrode 5 arranged between the source electrode 3 and the drain electrode 4 is preferably a circular shape in a proximal region. Similarly, the gate field plate 50 and the source field plate 30 are also preferably circular shape in a proximal region.
The embodiments described herein most preferably further include asymmetric source electrode tip size vs drain electrode tip size. As shown in
A more detailed representation of this tip asymmetry is shown in plan views
The actual dimensions of the linear regions (not shown in
As shown in
It is preferable to make the gate length of a proximal region longer than the gate length of a linear area in addition to each of above-mentioned distances. The actual ratio of linear region to proximal region and the number of fingers in a comb will vary depending on the desired operation speed and other variables as a skilled artisan readily will recognize.
The average length to average width ratio of the electrode fingers may be for example between 3 and 10. The average width of the drain electrodes can be less than 4 mm, less than 3 mm, less than 2 mm, or even less than 1.5 mm. The tips of the electrodes may be beveled due to isotropic etching or other formation process to a slope of at least 5 degrees, at least 10 degrees, at least 15 degrees or more. In a preferred embodiment the source electrodes are wider than the drain electrodes, as for example shown in the interdigitated structure of
A specific construction of a nitride semiconductor device is described next.
A semiconductor substrate is used such as a silicon (Si) substrate, a silicon carbide (SiC) substrate, and a GaN substrate, silicon on sapphire or a ceramic substrate. See
The nitride semiconductor layer 2 has the carrier feed layer 22 which consists of a first nitride semiconductor layer, and the carrier running layer 21 which consists of a second nitride semiconductor layer which has different bandgap energy from a first nitride semiconductor layer.
The carrier running layer 21 arranged on the buffer layer 11 is grown epitaxially as non-doped GaN, for example by an organic-metal-vapor-growth (MOCVD) method. Non-doped in this context means that the impurity is not added intentionally.
A band gap is larger than the carrier running layer 21, and the carrier feed layer 22 arranged on the carrier running layer 21 consists of a nitride semiconductor whose lattice constant is smaller than the carrier running layer 21. AluminumxGa1-xN non-doped as the carrier feed layer 22 can be used.
The carrier feed layer 22 is formed on the carrier running layer 21 by epitaxial growth by an MOCVD method etc. Since a lattice constant differs between the carrier feed layer 22 and the carrier running layer 21, piezo polarization is produced by a lattice strain. A high-density carrier arises in the carrier running layer 21 near the hetero-junction, and the two-dimensional carrier gas layer 23 as a current path (channel) is formed in it by this piezo polarization and the spontaneous polarization of the crystal of the carrier feed layer 22.
The source electrode 3 and the drain electrode 4 are formed of metal that allows low resistance contact with nitride semiconductor layer 2. For example, aluminum (aluminum), titanium (Ti), etc. can be used for the source electrode 3 and the drain electrode 4. Alternatively a laminated body of Ti and aluminum can be used for the source electrode 3 and the drain electrode 4.
Nickel gold (NiAu) etc. are employable as the gate electrode 5 and the gate field plate 50, for example, aluminum metallurgy (Au), copper (Cu), etc. are employable as the source electrode wiring 31 and the drain electrode wiring 41, for example.
Insulation layers can be added as needed, as will be appreciated by a skilled artisan.
Other embodiments not described herein will be understood by a skilled reader and are included within the ambit of the attached claims, as space limitations preclude adding additional information that is readily available.
