Patent Application
20070215931
The present invention relates to a nonvolatile floating gate memory cell made in a trench of a semiconductor substrate, with the trench having a first portion deeper than a second portion, an array of such cells, and a method of manufacturing.
Nonvolatile memory cells with each having a floating gate for the storage of charges thereon to control the conduction of current in a channel in a substrate of a semiconductive material is well-known in the art. Typically, such cells have been made in a semiconductor material which has a substantially flat surface along a horizontal plane. However, the prior art also discloses manufacturing such cells in a vertical relationship in a pillar which are gaps in a vertical position See, for example, U.S. Pat. No. 6,633,057; 6,235,583; 6,157,061; 5,999,453; 5,616,511; and 5,567,637. In addition, see the article entitled “A Self-Aligned Split-Gate Flash EEPROM Cell With 3-D Pillar Structure” by Fumihiko Hayashi and James D. Plummer published in the 1999 Symposium on VLSI Technology Digest of Technical Papers pages 87 and 88. The Hayashi and Plummer paper discloses a memory cell in which a channel silicon pillar is surrounded by a floating gate and a control gate.
In the prior art, non-volatile memory cells using floating gates for the storage of charges thereon have been either of the stack gate type or of a split gate type. In a stack gate type, the control gate is aligned with the floating gate and controls the entire channel region of the memory cell. In a split gate type, the control gate has at least a portion adjacent to the floating gate and controls a portion of the channel region while the floating gate controls another portion of the channel region.
Heretofore, none of the references discloses formation of a split gate type non-volatile memory cell wherein the cell is made in a trench having a first portion deeper than a second portion.
It is therefore, an object of the present invention to overcome this and other difficulties.
Accordingly, in the present invention, a non-volatile memory cell comprises a substrate of a substantially single crystalline semiconductive material having a first connectivity type with a surface. A trench is located in the surface and extends into the substrate to a first depth and to a second depth which is deeper than the first depth. The trench has a first side wall along the trench and extends to the first depth and a second sidewall along the trench extending from the first depth to the second depth and a bottom. A first region of a second conductivity type is in the substrate along the bottom of the trench. A second region of the second conductivity type is in the substrate along the surface of the trench. A channel region is formed in the substrate between the first region and the second region with the channel region having a first portion and a second portion. The first portion of the channel region is between the surface and the first depth and is along the first sidewall. The second portion of the channel region is between the first depth and the second depth and is along the second sidewall. A control gate extends from the surface of the substrate into the trench to the second depth insulated from the bottom. The control gate is adjacent to and insulated from the second sidewall of the trench. A floating gate is adjacent and insulated from the first sidewall of the trench between the first portion of the channel region and the control gate.
The present invention also relates to an array of the foregoing described nonvolatile memory cells. Finally, the present invention relates to a method of manufacturing an array of nonvolatile memory cells.
Referring to
In the first step of the method of the present invention in forming the nonvolatile memory cell and array of the present invention, a substantially single crystalline semiconductor substrate 10, such as silicon is shown. The substrate 10 is of a first conductivity type, preferably P-type. It has a horizontal surface 11. A first layer of silicon oxide or silicon dioxide 12 is deposited on the surface 11. Typically, the layer of silicon dioxide 12 is formed by thermal oxidation or deposited oxide, resulting in a layer of approximately 200 angstroms in thickness. It should be noted that the present process described herein is for the 90 nm process. However, the invention is not so limited and for different scale of integration, different dimensions need to be used. After the silicon dioxide layer 12 is formed, an implantation or multiple implantations are made through the silicon dioxide layer 12 and into the substrate 10. This results in the formation of a N-type region 20 beneath the entire surface 11 of the substrate 10. The resulting structure is shown in
A layer of silicon nitride 14 is deposited on the layer of silicon dioxide 12. The silicon nitride 14 can be formed by Chemical Vapor Deposition (CVD) resulting in a thickness of 500 angstroms thick silicon nitride 14. A photoresist layer 16 is then deposited on the layer of silicon nitride 14. The photoresist material 16 is masked and portions are cut from the photoresist material 16. The resulting structure is shown in
The openings in the photoresist 16 is used. as a mask to cut (i.e. anisotropically etch) through the silicon nitride 14 and through the silicon dioxide 12 onto the substrate 10. The resulting structure is shown in
With the surface 11 of the substrate 10 exposed, the substrate 10 is anisotropically etched forming trenches 22. The trenches 22 are etched to a first depth R of approximately 90 nanometers. The resulting structure is shown in
The photoresist material 16 is then removed. An optional, disposable, liner oxide layer can be formed and removed before the high quality gate oxide is formed by exposing the structure to an oxidation atmosphere to oxidize the exposed silicon in trenches 22 in the substrate 10. The exposure which oxidizes the exposed silicon substrate 10 results in the formation of a layer 24 of silicon dioxide of approximately 80 angstroms. This can be done by thermal oxidation. The resulting structure is shown in
Polysilicon 26 is then deposited on the structure shown in
The structure in
Another layer of silicon dioxide 28 is then deposited on the structure shown in
Using the silicon dioxide spacers 28 as a mask, in each of the trenches 22, and with the silicon nitride 14 covering the surface 11 of the substrate 10, the structure shown in
Another layer of silicon dioxide 36 is then deposited on the structure shown in
Polysilicon 40 is then deposited everywhere and covers the entire structure shown in
Referring to
The structure shown in
The structure shown in
The operation of the cell and memory array of the present invention is as follows.
To program a selected cell, the selected control gate polysilicon 40 receives approximately 1.2 volt, the selected common source region 20 receives approximately 7 volts, and the selected drain region 32 receives approximately 0.5 volt. This turns on the control gate channel region, in the portion of the trench which is deeper. The electrons traverse the channel region from the drain region 32 to the source region 20, and are injected onto the floating gate 26. The unselected drain regions 32 are supplied with a voltage higher than the voltage applied to the selected control gate polysilicon 40 in order to turn off the associated unselected channels and to prevent electrons from traversing from the unselected drain region 32 to the selected source region 20. This can be on the order of 1.5 volts. All other unselected source regions 20 are left floating or at ground.
To erase a selected cell, the selected control gate polysilicon 40 receives approximately 10 volts, and all other nodes are at ground. The electrons on the floating gate 26 tunnel from the floating gate 26 onto the control gate polysilicon 40. Since erase is by sector, all the cells in the same row having the same control gate polysilicon 40 are erased simultaneously.
To read a selected cell, the selected control gate polysilicon 40 receives close to full supply voltage (approximately 1 volt), the common source region 20 is grounded and the selected drain region 32 receives approximately 1 volt. Electrons would flow from the common source region 20 to the selected drain region 32 if the floating gate 26 were not programmed with electrons. If the floating gate 26 is programmed with electrons, then current would not flow in that selected cell. The unselected drain regions 32 is held at ground. Thus, for the unselected cells, no current can flow between the unselected drain region 32 and the unselected source region 20. All other unselected source regions 20 are also at ground.
