The present invention relates to memory devices and methods of manufacturing memory devices. The present invention has particular applicability to non-volatile memory devices.
The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement, e.g., a ten year data retention requirement.
Implementations consistent with the present invention provide a non-volatile memory device formed using a fin structure. Oxide-nitride-oxide (ONO) layers may be formed over the fin structure and a polysilicon layer may be formed over the ONO layers. The nitride layer in the ONO layers may function as the floating gate electrode for the non-volatile memory device. The polysilicon layer may function as the control gate and may be separated from the floating gate by the top oxide layer of the ONO layers.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a memory device that includes a substrate, an insulating layer, a fin structure, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The dielectric layers are formed over the fin structure and function as a charge storage dielectric and the control gate is formed over the dielectric layers.
According to another aspect of the invention, a method of manufacturing a non-volatile memory device is provided. The method includes forming a fin on an insulating layer, where the fin acts as a substrate and a bitline for the non-volatile memory device. The method also includes forming a number of dielectric layers over the fin, where the dielectric layers function as a charge storage dielectric. The method further includes forming source and drain regions, depositing a gate material over the dielectric layers and patterning and etching the gate material to form a control gate.
According to another aspect of the invention, a non-volatile memory array that includes a substrate, an insulating layer, a number of conductive fins, a number of dielectric layers and a number of gates is provided. The insulating layer is formed on the substrate and the conductive fins are formed on the insulating layer. The conductive fins act as bit lines for the memory array. The dielectric layers are formed over the fins and the gates are formed over the dielectric layers. The gates act as word lines for the memory array.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.
Reference is made to the attached drawings, wherein elements having the same reference number designation may represent like elements throughout.
The following detailed description of the invention refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and their equivalents.
Implementations consistent with the present invention provide non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, and methods of manufacturing such devices. The memory device may include a fin field effect transistor (FinFET) structure with dielectric layers and a control gate layer formed over a fin. One or more of the dielectric layers may act as a floating gate for the memory device.
In an exemplary implementation, buried oxide layer 120 may include a silicon oxide, such as SiO2, and may have a thickness ranging from about 50 Å to about 1000 Å. Silicon layer 130 may include monocrystalline or polycrystalline silicon having a thickness ranging from about 200 Å to about 3000 Å. Silicon layer 130 may be used to form a fin structure, as described in more detail below.
In alternative implementations consistent with the present invention, substrate 110 and layer 130 may comprise other semiconducting materials, such as germanium, or combinations of semiconducting materials, such as silicon-germanium. Buried oxide layer 120 may also include other dielectric materials.
Optionally, a dielectric layer, such as a silicon nitride layer or a silicon oxide layer (not shown), may be formed over silicon layer 130 to act as a protective cap during subsequent etching processes.
A photoresist material may be deposited and patterned to form a photoresist mask 140 for subsequent processing, as illustrated in
Semiconductor device 100 may then be etched. In an exemplary implementation, silicon layer 130 may be etched in a conventional manner, with the etching terminating on buried oxide layer 120, as illustrated in
During the formation of fin 210, bitline pickup or source and drain regions may also be formed adjacent the respective ends of fin 210. For example, silicon layer 130 may be patterned and etched to form bitline pickup or source and drain regions.
Photoresist mask 140 may then be removed. A number of films may then be deposited over fin 210. In an exemplary implementation, an oxide-nitride-oxide (ONO) film may be formed over fin 210. For example, an oxide layer 310 may be formed over fin 210, as illustrated in
A silicon layer 410 may then be formed over semiconductor 100 in a conventional manner, as illustrated in
Silicon layer 410 may then be patterned and etched to form the control gate for semiconductor device 100. For example,
The source/drain regions 220 and 230 may then be doped. For example, n-type or p-type impurities may be implanted in source/drain regions 220 and 230. For example, an n-type dopant, such as phosphorous, may be implanted at a dosage of about 1×1014 atoms/cm2 to about 5×1015 atoms/cm2 and an implantation energy of about 0.5 KeV to about 100 KeV. Alternatively, a p-type dopant, such as boron, may be implanted at similar dosages and implantation energies. The particular implantation dosages and energies may be selected based on the particular end device requirements. One or ordinary skill in this art would be able to optimize the source/drain implantation process based on the circuit requirements. In alternative implementations, source/drain regions 220 and 230 may be doped at an earlier step in the formation of semiconductor device 100, such as prior to formation of ONO layers 310–330. In addition, sidewall spacers may optionally be formed prior to the source/drain ion implantation to control the location of the source/drain junctions based on the particular circuit requirements. Activation annealing may then be performed to activate the source/drain regions 220 and 230.
The resulting semiconductor device 100 illustrated in
Semiconductor device 100 can operate as a non-volatile memory device, such as an EEPROM. Programming may be accomplished by applying a bias of, for example, about 3 to 20 volts to control gate 510 or 520. For example, if the bias is applied to control gate 510, electrons may tunnel from fin substrate 210 into ONO layers 310–330 (i.e., the charge storage electrode). A similar process may occur if the bias is applied to control gate 520. Erasing may be accomplished by applying a bias of, for example, about −3 to −20 volts to control gate 510/520.
Thus, in accordance with the present invention, a non-volatile memory device is formed using a FinFET structure. Advantageously, semiconductor device 100 has a double-gate structure with control gates 510 and 520 formed on either side of fin 210. Each of control gates 510 and 520 may be used to program the memory device. In addition, the FinFET structure enables the resulting memory device 100 to achieve increased circuit density as compared to conventional memory devices. The present invention can also be easily integrated into conventional semiconductor fabrication processing.
The structure of semiconductor device 100 illustrated in
An ONO film 620 may then be formed over fins 610 in a manner similar to that described above with respect to ONO layers 310–330 in
A bit line decoder 640 and word line decoder 650 may then be coupled to the bit lines 610 and word lines 630, respectively. The bit line and word line decoders 640 and 650 may then be used to facilitate programming or reading out data stored in each particular cell of the memory array 600. In this manner, a high density non-volatile memory array may be formed using a FinFET structure.
In other embodiments of the present invention, a memory device with multiple fins may be formed, as illustrated in
Next a low-K material 740, such as a fluorinated oxide, may be deposited to fill the space between the silicon fins 730, as illustrated in
In another embodiment, a FinFET memory device having fins with a small pitch may be formed from a silicon on insulator structure. For example, referring to
In another embodiment, a polysilicon fin may be trimmed to form a T-shaped gate for a memory device. For example, referring to
In yet another embodiment, a FinFET memory device may be formed in a similar manner as that described with respect to
In another embodiment, a semiconductor device 1100 may include a buried oxide layer 1110 formed on a substrate (not shown) with a silicon fin 1120 formed thereon, as illustrated in
In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, the present invention can be practiced without resorting to the specific details set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention.
The dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques. For example, metallization techniques, such as various types of CVD processes, including low pressure CVD (LPCVD) and enhanced CVD (ECVD) can be employed.
The present invention is applicable in the manufacturing of FinFET semiconductor devices and particularly in FinFET devices with design features of 100 nm and below. The present invention is applicable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention. In practicing the present invention, conventional photolithographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail. In addition, while a series of processes for forming the semiconductor device of
Only the preferred embodiments of the invention and a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein.
In addition, no element, act, or instruction used in the description of the present application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is used.
Number | Name | Date | Kind |
---|---|---|---|
5379255 | Shah | Jan 1995 | A |
5382540 | Sharma et al. | Jan 1995 | A |
5959328 | Krautschneider et al. | Sep 1999 | A |
5973356 | Noble et al. | Oct 1999 | A |
6207515 | Hsieh et al. | Mar 2001 | B1 |
6440801 | Furukawa et al. | Aug 2002 | B1 |
6551880 | Lai et al. | Apr 2003 | B1 |
6580124 | Cleeves et al. | Jun 2003 | B1 |
6727544 | Endoh et al. | Apr 2004 | B2 |
6768158 | Lee et al. | Jul 2004 | B2 |
6768166 | Hagemeyer | Jul 2004 | B2 |
20020028541 | Lee et al. | Mar 2002 | A1 |
20030042531 | Lee et al. | Mar 2003 | A1 |
20030235075 | Forbes | Dec 2003 | A1 |
20040235300 | Mathew et al. | Nov 2004 | A1 |
Number | Date | Country |
---|---|---|
102 20 923 | Nov 2003 | DE |
Number | Date | Country | |
---|---|---|---|
20040251487 A1 | Dec 2004 | US |