Patent Application
20120280303
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-102816, filed on May 2, 2011; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a non-volatile semiconductor memory device and a method of manufacturing the same.
In the field of NAND flash memories, as a result of the rapid advance in downsizing of device size for a reduction in cost through enhancement of bit density, cell size has nearly reached a physical limit of operation or processing. Therefore, a stacked nonvolatile memory formed by three-dimensionally stacking memory cells attracts attention as means for attaining higher bit density. As the stacked nonvolatile memory, stacked nonvolatile memories of a metal-oxide-nitride-oxide-semiconductor (MONOS) type and a floating gate type in which a floating gate is formed in a doughnut shape are proposed.
However, in the stacked nonvolatile memory of the MONOS type, reliability of a memory operation is low. It is difficult to realize a multi-value operation such as multi-level-cell (MLC: information for two bits is stored in one memory cell) and triple-level-cell (TLC: information for three bits is stored in one memory cell) universally used in a floating gate structure.
In the stacked nonvolatile memory in which the floating gate electrode film is formed in a doughnut shape, a projection area of a memory cell (corresponding to a cell area in a planar floating gate type structure) is large. The structure and the process of the stacked nonvolatile memory are substantially different from those of a nonvolatile memory of a planar floating gate type widely used in the past. This hinders replacement of the nonvolatile memory of the planar floating gate type in the past with the stacked nonvolatile memory.
In general, according to one embodiment, first, a stacked structure including a plurality of layers in which a spacer film and a channel semiconductor film are alternately stacked is formed above a substrate. Next, a first trench extending in a first direction is formed in the stacked structure, and a first space is formed by forming a recess in the channel semiconductor films from the first trench in a second direction perpendicular to the first direction. Thereafter, a tunnel dielectric film is formed on the channel semiconductor films in the first space, and the first space in which the tunnel dielectric film is formed is filled with a floating gate electrode film. Then, second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but so as not to divide the channel semiconductor films. The stacked structure is divided at predetermined interval in the second direction so that the channel semiconductor films are divided between memory cells adjacent to each other in the second direction.
Hereinafter, a non-volatile semiconductor memory device and a method of manufacturing the same according to exemplary embodiments will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. Cross-sectional views of a non-volatile semiconductor memory device used in the following embodiments are schematic views, and a relation between a thickness and a width of layers, a radio between thicknesses of layers, and the like may differ from actual ones. In addition, film thicknesses used in the following description are examples, and the present invention is not limited thereto.
The non-volatile semiconductor memory device has a structure in which a plurality of NAND string stacks NSS are arranged, in the X direction and the Y direction, on an ILD film 102 formed on a semiconductor substrate 101. The NAND string stack NSS has a structure in which a plurality of NAND strings NS are stacked, in the Z direction, through spacer films 104. The NAND string NS extends in the X direction and includes a plurality of memory cell transistors (hereinafter, referred to as “memory cell”) MC formed in series in the X direction on one main surface of a channel semiconductor film 103, which is an active area of a sheet shape parallel to a substrate surface, in the Y direction. Here, a NAND string group NSG includes a pair of NAND string stacks NSS arranged so that forming surfaces of memory cells MC can face each other. The NAND string groups NSG are arranged on the semiconductor substrate 101 in a matrix shape. The adjacent NAND string groups NSG are isolated by a gap-fill dielectric film 106.
The memory cell MC has a floating gate type structure. The memory cell MC includes a floating gate electrode film 109 extending in the Y direction and a pair of control gate electrode films 111M which are provided on both sides of the floating gate electrode film 109 in the Z direction. The floating gate electrode film 109 is formed above the channel semiconductor film 103 through the tunnel dielectric film 108. The control gate electrode film 111M is arranged to face the floating gate electrode film 109 through an inter-poly dielectric (IPD) film 110.
The control gate electrode film 111M includes a common connecting section 1111 extending in the Z direction and electrode forming sections 1112 that protrude from the common connecting section 1111 in the Y direction and are provided on both sides of the floating gate electrode film 109 in the Z direction through the IPD film 110. Thus, the control gate electrode film 111M is shared between the memory cells MC arranged in the Z direction. The electrode forming section 1112 is provided, above a side surface of the spacer film 104 in the Y direction through the IPD film 110, between the floating gate electrode films 109 arranged in the Z direction. Further, the control gate electrode film 111M is shared between one memory cell row arranged in the Z direction and another memory cell row faced by the forming surface of the memory cell MC of one memory cell row. In this example, the control gate electrode film 111M is configured with a film formed such that a conductive film 112 filled in a space between a pair of memory cell rows having the memory cells MC whose forming surfaces face each other, a conductive film 113 provided on the conductive film 112, and a silicide film 119 are stacked.
A sidewall film 116 made of an insulating material is filled in a space between the memory cells MC (the floating gate electrode film 109 and the control gate electrode film 111M) adjacent to each other in the X direction, and between the memory cell MC and the selection transistor ST.
The selection transistors ST, which control a connection with a source region or a drain region, are provided on both ends of the NAND string NS. The selection transistor ST includes a selection gate electrode film 1115 arranged, through the tunnel dielectric film 108, above one main surface of the channel semiconductor film 103 in the Y direction at both end portions of the memory cells MC arranged in the X direction. The selection gate electrode film 111S has a structure in which in a stacking structure of the IPD film 110, the conductive film 112, and the floating gate electrode film 109, the conductive film 113 is filled in a through hole extending in the Z direction by partially removing the IPD film 110, and the silicide film 119 is formed on the conductive film 113. That is, the selection gate electrode film 111S is configured with the floating gate electrode film 109, the conductive films 112 and 113, and the silicide film 119, and the selection gate electrode film 111S is shared between the selection transistors ST arranged in the Z direction. Further, similarly to the control gate electrode film 111M, the selection gate electrode film 111S is also shared between selection transistor ST rows, facing each other, within the NAND string group NSG. A source side selection transistor ST is arranged on one end of the NAND string NS in the X direction, and a drain side selection transistor ST is arranged on the other end of the NAND string NS.
The source region is provided on one end of the channel semiconductor film 103 in the X direction at the side at which the source side selection transistor ST is arranged, and the channel semiconductor films 103 that configure the NAND strings NS of the same height adjacent to each other in the Y direction are connected to each other. A lead-out section 180 connected to the cell array outside is provided. The lead-out section 180 has a step-like shape so that the channel semiconductor film 103 positioned in a lower layer can be exposed. A source line contact SC is provided on each step-difference portion and is connected to a source line SL, which extends in the X direction, above the cell array.
The drain region is provided on one end of the channel semiconductor film 103 in the X direction at the side at which the drain side selection transistor ST is arranged. In the drain region, end portions of the NAND strings NS adjacent to each other in the Z direction are connected to each other by a drain region connection contact 113D of a pillar shape extending in the Z direction. For example, the drain region connection contact 113D is made of the same material as the conductive film 113. Further, the drain region connection contact 113D is connected to a bit line BL extending in the X direction, through a bit line contact BC, above the drain region connection contact 113D.
The drain region connection contact 113D is provided for each NAND string stack NSS, and the drain region connection contacts 113D, adjacent to each other in the Y direction, within the NAND string group NSG are isolated from each other by a dielectric film. In this example, the dielectric film is configured with the sidewall film 116 formed along an inner wall of an isolation trench for isolating the drain region connection contacts 113D from each other, a dielectric film 117 covering the inner surface of the isolation trench, and a gap-fill dielectric film 118 filled in the isolation trench.
The control gate electrode film 111M, which connects the memory cells MC arranged in the Z direction to each other, is connected to a word line WL extending in the Y direction, through a word line contact WC, above the control gate electrode film 111M. Similarly, the selection gate electrode film 1115, which connects the selection transistors ST arranged in the Z direction, is connected to a selection gate line SG extending in the Y direction, through a selection gate line contact SGC, above the selection gate electrode film 1115.
For example, the semiconductor substrate 101 and the channel semiconductor film 103 may be made of a material selected from among Si, Ge, SiGe, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, InGaAsP, and the like. The channel semiconductor film 103 may be made of a single crystalline semiconductor or a poly crystalline semiconductor.
For example, a silicon oxide film may be used as the tunnel dielectric film 108. An amorphous silicon film, a polysilicon film, or the like into which impurities such as phosphorous (P) or boron (B) is doped may be used as the floating gate electrode film 109. Further, a silicon oxide film or the like may be used as the IPD film 110. Further, as the control gate electrode film 111M and the selection gate electrode film 111S, a metal film made of W, TaN, WN, TiAlN, TiN, WSi, CoSi, NiSi, PrSi, NiPtSi, PtSi, Pt, Ru, or the like, RuO2, a B-doped polysilicon film, a P-doped polysilicon film, a silicide film, or a stacked film thereof can be used.
The example of the drawings illustrates the structure in which 6 channel semiconductor films 103 are stacked in the Z direction. However, the number of stacked channel semiconductor films 103 is not limited thereto, and an arbitrary number of channel semiconductor films 103 may be stacked. Further, the number of memory cells MC formed on one channel semiconductor film 103 in the X direction may be an arbitrary number. The memory cell MC arranged at a position adjacent to the selection transistor ST may deteriorate due to influence of strong electric field caused by the selection transistor ST, and so may function as not an actual memory cell but a dummy memory cell.
In the non-volatile semiconductor memory device having the above configuration, an arbitrary memory cell MC is selected such that a position on a plane parallel to the semiconductor substrate 101 is selected through the word line WL and the bit line BL and a stacked layer is selected through the source line SL. The memory cell MC does not individually include an impurity diffusion region that functions as the source/drain region. By forming a depletion layer in the channel semiconductor film 103 between the adjacent control gate electrode films 111M through fringing field formed by applying a voltage to each control gate electrode films 111M, formed is a channel connected to the entire channel semiconductor film 103.
Each memory cell transistor MC is an inversion type transistor or a depletion type transistor having no source/drain structure. Typically, in memory cells MC having no source/drain structure, a region where high-concentration electrons exist is not present in a channel, even though Vpass is applied to a non-selected cell, a program disturb or read disturb hardly occurs.
A writing operation on an arbitrary floating gate electrode film 109 is performed such that electrons are injected from the source region into the selected memory cell MC through the depletion layer formed in the channel semiconductor film 103. An erasing operation is performed such that electrons are collectively pulled out from the floating gate electrode films 109 of all memory cells MC on the channel semiconductor film 103 by increasing electric potential of the channel semiconductor film 103. A method of selecting an arbitrary memory cell MC is not limited to the above example since a plurality of methods or wiring structures are present.
Next, a description will be made in connection with a method of manufacturing the non-volatile semiconductor memory device having the above structure.
In the following, described is an example of manufacturing a non-volatile semiconductor memory device having a structure in which 6 layers each of which includes the channel semiconductor film 103 and the spacer film 104 are stacked at a pitch of 60 nm in parallel to the semiconductor substrate 101, a half pitch in the Y direction is 62 nm, and a half pitch in the X direction is 25 nm. As a result, bit density equal to a NAND type flash memory of a two-dimensional structure (a planar floating gate type structure) in which a half pitch is 16.1 nm can be achieved. Further, a method of forming a peripheral circuit and a lead-out portion is the same as in a method of forming a typical non-volatile semiconductor memory device or a typical stacked non-volatile semiconductor memory device, and thus a detailed description thereof will not be provided.
First, as illustrated in
Thereafter, a plurality of layers (here, 6 layers) in which a channel semiconductor film 103 and a spacer film 104 are alternately stacked are formed on the ILD film 102. For example, an amorphous silicon film having a thickness of 20 nm may be used as the channel semiconductor film 103, and a silicon oxide film having a thickness of 40 nm may be used as the spacer film 104.
Further, a hard mask film 105 is formed on the spacer film 104 of the top layer. For example, a silicon nitride film having a thickness of 50 nm may be used as the hard mask film 105. Further, the hard mask film 105 may be formed using SiCN, SiBN, alumina, titania, zirconia, or the like besides the silicon nitride film. However, the hard mask film 105 is preferably formed using a material that is easily recess-etched.
Next, as illustrated in
Thereafter, a gap-fill dielectric film 106 is formed in the trench 151. The top surface of the gap-fill dielectric film 106 is planarized using a chemical mechanical polishing (CMP) technique, and so the top surface of the hard mask film 105 is exposed in a region other than the position at which the trench 151 is formed. For example, a silicon oxide film formed by a chemical vapor deposition (CVD) technique may be used as the gap-fill dielectric film 106. Then, a hard mask film 107 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 100 nm may be used as the hard mask film 107.
Next, as illustrated in
Thereafter, as illustrated in
Next, a tunnel dielectric film 108 is formed on a side surface of the channel semiconductor film 103 inside the space 153. For example, the tunnel dielectric film 108 may be formed using a technique such as thermal oxidation technique and a plasma nitridation technique. For example, the thickness of the tunnel dielectric film 108 may be set to 8 nm. Then, a floating gate electrode film 109 is formed over the entire surface of the semiconductor substrate 101. For example, a P-doped amorphous silicon film having a thickness of 15 nm formed by a low pressure CVD (LPCVD) technique may be used as the floating gate electrode film 109. Thereafter, the floating gate electrode film 109 is dry-etched so that the floating gate electrode film 109 can remain only in the space 153 formed by recess-etching the channel semiconductor film 103. For example, chlorine gas may be used as etching gas.
Next, as illustrated in
Further, as illustrated in
Next, as illustrated in
Subsequently, a conductive film 112 is formed over the entire surface of the semiconductor substrate 101. Here, the conductive film 112 is filled in the trench 152 and the space 154 formed in the trench 152. For example, a P-doped polysilicon film having a thickness of 50 nm may be used as the conductive film 112. The conductive film 112 functions as part of the control gate electrode film 111M and part of the selection gate electrode film 1115, and has a structure in which the electrode forming section 1112 is formed in the space 154, and the electrode forming sections 1112 of the control gate electrode films 111M, which are stacked in the Z direction through the IPD film 110, are connected to each other, between the floating gate electrode films 109, by the common connecting section 1111 extending in the Z direction.
Thereafter, a mask film (not illustrated) is formed over the semiconductor substrate 101, and a selection gate electrode film-forming trench 155 and a drain region connection contact forming trench 156 are formed by a lithography technique and an RIE technique. The selection gate electrode film-forming trench 155 is formed by collectively processing the stacked films so that the floating gate electrode films 109, the IPD films 110, and the conductive films 112 of a pair of NAND string stacks NSS, which face each other, in the forming regions of the selection transistors ST can be partially removed and so the conductive film 112 of the lowest layer can be exposed. The drain region connection contact forming trench 156 is formed by collectively processing the stacked films in part of the drain region of each NAND string stack NSS so that the conductive film 112 of the lowest layer can be exposed. Here, the drain region connection contact forming trench 156 is formed in a region between the gap-fill dielectric films 106 of the pair of NAND string stacks NSS. For example, a CVD carbon film may be used as the mask film. After the selection gate electrode film-forming trench 155 and the drain region connection contact forming trench 156 are formed, the mask film is removed.
Thereafter, a conductive film 113 is filled in the selection gate electrode film-forming trench 155 and the drain region connection contact forming trench 156. For example, a P-doped polysilicon film having a thickness of 80 nm may be used as the conductive film 113. As a result, in the forming region of the selection transistor ST, the floating gate electrode film 109 and the conductive films 112 and 113 are physically connected to each other. Subsequently, a hard mask film 114, which will be used later for processing the control gate electrode film, is formed over the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 150 nm may be used as the hard mask film 114.
Next, as illustrated in
Thereafter, the entire surface over the semiconductor substrate 101 is coated with a photoresist film. The photoresist film is patterned by a lithography technique to cover a non-processed region, so that a photoresist pattern 115 is formed. The photoresist pattern 115 may be formed to protect the channel semiconductor film 103 (the active area) of the memory cell MC as illustrated in
Next, as illustrated in
Thereafter, as illustrated in
Thereafter, as illustrated in
Then, an ILD film (not illustrated) is formed, and thereafter a contact plug and a wiring are formed. However, the contact plug and the wiring may be formed using a known technique, and thus a detailed description thereof will not be provided. Through the above process, the non-volatile semiconductor memory device according to the first embodiment is obtained.
In the stacked non-volatile semiconductor memory device, the erasing operation tends to be more difficult than the writing operation. It is because unlike the planar floating gate type structure, it is difficult to apply an erasing voltage to a semiconductor channel through a substrate, and instead channel potential has to be raised by a voltage supplied from a source line SL. In this regard, by employing the structure illustrated in
In the first embodiment, a plurality of sheet shaped channel semiconductor films 103, which are parallel to the substrate surface and extend in the X direction, are stacked in the Z direction through the spacer films 104. The floating gate electrode films 109, which extend in the Y direction, are provided at predetermined intervals in the X direction on one side surfaces of the channel semiconductor films 103 in the Y direction through the tunnel dielectric film 108. Further, the control gate electrode films 111M are provided on both surfaces of the floating gate electrode film 109 in the Z direction through the IPD film 110. Further, the control gate electrode film 111M is provided to connect the memory cells MC arranged in the Z direction with each other. As a result, there are advantages of minimizing the projected area of the memory cell MC and increasing the memory density while suppressing the number of stacked layers. Further, each memory cell MC has the same structure of the planar floating gate type structure which has been widely used in the past. Thus, the conventional planar floating gate type structure can be easily replaced with the stacked non-volatile semiconductor memory device having higher bit density, and the same memory performance as in the conventional planar floating gate type structure can be realized. Further, since a structure in which the memory cells MC having the planar floating gate type structure already proven as the non-volatile semiconductor memory device are stacked, reliability can be easily secured, and a user learning period can be shortened.
Further, the floating gate electrode film 109 is not formed on the both side surfaces of the whole circumference of the channel semiconductor film 103. The floating gate electrode film 109 is only formed on one side surface of the channel semiconductor film 103 in the Y direction, however, the floating gate electrode film 109 is not formed on the opposite other side surface. As a result, the back gate electrode film 121 can be arranged on the other side of the surface side, and thus there is an effect capable of further improving erasing characteristics of the memory cell MC.
In addition, since a shape in which the stacked films can be collectively processed is provided, the memory cells MC can be stacked without significantly increasing the number of processes, and thus the bit capacity per unit area can be enhanced. That is, there is an effect capable of improving a degree of integration without performing scaling down.
Further, after the spacer film 104, which corresponds to a shallow trench isolation (STI) of a typical floating gate memory cell MC, is formed, the tunnel dielectric film 108 and the floating gate electrode film 109 are formed on the channel semiconductor film 103, and further the IPD film 110 and the control gate electrode film 111M are formed by forming a recess in the spacer film 104. As described above, there are effects capable of forming through a manufacturing process flow, which is substantially the same as the typical floating gate type structure, and relatively easily controlling the shape of the floating gate electrode film 109.
The first embodiment has been described in connection with the structure in which the control gate electrode films of the memory cell are arranged on both sides in the Z direction. However, a second embodiment will be described in connection with a non-volatile semiconductor memory device having a structure in which the control gate electrode films are arranged on both sides in the X direction.
The non-volatile semiconductor memory device has a structure in which a plurality of NAND string stacks NSS are arranged, in the X direction and the Y direction, above a semiconductor substrate 101. The NAND string stack NSS has a structure in which a plurality of NAND strings NS are stacked, in the Z direction, through spacer films 104. The NAND string NS extends in the X direction and includes a plurality of memory cell transistors MC formed in series in the X direction on one main surface of a channel semiconductor film 103, which is an active area of a sheet shape parallel to a substrate surface, in the Y direction. Here, a NAND string group NSG includes a pair of NAND string stacks NSS arranged so that forming surfaces of memory cells MC can face each other. The NAND string groups NSG are arranged on the semiconductor substrate 101 in a matrix shape. The adjacent NAND string groups NSG are isolated by a gap-fill dielectric film 106.
The memory cell MC has a floating gate type structure. The memory cell MC includes a floating gate electrode film 109 extending in the Y direction and a pair of control gate electrode films 111M which are arranged, on both sides of the floating gate electrode film 109 in the X direction, to face each other. The floating gate electrode film 109 is formed above the channel semiconductor film 103 through the tunnel dielectric film 108. The control gate electrode film 111M is provided, between the floating gate electrode films 109 of the memory cells MC adjacent to each other in the X direction, above the channel semiconductor film 103, through an inter-poly dielectric (IPD) 110. The control gate electrode film 111M is shared between the memory cells MC adjacent to each other in the Z direction. Further, the control gate electrode film 111M is shared between the memory cells MC of a pair of NAND string stacks NSS in which the forming surfaces of the memory cells MC face each other.
The spacer film 104 isolates the memory cells MC (the floating gate electrode films 109) adjacent to each other in the Z direction from each other and isolates the selection transistors ST from each other. Between the floating gate electrode films 109 of the memory cells MC, which are adjacent to each other in the Y direction and share the control gate electrode film 111M, a gap-fill dielectric film 131, which isolates the floating gate electrode films 109, is provided. The other components are substantially the same as in the first embodiment and are denoted by the same reference numerals, and the redundant description will not be repeated.
In the non-volatile semiconductor memory device having the above configuration, an arbitrary memory cell MC is selected such that a position on a plane parallel to the semiconductor substrate 101 is selected through two neighboring word lines WL sandwiching the floating gate electrode film 109 of the selected cell and one bit line BL and a stacked layer is selected through the source line SL. The memory cell MC does not individually include an impurity diffusion region that functions as the source and drain regions. By an electric field which is generated by applying a voltage to each control gate electrode films 111M so that a depletion layer is formed in the channel semiconductor film 103 under the floating gate electrode film 109 and the channel semiconductor film 103 directly below the control gate electrode films 111M, formed is a channel connected to the entire channel semiconductor film 103.
Each memory cell MC is an inversion type transistor or a depletion type transistor having no source/drain structure. As will be described later, in the structure according to the second embodiment, it is not necessary to form the control gate electrode film 111M by collectively processing layers in the complicated stacked structure described in the first embodiment, however, a voltage may be applied even to a non-selected cell next to the selected. However, in the structure of the memory cell having no impurity diffusion region, a region where high-concentration electrons exist is not present in a channel, even though Vpass is applied to a non-selected cell, a program disturb or read disturb hardly occurs. The writing operation and the erasing operation on an arbitrary floating gate electrode film 109 are the same as in the first embodiment, and the redundant description will not be repeated.
Next, a description will be made in connection with a method of manufacturing the non-volatile semiconductor memory device having the above structure.
In the following, described is an example of manufacturing a non-volatile semiconductor memory device having a structure in which 6 layers each of which includes the channel semiconductor film 103 and the spacer film 104 are stacked at a pitch of 40 nm in parallel to the semiconductor substrate 101, a half pitch in the Y direction is 62 nm, and a half pitch in the X direction is 30 nm. As a result, bit density equal to a NAND flash type memory of a two-dimensional structure in which a half pitch is 17.0 nm can be achieved. Further, a method of forming a peripheral circuit and a lead-out portion is the same as in a method of forming a typical non-volatile semiconductor memory device or a typical stacked non-volatile semiconductor memory device, and thus a detailed description thereof will not be provided.
First, as illustrated in
Thereafter, a plurality of layers (here, 6 layers) in which a channel semiconductor film 103 and a spacer film 104 are alternately stacked are formed on the ILD film 102. For example, an amorphous silicon film having a thickness of 15 nm may be used as the channel semiconductor film 103, and a silicon oxide film having a thickness of 25 nm may be used as the spacer film 104. Further, a hard mask film 105 is formed on the spacer film 104 of the top layer. For example, a silicon nitride film having a thickness of 50 nm may be used as the hard mask film 105. Further, it is desirable to reduce a channel width (the thickness of the channel semiconductor film 103) so as to achieve a high coupling ratio (CR) in the above structure.
Then, by collectively processing the stacked films, which includes the hard mask film 105, the spacer film 104, and the channel semiconductor film 103, using a lithography technique and an RIE technique, a trench 151, which extends in the X direction to expose a part of the ILD film 102, is formed at a predetermined pitch in the Y direction. For example, the width of the trench 151 may be set to 25 nm, and the pitch may be set to 232 nm. The trench 151 corresponds to one which divides the stacked film in association with an area for forming the NAND string group NSG, and isolates the channel semiconductor films 103 of the memory cells MC, adjacent to each other in the Y direction, in the adjacent NAND string group NSG, in
Thereafter, a gap-fill dielectric film 106 is formed in the trench 151. The top surface of the gap-fill dielectric film 106 is planarized using a CMP technique, and so the hard mask film 105 is exposed in a region other than the position at which the trench 151 is formed. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 106. Then, a hard mask film 107 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 100 nm may be used as the hard mask film 107.
Next, as illustrated in
Thereafter, a space 153 is formed by forming a recess in the channel semiconductor film 103 by a predetermined amount in the Y direction by using an etching technique. For example, a wet etching technique using choline, a CDE technique, a dry etching technique using chlorine gas, or the like may be used as the etching technique. For example, the recess amount of the channel semiconductor film 103 may be set to 60 nm.
Next, a tunnel dielectric film 108 is formed on a side surface of the channel semiconductor film 103 inside the space 153. For example, the tunnel dielectric film 108 may be formed using a technique such as thermal oxidation technique and a thermal nitridation technique, and the thickness of the tunnel dielectric film 108 may be set to 8 nm. Then, a floating gate electrode film 109 is formed over the entire surface of the semiconductor substrate 101. For example, a P-doped amorphous silicon film having a thickness of 15 nm may be used as the floating gate electrode film 109. Thereafter, the floating gate electrode film 109 is etched by a dry etching technique so that the floating gate electrode film 109 can remain only in the space 153 formed by recess-etching the channel semiconductor film 103. For example, chlorine gas may be used as etching gas.
Further, the hard mask films 107 and 105 are isotropically etched from an end portion of the floating gate electrode film 109 in the Y direction by a predetermined amount. For example, a wet etching technique using a hot phosphoric acid may be used as the isotropic etching technique. For example, the recess amount of the hard mask films 107 and 105 may be set to 60 nm. The recess amount of the hard mask films 107 and 105 is set to cause the channel semiconductor film 103 to be protected in a self-aligning manner when an electrode pattern forming trench is formed later, similarly to the first embodiment.
Thereafter, the gap-fill dielectric film 131 is formed in the trench 152, and a planarization process is performed using a CMP technique until the hard mask film 107 is exposed in an area other than the forming position of the trench 152. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 131.
Next, as illustrated in
Thereafter, a conductive film 113 is filled in the selection gate electrode film-forming trench 155 and the drain region connection contact forming trench 156. Then, a planarization process is performed using a CMP technique. For example, an As-doped amorphous silicon film may be used as the conductive film 113. As a result, in the forming region of the selection transistor ST, a common connection between the floating gate electrode films 109 of the memory cells MC facing each other through the gap-fill dielectric film 131 therebetween is made by the conductive film 113. The selection gate electrode film 111S is configured with the floating gate electrode film 109 and the conductive film 113. The drain region connection contact 113D is formed in the drain region connection contact forming trench 156.
In addition, a hard mask film 114, which will be used later for processing the control gate electrode film 111M, is formed over the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 150 nm may be used as the hard mask film 114.
Next, as illustrated in
Further, the hard mask films 107 and 105 are formed to protect the channel semiconductor film 103 from being etched when the control gate electrode film-forming trench 159 is processed. Thus, even though precise overlay is not performed, the channel semiconductor film 103 of the memory cell MC can be protected in a self-aligning manner. The hard mask films 107 and 105 are preferably made of a material capable of easily obtaining selectivity when the control gate electrode film-forming trench 159 is processed. The hard mask films 107 and 105 may be formed of a dielectric film made of SiBN, SiCN, alumina, titania, hafnia, zirconia, or the like, instead of the silicon nitride film.
Next, as illustrated in
Then, a conductive film 112 is filled in the control gate electrode film-forming trench 159. For example, a TaN/W stacked film having a thickness of 50 nm formed by a CVD technique may be used as the conductive film 112. Thereafter, a portion of the conductive film 112 formed in a region other than the control gate electrode film-forming trench 159 is removed using a CMP technique.
Thereafter, a dielectric film 132 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 30 nm formed by an LPCVD technique may be used as the dielectric film 132. As a result, the conductive film 112 filled in the control gate electrode film-forming trench 159 becomes the control gate electrode film 111M. As described above, in the structure of the second embodiment, there is an advantage of relatively easier metallization of the control gate electrode film 111M.
Then, an ILD film is formed, and thereafter, a contact plug and a wiring are formed. However, the contact plug and the wiring may be formed using a known technique, and thus a detailed description thereof will not be provided. Through the above process, the non-volatile semiconductor memory device according to the second embodiment is obtained.
Further, there may be provided a configuration in which a back gate electrode film is formed, on a surface opposite to the memory cell forming surface of the channel semiconductor film 103, through a gate dielectric film, similarly to
In the second embodiment, it is sufficient if the control gate electrode film-forming trench 159 is formed in the stacked film including the channel semiconductor film 103 and the spacer film 104 when the control gate electrode film 111M is processed. Thus, there is an advantage in that collective processing is easier than that of the first embodiment.
A third embodiment will be described in connection with a manufacturing method capable of further reducing a stacked film thickness of a memory cell by processing an end portion of a floating gate electrode film in the non-volatile semiconductor memory device having the structure according to the first embodiment illustrated in
In the following, a description will be made in connection with an example capable of achieving the same bit density as in a NAND flash type memory of a two-dimensional structure whose half pitch is 21.2 nm when 4 layers each of which includes a channel semiconductor film 103 and a spacer film 104 are stacked in parallel to a semiconductor substrate 101.
First, similarly to the process according to the first embodiment illustrated in
Thereafter, a plurality of layers (here, 4 layers) in which a channel semiconductor film 103 and a spacer film 104 are alternately stacked are formed on the ILD film 102. For example, an amorphous silicon film having a thickness of 20 nm may be used as the channel semiconductor film 103, and a silicon oxide film having a thickness of 20 nm may be used as the spacer film 104.
Further, a hard mask film 105 is formed on the spacer film 104 of the top layer. For example, a silicon nitride film having a thickness of 50 nm may be used as the hard mask film 105. Thereafter, by collectively processing the stacked films, which includes the hard mask film 105, the spacer film 104, and the channel semiconductor film 103, using a lithography technique and an RIE technique, a trench 151, which extends in the X direction to expose a part of the ILD film 102, is formed at a predetermined pitch in the Y direction. For example, the width of the trench 151 may be set to 25 nm, and the pitch may be set to 288 nm. The trench 151 corresponds to one which divides the stacked film in association with an area for forming the NAND string group NSG, and isolates the channel semiconductor films 103 of the memory cells MC, adjacent to each other, in the NAND string groups NSG adjacent to each other in the Y direction, in
Thereafter, a gap-fill dielectric film 106 is formed in the trench 151. The top surface of the gap-fill dielectric film 106 is planarized using a CMP technique, and so the hard mask film 105 is exposed in a region other than the position at which the trench 151 is formed. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 106. Then, a hard mask film 107 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 100 nm may be used as the hard mask film 107.
Next, by collectively processing the stacked films, which includes the hard mask films 107 and 105, the spacer film 104, and the channel semiconductor film 103, using a lithography technique and an RIE technique, a trench 152, which extends in the X direction to expose a part of the ILD film 102, is formed at a predetermined pitch in the Y direction. For example, the width of the trench 152 may be set to 40 nm. The trench 152 corresponds to one which divides an area for forming the NAND string stack NSS in
Thereafter, a space 153 is formed by etching the channel semiconductor film 103 by a predetermined amount in the Y direction. For example, a wet etching technique using choline, a CDE technique, a dry etching technique using chlorine gas, or the like may be used as the etching technique. For example, the recess amount of the channel semiconductor film 103 may be set to 50 nm.
Next, a tunnel dielectric film 108 is formed on a side surface of the channel semiconductor film 103 inside the space 153. For example, the tunnel dielectric film 108 may be formed using a technique such as plasma oxidation technique and a plasma nitridation technique. For example, the thickness of the tunnel dielectric film 108 may be set to 8 nm. Then, a floating gate electrode film 109 is formed over the entire surface of the semiconductor substrate 101. For example, a P-doped amorphous silicon film having a thickness of 20 nm may be used as the floating gate electrode film 109. Thereafter, the floating gate electrode film 109 is etched by a dry etching technique so that the floating gate electrode film 109 can remain only in the space 153. For example, chlorine gas may be used as etching gas.
Next, as illustrated in
Then, an oxide film 133 is formed on the surface of the floating gate electrode film 109. For example, a silicon oxide film having a thickness of 5 nm formed by plasma oxidizing the surface of the floating gate electrode film 109 may be used as the oxide film 133.
Next, as illustrated in
Thereafter, the hard mask films 107 and 105 are isotropically etched from the end portion of the floating gate electrode film 109 by a predetermined amount. For example, a wet etching technique using a hot phosphoric acid may be used as the isotropic etching technique. For example, the recess amount of the hard mask films 107 and 105 may be set to 50 nm.
Next, as illustrated in
Thereafter, performed is a process of forming the selection gate electrode film-forming trench 155 and the drain region connection contact forming trench 156 illustrated in
In the third embodiment, after the spacer film 104 corresponding to the STI of the typical floating gate NAND flash type memory is formed, the tunnel dielectric film 108 and the floating gate electrode film 109 are formed on the channel semiconductor film 103. Next, a recess is formed in the spacer film 104, and further the end portion of the floating gate electrode film 109 is slimmed. As a result, there is an effect capable of forming a space in which the IPD film 110 and the control gate electrode film 111M are formed by the substantially same manufacturing process flow of the typical NAND flash type memory of floating gate type. Further, the final structure of the memory cell MC hardly differs in shape from the typical floating gate type structure, and the almost same memory performance as in the conventional floating gate type structure can be realized. In addition, since the stacked film thickness per layer can be reduced, it is effective, particularly, when the number of stacked layers is increased.
A fourth embodiment will be described in connection with a manufacturing method capable of further reducing a projected area of a memory cell by processing an end portion of a floating electrode film in the non-volatile semiconductor memory device having the structure according to the first embodiment illustrated in
In the following, a description will be made in connection with an example capable of achieving the same bit density as in a NAND flash type memory of a two-dimensional structure (a planar floating gate type structure) whose half pitch is 19.0 nm when 4 layers each of which includes a channel semiconductor film 103 and a spacer film 104 are stacked in parallel to a semiconductor substrate 101.
First, as illustrated in
Subsequently, a plurality of layers (here, 4 layers) in which a channel semiconductor film 103 and a spacer film 104 are alternately stacked are formed on the ILD film 102. For example, an amorphous silicon film having a thickness of 20 nm may be used as the channel semiconductor film 103, and a silicon oxide film having a thickness of 75 nm may be used as the spacer film 104.
Further, a hard mask film 105 is formed on the spacer film 104 of the top layer. For example, a silicon nitride film having a thickness of 50 nm may be used as the hard mask film 105. Thereafter, by collectively processing the stacked films, which includes the hard mask film 105, the spacer film 104, and the channel semiconductor film 103, using a lithography technique and an RIE technique, a trench 151, which extends in the X direction to expose a part of the ILD film 102, is formed at a predetermined pitch in the Y direction. For example, the width of the trench 151 may be set to 25 nm, and the pitch may be set to 232 nm. The trench 151 corresponds to one which divides the stacked film in association with an area for forming the NAND string group NSG, and isolates the channel semiconductor films 103 of the memory cells MC, adjacent to each other, in the NAND string groups NSG adjacent to each other in the Y direction, in
Thereafter, a gap-fill dielectric film 106 is formed in the trench 151. The top surface of the gap-fill dielectric film 106 is planarized using a CMP technique, and so the hard mask film 105 is exposed in a region other than the position at which the trench 151 is formed. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 106. Then, a hard mask film 107 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 100 nm may be used as the hard mask film 107.
Next, a mask film (not illustrated) is formed over the entire surface of the semiconductor substrate 101. By collectively processing the stacked films, which includes the hard mask films 107 and 105, the spacer film 104, and the channel semiconductor film 103, using a lithography technique and an RIE technique, a trench 152, which extends in the X direction to expose a part of the ILD film 102, is formed at a predetermined pitch in the Y direction. For example, the width of the trench 152 may be set to 30 nm. The trench 152 divides an area for forming the NAND string stack NSS in
Thereafter, a space 153 is formed by forming a recess in the channel semiconductor film 103 by a predetermined amount in the Y direction by using an etching technique. For example, a wet etching technique using choline, a CDE technique, a dry etching technique using chlorine gas, or the like may be used as the etching technique. For example, the recess amount of the channel semiconductor film 103 may be set to 60 nm.
Next, a tunnel dielectric film 108 is formed on a side surface of the channel semiconductor film 103 inside the space 153. For example, the tunnel dielectric film 108 may be formed using a technique such as plasma oxidation technique and a thermal nitridation technique. For example, the thickness of the tunnel dielectric film 108 may be set to 8 nm. Then, a conductive film 134 functioning as part of the floating gate electrode film 109 is formed over the entire surface of the semiconductor substrate 101. For example, a P-doped amorphous silicon film having a thickness of 20 nm may be used as the conductive film 134. Thereafter, the conductive film 134 is continuously etched by a dry etching technique so that the conductive film 134 is removed by a predetermined amount (e.g., 30 nm) from an end portion of the space 153 (an end portion of the spacer film 104 in the Y direction), formed by recess-etching the channel semiconductor film 103. For example, chlorine gas may be used as etching gas.
Next, as illustrated in
Then, a conductive film 135 functioning as part of the floating gate electrode film 109 is formed over the entire surface of the semiconductor substrate 101, and the conductive film 135 is etched by a dry etching technique to remain only in the space 160. For example, a P-doped amorphous silicon film having a thickness of 20 nm may be used as the conductive film 135. For example, chlorine gas may be used as etching gas. The floating gate electrode film 109 is configured with the conductive films 134 and 135.
Next, as illustrated in
In addition, the hard mask films 107 and 105 are isotropically etched by a predetermined amount. For example, a wet etching technique using a hot phosphoric acid may be used as the isotropic etching technique. For example, the recess amount of the hard mask films 107 and 105 may be set to 70 nm.
Next, an IPD film 110 is formed over the entire surface of the semiconductor substrate 101. The IPD film 110 is formed to conformally cover the inside of the space 154. A SiN—SiO—SiN—SiO (NONO) film having a thickness of 11 nm may be used as the IPD film 110. Further, a conductive film 112 functioning as the control gate electrode film 111M is formed over the entire surface of the semiconductor substrate 101. Here, the conductive film 112 is formed to be filled in the trench 152 and the space 154 formed in the trench 152. For example, a P-doped polysilicon film having a thickness of 50 nm may be used as the conductive film 112. As a result, the conductive film 112 has a structure in which the electrode forming section 1112 is formed, in the space 154 between the floating gate electrode films 109, with the IPD film 110 interposed, and the electrode forming sections 1112 stacked in the Z direction are connected to each other by the common connecting section 1111 extending in the Z direction.
Thereafter, performed is a process of forming the selection gate electrode film-forming trench 155 and the drain region connection contact forming trench 156 illustrated in
In the fourth embodiment, after the spacer film 104 corresponding to the STI of the typical NAND flash type memory of floating gate type is formed, the tunnel dielectric film 108 and the conductive film 134 functioning as the floating gate electrode film 109 are formed on the channel semiconductor film 103. Next, a recess is formed around the end portion of the spacer film 104, the conductive film 135 is filled in the recess, and as a result the end portion of the floating gate electrode film 109 extends in the Y direction. As a result, since a surface area of the floating gate electrode film 109 is increased, effects capable of suppressing the length of the floating gate electrode film 109 and reducing a plane area of the memory cell MC can be obtained in addition to the effects of the first embodiments. Further, the structure according to the fourth embodiment is appropriate for memory cells of a relatively small number of stacked layers.
Thereafter, when the IPD film 110 and the control gate electrode film 111M are formed in the control gate electrode film-forming trench 159, the control gate electrode film 111M is formed, on the side surface of the channel semiconductor film 103, through the IPD film 110 since the tunnel dielectric film 108 is removed from the side surface of the control gate electrode film-forming trench 159 in the negative Y direction as illustrated in
When the control gate electrode film 111M is close to the channel semiconductor film 103 as described above, there occurs a problem in that a tunneling current flows from a channel directly to the control gate electrode film 111M. That is, in the forming method described in the second embodiment, there may occurs a situation in which the IPD film 110 only exists between the channel semiconductor film 103 and the control gate electrode film 111M due to a processing fluctuation. In this case, a leakage current from the channel semiconductor film 103 to the control gate electrode film 111M may occur. In addition, on the side surface of the control gate electrode film-forming trench 159 in the positive Y direction, the floating gate electrode film 109 may not be divided for each memory cell MC as illustrated in
In this regard, the fifth embodiment will be described in connection with a method of manufacturing a non-volatile semiconductor memory device capable of preventing the above problem from occurring in the non-volatile semiconductor memory device having the structure according to the second embodiment illustrated in
First, as illustrated in
Thereafter, a plurality of layers in which a floating gate electrode film 109 and a spacer film 104 are alternately stacked are formed on the ILD film 102. Here, 6 layers each of which includes a floating gate electrode film 109 and a spacer film 104 are stacked. For example, a P-doped amorphous silicon film having a thickness of 30 nm may be used as the floating gate electrode film 109, and a silicon oxide film having a thickness of 25 nm may be used as the spacer film 104. Further, a hard mask film 105 is formed on the spacer film 104 of the top layer. For example, a silicon nitride film having a thickness of 50 nm may be used as the hard mask film 105.
Then, by collectively processing the stacked films, which includes the hard mask film 105, the spacer film 104, and the floating gate electrode film 109, using a lithography technique and an RIE technique, a trench 161, which isolates the floating gate electrode film 109 between the memory cells MC adjacent to each other in the Y direction, is formed to exposes part of the ILD film 102. The trench 161 has a shape extending in the X direction, but is not formed in an area in which a selection gate electrode film is to be formed. That is, the trench 161 is provided, between selection gate electrode film-forming regions adjacent to each other in the X direction, at a predetermined pitch in the Y direction. The pitch in the Y direction is set to a dimension of the NAND string group NSG faced by the memory cell MC in the Y direction in
Thereafter, the gap-fill dielectric film 131 is formed in the trench 161, and the top surface of the gap-fill dielectric film 131 is planarized using a CMP technique until the hard mask film 105 is exposed in an area other the forming position of the trench 161. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 131.
Next, as illustrated in
Next, an IPD film 110 is formed over the entire surface of the semiconductor substrate 101. The IPD film 110 is formed to conformally cover the inside of the control gate electrode film-forming trench 159. For example, a hafnia film having a thickness of 11 nm may be used as the IPD film 110.
Then, a conductive film 112 functioning as part of the control gate electrode film is filled in the control gate electrode film-forming trench 159. For example, a P-doped amorphous silicon film having a thickness of 30 nm may be used as the conductive film 112. Thereafter, a portion of the conductive film 112 and a portion of the IPD film 110, which are formed in a region other than the control gate electrode film-forming trench 159, are removed using a CMP technique.
Then, a hard mask film 136 for processing the channel semiconductor film 103 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 150 nm may be used as the hard mask film 136.
Thereafter, as illustrated in
Thereafter, as illustrated in
Next, a tunnel dielectric film 108 is formed on a side surface of the floating gate electrode film 109 inside the space 162. For example, a silicon oxide film having a thickness of 7 nm formed by an atomic layer deposition (ALD) technique may be used as the tunnel dielectric film 108.
Then, a channel semiconductor film 103 is formed over the entire surface of the semiconductor substrate 101. For example, an amorphous silicon film having a thickness of 10 nm may be used as the channel semiconductor film 103. Thereafter, the channel semiconductor film 103 is etched by a dry etching technique so as to have a recess, and hence the channel semiconductor film 103 remains only in the space 162 formed by etching the floating gate electrode film 109 to have a recess. For example, chlorine gas may be used as etching gas.
As described above, after the IPD film 110 and the conductive film 112 functioning as the control gate electrode film are formed to be filled in the control gate electrode film-forming trench 159, the trench 151 is formed at a position close to the end portion of the conductive film 112 in the Y direction, and the tunnel dielectric film 108 and the channel semiconductor film 103 are formed in the space 162 formed by forming a recess in the floating gate electrode film 109. Thus, provided is a structure in which the tunnel dielectric film 108 and the IPD film 110 remain between the control gate electrode film (the conductive film 112) and the channel semiconductor film 103. Further, after the tunnel dielectric film 108 is formed in the space 162, the channel semiconductor film 103 is formed. Thus, the width of the floating gate electrode film 109 is wider than the width of the channel semiconductor film 103.
Thereafter, the gap-fill dielectric film 106 is formed to be filled in the trench 151, and a planarization process is performed by a CMP technique until the mask film 136 is exposed in a region other than the forming position of the trench 151. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 106.
Next, as illustrated in
Thereafter, a conductive film 113 is formed to be filled in the selection gate electrode film-forming trench 155 and the inside of the drain region connection contact forming trench 156. Then, a planarization process is performed using a CMP technique so that the conductive film 113 remains only in the selection gate electrode film forming trench 155 and the drain region connection contact forming trench 156. For example, a P-doped amorphous silicon film having a thickness of 80 nm may be used as the conductive film 113. As a result, in the forming region of the selection transistor ST, made is a common connection between the floating gate electrode films 109 of the memory cells MC facing each other through the gap-fill dielectric film 131 therebetween. The drain region connection contact 113D is formed in the drain region connection contact forming trench 156.
Next, as illustrated in
Thereafter, conductive films 139 and 140 and a hard mask film 141 are formed over the entire surface of the semiconductor substrate 101. For example, a P-doped amorphous silicon film having a thickness of 50 nm formed by a CVD technique may be used as the conductive film 139, and a TaN/W stacked film having a thickness 50 nm may be used as the conductive film 140. Further, a silicon nitride film having a thickness of 80 nm may be used as the hard mask film 141. The conductive film 139 is formed to be filled in the contact hole 163 and functions a contact plug 138.
Next, by processing the hard mask film 141 and the conductive films 139 and 140 using a lithography technique and an RIE technique, a control gate electrode pattern 142 having a predetermined half pitch is formed on a region in which the contact plug 138 is formed. Here, formed is the control gate electrode pattern 142 having a half pitch of 30 nm in the X direction. The control gate electrode film 111M is configured with the conductive film 112, the contact plug 138, the conductive films 139, and 140. The selection gate electrode film 1115 is configured with the floating gate electrode film 109, the conductive film 113, the contact plug 138, and the conductive films 139 and 140.
Next, as illustrated in
Then, an ILD film is formed, and thereafter a contact plug and a wiring are formed. However, the contact plug and the wiring may be formed using a known technique, and thus a detailed description thereof will be omitted. Through the above process, the non-volatile semiconductor memory device according to the fifth embodiment is obtained.
In the fifth embodiment, the floating gate electrode film 109 into which a dopant is doped at a high concentration is initially stacked via the spacer film 104, and then the control gate electrode film-forming trench 159 is formed and filled with the IPD film 110 and the control gate electrode film 111M. Thereafter, the trench 151 is formed at the position close to the end portion of the IPD film 110 in the Y direction, and the space 162 formed by forming a recess in the floating gate electrode film 109 is filled with the tunnel dielectric film 108 and the channel semiconductor film 103. As a result, the IPD film 110 and the tunnel dielectric film 108 can be formed between the channel semiconductor film 103 and the control gate electrode film 111M. Accordingly, there are effects capable of avoiding a situation in which only the IPD film 110 is present between the control gate electrode film 111M and the channel semiconductor film 103 and preventing a leak from the channel semiconductor film 103 to the control gate electrode film 111M.
Further, since the width of the floating gate electrode film 109 is easily increased to be wider than the width the channel semiconductor film 103, there are effects capable of increasing controllability of a channel and easily attaining a higher coupling ratio.
In the manufacturing methods described in the first to fifth embodiments, the memory cell MC is a thin film transistor (TFT) formed on the channel semiconductor film 103 made of polysilicon (amorphous silicon is used when a film is formed, however, amorphous silicon is finally converted to polycrystalline silicon by crystallization). However, the TFT has disadvantages in that it is difficult to achieve high mobility due to influence of a grain boundary, and cell characteristics such as a threshold voltage distribution easily vary due to the influence of the grain boundary. In this regard, a sixth embodiment will be described in connection with a method of manufacturing a non-volatile semiconductor memory device having the channel semiconductor film 103 made of single crystal.
In the following, described is an example of manufacturing a non-volatile semiconductor memory device having a structure in which six layers, each including a channel semiconductor film 103 and a sacrificial film 146, are stacked at a pitch of 60 nm in parallel to a semiconductor substrate 101, a half pitch in the Y direction is 62 nm, and a half pitch in the X direction is 25 nm.
First, as illustrated in
Next, formed are a plurality of layers in which the sacrificial film 146 of single crystal and the channel semiconductor film 103 of single crystal are alternately stacked over the entire surface of the semiconductor substrate 101. Here, six layers of the sacrificial films 146 having the same thickness and five layers of the channel semiconductor films 103 having the same thickness are alternately formed. Thereafter, a channel semiconductor film 103b having a thickness larger than that of the channel semiconductor films 103 is formed on the sacrificial film 146 of the top layer. The sacrificial films 146 and the channel semiconductor films 103 and 103b of single crystal may be formed using a selective epitaxial growth technique or a blanket epitaxial growth technique. For example, a single crystalline SiGe film having a thickness of 20 nm may be used as the sacrificial film 146. For example, a single crystalline silicon film having a thickness of 40 nm may be used as the channel semiconductor film 103. For example, a single crystalline silicon film having a thickness of 50 nm may be used as the channel semiconductor film 103b.
Thereafter, the upper portion of the channel semiconductor film 103b of the top layer is oxidized to form a spacer film 147. For example, a silicon thermal oxide film having a thickness of 40 nm, formed by oxidizing the upper portion of the channel semiconductor film 103b by 20 nm, may be used as the spacer film 147.
Then, a hard mask film 105 is formed on the spacer film 147. For example, a silicon nitride film having a thickness of 50 nm may be used as the hard mask film 105. Further, the hard mask film 105 may be formed using a film made of SiCN, SiBN, alumina, titania, zirconia, or the like besides the silicon nitride film. Moreover, it is preferable that the hard mask film 105 can be easily etched to form a recess that acts as a mold of floating gates.
Next, as illustrated in
Thereafter, a gap-fill dielectric film 106 is formed in the trench 151. The upper surface of the gap-fill dielectric film 106 is planarized using a CMP technique, and so the hard mask film 105 is exposed in a region other than the position at which the trench 151 is formed. For example, a silicon oxide film formed by a CVD technique may be used as the gap-fill dielectric film 106. Then, a hard mask film 107 is formed over the entire surface of the semiconductor substrate 101. For example, a silicon nitride film having a thickness of 100 nm may be used as the hard mask film 107.
Next, as illustrated in
Thereafter, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, a tunnel dielectric film 108 is formed on a side surface of the channel semiconductor film 103 inside the space 153. For example, the tunnel dielectric film 108 may be formed using a technique such as a thermal oxidation technique, a thermal nitridation technique, or a plasma nitridation technique. Then, a floating gate electrode film 109 is formed over the entire surface of the semiconductor substrate 101. For example, a P-doped amorphous silicon film having a thickness of 15 nm may be used as the floating gate electrode film 109. Thereafter, the floating gate electrode film 109 is continuously etched to form a recess by a dry etching technique so that the floating gate electrode film 109 remains only in the space 153. For example, chlorine gas may be used as etching gas. As a result, formed is a structure in which the floating gate electrode film 109 is stacked above the single crystalline silicon via the tunnel dielectric film 108, similarly to the typical NAND flash type memory of the planar floating gate type structure.
Next, as illustrated in
Then, the hard mask films 107 and 105 are etched to form a recess starting from the end portion of the floating gate electrode film 109 by a predetermined amount by using an isotropic etching technique. For example, a wet etching technique using a hot phosphoric acid may be used as the isotropic etching technique. For example, the recess amount of the hard mask films 107 and 105 may be set to 50 nm.
Thereafter, an IPD film 110 is formed over the entire surface of the semiconductor substrate 101. The IPD film 110 is formed to conformally cover the inside of the space 154. A SiO—SiN—SiO (ONO) film having a thickness of 9 nm may be used as the IPD film 110.
Further, a conductive film 112 functioning as part of the control gate electrode film 111M is formed over the entire surface of the semiconductor substrate 101. Here, the conductive film 112 is formed to be filled in the trench 152 and the space 154 formed in the trench 152. For example, a P-doped polysilicon film having a thickness of 50 nm may be used as the conductive film 112. The conductive film 112 functions as part of the control gate electrode film 111M and part of the selection gate electrode film 111S, and has a structure in which the electrode forming section 1112 is formed in the space 154, and the electrode forming sections 1112 of the control gate electrode films 111M, which are stacked in the Z direction via the IPD film 110, are connected to each other, between the floating gate electrode films 109, by the common connecting section 1111 extending in the Z direction. As a result, formed is a structure in which the tunnel dielectric film 108, the floating gate electrode film 109, the IPD film 110, and the conductive film 112 (the control gate electrode film 111M) are stacked on the channel semiconductor film 103.
Thereafter, performed is a process of forming the selection gate electrode film-forming trench 155 and the drain region connection contact forming trench 156 illustrated in
In the sixth embodiment, formed are a plurality of layers in which the sacrificial films 146 of single crystal and the channel semiconductor films 103 and 103b of single crystal, which extend in the X direction in parallel to the substrate surface, are alternately stacked in the Z direction. The trench 152 extending in the X direction is formed. Thereafter, the oxide film 148 is formed by oxidizing the channel semiconductor films 103 and 103b so as to be filled in the space 164 formed by removing the sacrificial film 146. Next, the space 153 is formed by forming a recess in the channel semiconductor films 103 and 103b by a predetermined amount, and the tunnel dielectric film 108 is formed in the space 153. Thereafter, the space 153 is filled with the floating gate electrode film 109. Thereafter, the IPD film 110 and the control gate electrode film 111M are formed by forming a recess in the oxide film 148 by a predetermined amount. As a result, the channel semiconductor film 103 can be formed of a single crystalline semiconductor film having no grain boundary, and it is possible to form a non-volatile semiconductor memory device capable of high speed operation and suppressing a variation in a threshold voltage distribution. Further, since the channel semiconductor film 103 is stacked in parallel to the semiconductor substrate 101, there is an effect capable of performing single crystallization of the channel semiconductor film 103 using crystallization information of the semiconductor substrate 101.
The above description has been made in connection with the example of manufacturing the non-volatile semiconductor memory devices according to the first, third, and fourth embodiments. However, the above described manufacturing method can be similarly applied to the non-volatile semiconductor memory devices according to the second and fifth embodiment.
A seventh embodiment will be described in connection with a scaling scenario of the non-volatile semiconductor memory devices according to the above embodiments.
The non-volatile semiconductor memory device illustrated in
However, the non-volatile semiconductor memory device illustrated in
In the stacked volatile semiconductor memory devices according to the above embodiments, by increasing the number of stacked layers, the effective half pitch can be reduced. However, when the number of stacked layers is increased, the staked film thickness of the memory cell MC increases, processing difficulty increases, and the lead-out portion 180 of each channel semiconductor film 103 staked as described in the first embodiment increases in size. In this regard, in a stage in which the number of stacked layers is not so many, it is desirable to employ the structure in which the IPD film 110 is formed on the three surfaces of the floating gate electrode film 109, which is illustrated in
Meanwhile, in a stage in which the number of stacked layers increases, it is desirable to employ the structure of using only one surface of the floating gate electrode film 109, which is illustrated in
It can be understood that when an MLC represented by the curved line S1 of
The above embodiments are examples, and the number of stacked layers of the non-volatile semiconductor memory device is not limited to the above examples. The number of stacked layers other than 4 layers or 6 layers may be used.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-102816 | May 2011 | JP | national |
