Patent Grant
RE50025
This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2007-239089, filed on Sep. 14, 2007, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device with a floating gate type memory cellof a floating gate type, and specifically relates to a method of controlling read/write of a NAND-type flash memory.
2. Description of the Related Art
A currently manufactured NAND-type flash memory has floating gate type of memory cells, wherein write and erase of whichoperations are performed with electron-injection and electron-releasing ofat the respective floating gates (FGs). ControllingBy controlling the electron injection quantity in a floating gate, it is ablepossible to set multiple threshold voltage states (i.e., data states). In practice, it has been achieved such a NAND-type flash memory that stores four level data (i.e., stores two bits per cell).
What becomes problematic whenProblems occur as the NAND-type flash memory is more highly integrated and stores more data bits per cellis; creating an interference noise between floating gates. This interference effect is defined as follows: assuming that a memory cell Cell_A is written, and then adjacent memory cell Cell_B is written, FG potential of Cell_A is influenced by the change of FG potential of Cell_Bto be changed, so that the threshold distribution appears to be widened.
There has been proposed a write control scheme preferable for makinglessening the interference between memory cells less (refer to, for example, JP-A-2005-243205). In this write control scheme, it is not used such an upper page write mode that brings straightincreases the lowermost level of four levels to the uppermost level is not used. As a result, the interference noise between cells will be reduced. Additionally, in the write control scheme, word lines are basically selected in order from the source line side, and word line selecting orders of the lower page write and the upper page write are suitably combined so as to reduce the influenceinterference between cells.
However, as the highlyhigher integration of the NAND-type flash memories progresses, there is possibility that it becomes more difficult to avoid the interference noise between adjacent cells.
According to an aspect of the present invention, there is provided a method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, includingincludes a read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed incompleting data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell in the read procedure.
According to another aspect of the present invention, there is provided a method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, includingincludes a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and a normal read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell; a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously toas the selected memory cell; and a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells; the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously toas the selected memory cell; and a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the level of the fourth read pass voltage being selected in level in accordance with the cell's threshold shift amount.
According to still another aspect of the present invention, there is provided a method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, includingincludes a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and a normal read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the level of the third read voltage being selected in level in accordance with the cell's threshold shift amount, the maximum valevalue of which is higher than the first read pass voltage.
Illustrative embodiments of this invention will be explained with reference to the accompanying drawings below.
Basic Configuration and Basic Write-control Scheme
One end of NAND cell unit 100 is coupled to bit line BL via the select gate transistor SG1; and the other end is coupled to common source line CELSRC via the select gate transistor SG2.
One memory cell has N-type source and drain diffusion layers formed on a P-well formed on a silicon substrate, and a stacked gate structure with a floating gate and a control gate stacked above the channel region defined by the source and drain layers. ChangingBy changing the charge amount held in the floating gate by a write or erase operation, the threshold voltage of the cell is changed, so that one bit per cell or multiple bits per cell will be stored.
Control gates of the memory cells MC0-MC31 in the NAND cell unit 100 are coupled to different word lines WL0-WL31, respectively; and gates of the select gate transistors SG1 and SG2are coupled to select gate lines SGD and SGS, respectively.
A set of NAND cell units 100, which shares word lines WL0-WL31 and select gate lines SGD and SGS, constitutes a block 101 serving as a data erase unit. Usually, as shown in the drawing, plural blocks are arranged in the bit line direction.
The various operations of the NAND-type flash memory are achieved together with command inputs. For example, in a write mode, data load command is input via input/output circuit 1 to be latched in command register 2; then write destination address is input via input/output circuit (I/O buffer) 1 to be latched in address register 3; write data is input via input/output circuit 1 to be loaded in sense amplifier circuit (serving as write circuit) 30; and write executing command is input via input/output circuit 1 to be latched in command register 2. As a result, the write operation will start automatically in the chip.
That is, by the write executing command being input, sequence control circuit 4 starts to execute. This sequence control circuit 4 executes the following controls: voltage controlling necessary for data writing; timing controlling of write pulse applications and verify-reading operations; and repeat-controlling of the write pulse applications and verify-read operations until a desirable write operation is completed.
High voltage generation circuit 5 generates under the condition of the sequence control circuit 4 write voltage Vpgm, write pass voltage Vpass, read pass voltage Vread and other high voltages (boosted voltages) necessary for row-signal driving circuit 20, page buffer control circuit 6 and the like.
Row-signal driving circuit 20 has: CG decoder/drivers 24, the number of which is equal to that of word lines in a NAND cell unit; SGD driver 22 for controlling the drain side select gate line SGD; SGS driver 23 for controlling the source side select gate line SGS; and VRDEC driver 21 for outputting boosted supply voltage VRDEC used in the block decoder. These drivers 21-24 are shared by plural blocks 101 in the memory cell array 102.
It is required offor the NAND-type flash memory to be useduse plural voltages applied to plural word lines in a selected NAND cell unit. Therefore, page addresses used for selecting word lines in the NAND cell unit in the row address will be input to the respective CG decoder/drivers 24.
Disposed at the word line end of each block in the memory cell array 102 is a narrow sensed row decoder 10, which has a block selecting function. Row decoder 10 has block decoder 11 for receiving the block address sent from address register 3 and decoding it, and transferring transistor array 12, the common gate of which is driven by the outputs of block decoder 11, for transferring voltages necessary for write, erase and read to the word lines and the select gate lines. Block decoder 11 includes a level shift circuit for outputting a required voltage to the common gate TG of the transistor array 12.
OneFirst ends of the transfer transistor array 12 are coupled to the respective drivers 21-24 while the other second ends are coupled to word lines and select gate lines in the memory cell array 102. For example, at a write pulse application time, it is in need of applying a write voltage Vpgm (about 20V) is needed to be applied to a selected word line. At this time, applied to the common gate TG is Vpgm+Vt (Vt; threshold voltage of the transfer transistor 12), which is supplied from VRDEC driver 21.
In the NAND-type flash memory, FN tunneling current is used for writing and erasing cells. Specifically in the writing mode, a lot of memory cells may be written simultaneously because a necessary current for shifting cell's threshold is very smallas different, which differs from a NOR-type flash memory. Therefore, a page length, which is defined as a collectively processing unit in a write mode or read mode, will be set to be as large as 2 kByte or 4 kByte. Sense amplifier circuit (i.e., page buffer) 30 includes sense amps 31 with the same number as the page length.
Column decoder 7 decodes, for example at a write data loading time, column address sent from address register 3, and couples the input/output circuit 1 to selected sense amps PB, thereby makingcausing write data for the respective column addresses to be loaded in the sense amplifier circuit 30. In a read mode, read data stored in a lump in the sense amplifier circuit 30 are output to input/output circuit 1 as sequentially selected in accordance with a column address.
In case of this sense amplifier scheme, memory cells selected by a word line and all even-numbered bit lines constitute a page (even page) to be read or written simultaneously while memory cells selected by a word line and all odd-numbered bit lines constitute another page (odd page) to be read or written simultaneously.
Another latch circuit L2 is coupled to the sense node TDC via transfer transistor 33, and coupled to operational circuit 34 via transfer transistor 34a. The operational circuit 34 including transistors 34a, 34b and 34c may execute some operations for the sense node TDC in accordance with the potential of gate node DDC of transistor 34b. For example, setting drain voltage VPRE of transistor 34b at 0V when DDC is “H”, and turning on transistor 34c, the potential of node TDC will be changed in accordance with data at DDC.
Transistor 35 is a bit line precharging transistor. Transistor 37 is one used for coupling a bit line to the sense node TDC. This transistor 37 serves for amplifying a small bit line amplitude in accordance with gate voltage control thereof at a read time, and serves for coupling the latch circuit to the bit line at a write time.
Transistors 38a and 38b are high breakdown voltage onestransistors, which serve for not only shuttinggenerating an erase voltage of about 20V to be applied to bit lines but also selecting the even and odd bit lines BLe and BLo.
In the lower page (LP) write (or program), cells of level “E” are selectively set up to have a medium level “LM”, that is set between levels “A” and “B”. After the LP write, the upper page (UP) write is performed. In the upper page write, level “A” write from level “E” and level “B” or “C” write from level “LM” are performed simultaneously.
The lower limit values of the threshold voltages of levels “LM”, “A”, “B” and “C” are defined by verifying voltages VLv, Vav, Vbv and Vcv, respectively, used at the respective write-verify times.
The basic data write order (word line selection order) in this embodiment is shown in
That is, assuming that cells in the NAND string are written in order from the source line side, first, the lower page, L:{circle around (1)}, of word line WL0 on the even numbered bit line BLe side is written; then, the lower page, L:{circle around (2)}, of word line WL0 on the odd numbered bit line BLo side is written. Following itthat, the lower page, L:{circle around (3)}, of word line WL1 on the even numbered bit line BLe side is written; and then, the lower page, L:{circle around (4)}, of word line WL0 on the odd numbered bit line BLo side is written. Next, the upper page, U:{circle around (5)}, of word line WL0 on the even numbered bit line BLe side is written; and then, the upper page, L:{circle around (6)}, of word line WL0 on the odd numbered bit line BLo side is written.
Successively, gogoing to word line WL2, and the lower page, L:{circle around (7)}, on the even numbered bit line BLe side is written; and then, the lower page, L:{circle around (8)}, of word line WL2 on the odd numbered bit line BLo side is written. Following itthat, gogoing back to word line WL1, and the upper page, U:{circle around (9)}, on BLe is written; and then the upper page, U:{circle around (10)}, of the word line WL1 on the odd bit line BLo side is written. Hereinafter, the same write operation will be repeated.
DataWith data writing in accordance with the above-described order, it becomes possible to prevent the adjacent cell from being written into C level from E level after having decided a noticed cell's threshold at either one of A to C levels. The threshold change of the adjacent cell of the noticed cell after writing it will be suppressed to be about a half (i.e., E→A, LM→C) in comparison with the change from E level to C level, and resulting in that the interference effect of cells is reduced in half.
Subject to be Solved
Although the basic configuration and basic write control scheme have been explained above, there are remained problems remain to be solved, which will be explained in detail below.
When memory cell MC2 is selected, the selected word line WL2 is applied with select voltage Vsel while unselected word lines WL0-1 and WL3-7 (i.e., unselected memory cells) are applied with read pass voltage Vread that is necessary to turn on cells without regard to cell data. The select voltage Vsel is either one selected from verify voltages VLv, Vav, Vbv and Vcv, which are selected in accordance with write levels, at a write-verify time, or either one selected from read voltages Var, Vbr and Vcr set between the respective data levels at a normal read time.
Notice here the C level of the memory cell on the word line WLn−1, which has already been written. The cell threshold distribution becomes “b1” shown by a solid line when there is not influenced by theno influence of interference between floating gates, while it becomes “b2” shown by a dotted line when there is influenced by itinfluence of interference. With respect to word line WLn+1, distribution “c1” shown by a solid line is obtained without the interference while distribution “c2” shown by a dotted line is obtained with the interference.
Note here that unselected word lines WLn−1 and WLn+1 disposed adjacent to the selected word line WLn are different in condition from the remaining unselected word lines with respect to the interference effect between adjacent cells. That is, each of the remaining word lines and the selected word lines is sandwiched by word lines with Vread applied. By contrast, with respect to word lines WLn−1 and WLn+1, one of word lines adjacent to them areis set at Vread while the other areis set at Vav.
As a result, the memory cells on the unselected word lines WLn−1 and WLn+1, one of the two adjacent word lines of each of which is low in potential, have an apparently higher threshold state than those on the remaining unselected word lines because of a large interference of adjacent cells. This will be explained with reference to
On the other hand, as the cell size is shrunk, the floating gate FGn of the noticed cell is strongly coupled to adjacent floating gates and adjacent word lines with capacitances C3 and C4, respectively.
Under the capacitive coupling situations, when word line WLn+1 is applied with the read pass voltage Vread and word line WLn is applied with a read voltage lower than the read pass voltage, the floating gate FGn+1 under the word line WLn+1 becomes lower in potential than the case where FGn+1 is directly controlled by the word line WLn+1 with Vread applied. The reason is as follows: a first capacitive coupling effect, in which the potential of FGn+1 is reduced from word line WLn via the floating gate FGn+1 (i.e., via capacitance C2 and C3), and a second capacitive coupling effect, in which the potential of FGn+1 is reduced from word line WLn directly, are overlapped, so that the floating gate FGn+1 is not sufficiently increased in potential with Vread.
Explaining that in other words, the memory cell under aan unselected word line adjacent to the selected word line becomes apparently high in threshold. As shown in
As a result, as shown in
Next,
It will be guessed thatHere we consider the C-level cell under the word line WLn−1 becomes to have distribution “b3” shown by dash line as similar to that in the case shown in
The threshold voltage change of the A level cell under the selected word line WLn will be explained as follows: in reception of the resultthe case that distributions “c1” to “c3” of LM levels of cells under the word line WLn+1 shown in
The effect of expanding the post-write data threshold distributions due to the on-margins of unselected cells against the read pass voltage is referred to as a “back pattern noise”. In general, in such a cell that is easily written in a NAND string, the back pattern noise appears large. That is, the nearer to the cell source line, the larger the back pattern noise appears. However, when the interference between cells becomes large due to the cell miniaturization, it becomes difficult to ignore the interference even if it is due to one cell, and the interference influence appears as a result of the reduction of on-margin.
The above-described influence on the threshold voltage of the adjacent cell due to the selected word line will be explained together with a detailed numerous exampleexamples with reference to the coupling capacitances shown in
ΔVt={(C4+C3·Cr/C2}ΔVwl [Exp. 1]
where, Cr=C2/Call (Call is the total capacitance value of FGn).
By use of the following numerous example of: (C4+C3·Cr)/C2=0.066; and ΔVwl=4.5v (Vread=5.5V, Vsel=1V) as used in the conventional NAND-type flash memory, ΔVt=0.3V is obtained. In other words, the difference between threshold distributions “c2” and “c3” in
Next, by use of the following numerous example of: (C4+C3·Cr)/C2=0.13; and ΔVwl=4.5v as obtained in case the interference between cells becomes large due to the cell miniaturization, ΔAVt=0.59V is obtained. In other words, the difference between threshold distributions “c2” and “c3” in
Conventionally, the read pass voltage Vread is set at about 5.5V, and the upper limit of the distribution “c2” is set at about 4V. In the NAND-type flash memory belonging to a generation, in which the design rule is larger than 56 nm, the difference between the distributions “c2” and “c3” is about 0.3V, so that the back pattern noise due to the unselected cells adjacent to the selected cell is not problematic. However, in such a generation that the design rule is 56 nm or less, as explained in the calculation example, the difference between distributions “c2” and “c3”, i.e., the threshold voltage difference, becomes about 0.6V. As a result, when estimating the device with the same read pass voltage and the upper limit of the threshold voltage, the back pattern noise becomes more apparent remarkably.
The condition of that the above-described effect starts to be apparent as the back pattern noise is inresults from the fact that the difference between the read pass voltage and the upper limit of the distribution “c3”, i.e., on-margin dVon_3a of the unselected cell as shown in
First R/W Scheme in the Embodiment
As shown in these
Vread2 is an adjusted voltage such as to be able tothat can cancel the apparent threshold increase of the unselected cell under the adjacent and unselected word line WLn+1 due to the read voltage of the selected word line WLn. If Vread2−Vread is too large, in aan unselected word line, the both adjacent word lines of which are applied with Vread, the on-margin against Vread is reduced, and resulting in that the back pattern noise due to word lines WLn+2˜WLm becomes large. Therefore, it is desired to set Vread2 at such a level that is able to suppress the influence in the memory cells under word line WLn+1.
Applied to the adjacent and unselected word line WLn+1 on the bit line side of the selected word line WLn is a pass voltage Vread2 higher than Vread applied to the remaining unselected word lines. As a result, the increase of the back pattern noise due to the selected word line voltage will be suppressed.
The operation will be explained below in accordance with the sense unit configuration shown in
For example, when even numbered bit lines BLe are subjected to data read, these are set at “H”, and Vpre+Vt is applied to BLCLAMP, so that the even numbered bit lines, BLe, are precharged. Odd numbered bit lines, BLo, are set as Vss, and serve as shield lines.
After the word lines and bit lines have been set at certain levels, respectively, stop the bit line precharge operation is stopped at timing r1, and raise simultaneously the select gate line SGS on the source line side is raised to turn on the select gate transistor SG2, thereby discharging the bit lines in accordance with data of selected cells. If the threshold voltage of a selected cell is lower than the select voltage (i.e., data “1”), the bit line is discharged while if not so (i.e., data “0”), the bit line is not discharged.
Prior to data sensing, sense node TDC is precharged at timing r2. Then, clamping transistor is turned on at timing r3, thereby coupling the bit line to the sense node TDC. Assuming that the sense level is Vsen set between “0” and “1”, BLCLAMP is applied with Vsen+Vt, which is able tocan turn on transistor 37 when bit line level is Vsen. Since bit line capacitance is sufficiently larger than the capacitance of the sense node TDC, the bit line potential change with a small amplitude will be amplified at the sense node TDC.
Although, after timing r4, the write-verify operation and the normal read operation hashave a slight difference, data at the sense node after sensing, or data after certain operational processing at the sense node TDC, is stored in latch L1. Finally, after discharging word lines and bit lines at timing r5, the write-verify operation or the normal read operation ends.
IntroducingBy introducing the above-described read pass voltage Vread2, the on-resistance increase of the cell under the unselected word line WLn+1 is suppressed, and the threshold voltage shift of the selected cell under the selected word line is suppressed. Explaining that in detail, as explained with reference to
By contrast, according to this embodiment, as shown in
Second R/W Scheme in the Embodiment
This second R/W scheme is different from the first R/W scheme in the following fact: in this second R/W scheme, as shown in
Vread2 is an adjusted voltage such as to be able tothat can cancel the apparent threshold increase of the unselected cell under the adjacent and unselected word lines WLn+1 and WLn−1 due to the read voltage of the selected word line WLn. If Vread2−Vread is too large, in aan unselected word line, the both adjacent word lines of which are applied with Vread, the on-margin against Vread is reduced, and resulting in that the back pattern noise due to word lines WLn+2˜WLm becomesbecoming large. Therefore, it is desired to set Vread2 at such a level that is able to suppress the influenceinterference in the memory cells under word line WLn+1.
According to this second R/W scheme, in addition to the effect obtained in the first R/W scheme, it will be provided the following effect that theof reduction of cell current Icell of the whole NAND string due to the reduction of on-margin of the cell under the word line WLn−1 is suppressed is realized.
Third R/W Scheme in the Embodiment
Note here that
As differentDifferently from the second R/W scheme, applied to the adjacent and unselected word line WLn+1 on the bit line side is read pass voltage Vread3 lower than Vread applied to the remaining word lines. As similarSimilarly to the second R/W scheme, applied to the adjacent and unselected word line WLn−1 on the source line side is read pass voltage Vread2 higher than Vread applied to the remaining word lines.
The cell under the adjacent and unselected word line WLn+1 on the bit line side is set inat LM level at this stage, so that it may be obtained a sufficiently low on-resistance with Vread3 lower than Vread can be obtained. Therefore, it is permitted to use such the pass voltage Vread3. TheWith the adjacent and unselected word line WNn−1 on the source line side being applied with Vread2, it becomes possible to secure a large on-margin dVon_1c in case of C-level cell.
By contrast, in the normal read operation for the selected word line WLn after having written all cells, the adjacent and unselected word line WLn+1 on the bit line side is applied with such a read pass voltage that is changed in accordance with cell data as follows.
That is, in case the cell data of word line WLn+1 is A- or C-level, as shown in
In case the cell data of word line WLn+1 is E- or B-level with a small threshold shift amount, as shown in
To makeestablish the read condition for the selected word line after all data have been written different in accordance with the write data in the adjacent and unselected word line WLn+1, it is required to refer to the data of the word line WLn+1 when word line WLn is selected. For this purpose, perform data read of word line WLn+1 is performed prior to data read of word line WLn, and store the data is stored in the sense amplifier/data latch. For example, cell data of word line WLn+1 is A- or C-level, reference data “0” is latched while cell data is E- or B-level, reference data “1” is latched.
Data read for the word line WLn is performed with two cycles with conditions shown in
The correcting read operation in this embodiment in accordance with the adjacent cell's data will be explained in detail with reference to
“cell1” is a memory cell to be read as an on-cell, which is not influenced by the interference between cells. “cell2” is a memory cell, the threshold voltage of which is shifted due to the interference between cells, and it is corrected in the read operation to be read as an on-cell (cell on the lower side). “cell3” is a memory cell, thewith a threshold voltage of which is higher than those of “cell1” and “cell2”.
In the write-verify operation, the selected voltage Vsel applied to the selected word line WLn is the verifying voltage while pass voltage Vread3 (<Vread) is applied to the unselected word line WLn+1.
In this embodiment, prior to starting the read operation for the selected word line WLn, data of the unselected word line WLn+1 is read and stored. This operation is performed automatically by the controller when word line WLn is selected in the read operation. In this read operation of the unselected word line WLn+1, in case E-level or B-level is judged, “H” is set at node PDC while A-level or C-level is judged, “L” is set at the node PDC. TheAs the sense unit has a certain number of data nodes and an arithmetic processing function, the above-described data read may be easily performed. The detailed explanation is omitted.
Next, the read operation for the selected word line WLn will be explained as follows: in the lower page read operation, as shown in
In the case of threshold distributions and data bit assignment shown in
In case the adjacent cell's data on the word line WLn+1 is E- or B-level, the interference from the adjacent cell to the selected cell is small, the threshold voltage of the selected cell on the word line WLn is hardly changed from the write-verified state. Therefore, in case the adjacent cell is in this state, data will be obtained in the read operation Read1 with the pass voltage of word line WLn+1 set at Vread3, that is the same as one at the write-verify time.
By contrast, in case the adjacent cell's data on the word line WLn+1 is A- or C-level, the threshold voltage of the selected cell appears to be increased due to the interference between floating gates FG. Therefore, in the read operation Read2, the pass voltage of the word line WLn+1 is set at Vread2 higher than Vread3, so that the interference effect will be cancelled.
It has already been provided theThe idea for canceling the interference effect of the floating gate type of memory cells with selection of the read condition of the selected cell has been raised (e.g., refer to U.S. Pat. No. 5,867,429, or JP-A-2004-32866). However, this idea is for adjusting the read condition of the selected cell itself influenced by the interference effect between floating gates, and the variations of the interference effects within the memory cells are not considered.
By contrast, in this embodiment, the read pass voltage applied to the adjacent and unselected word line WLn+1 is selected in accordance with the data written state in the unselected cell, thereby canceling the interference between cells. The operation principle will be explained in detail below.
The interference effect between cells described here is defined as follows: when writing an adjacent cell after writing a noticedselected noted cell, FG potential of the adjacent cell is reduced to be lower than that of the selected cell, thereby resulting in that FG potential of the noticedselected cell also is reduced due to capacitive coupling, and the threshold voltage of the noticedselected cell appears to be high. This is an interference effect obtained via the coupling capacitance C3 shown in
Therefore, in case the adjacent cell is written, it is desired to restore the FG potential of the adjacent cell in accordance with the written level into the same state as that obtained when the noticedselected cell is written. However, when the adjacent word line is changed in potential to achieve this, such interference will be obtained that the noticedselected cell is directly influenced from the adjacent word line via coupling capacitance C4 shown in
In this embodiment, in consideration of the both of an interference function based on the serial-connected capacitance, C2+C3, of the adjacent cells and another interference function based on the coupling capacitance C4, the read operation is corrected. As a result, it becomes possible to strongly reduce the variations. This point will be explained in detail below.
When the adjacent and unselected word line WLn+1 is changed in potential by ΔVwl, the threshold voltage change ΔVt is obtained as expressed in the following expression Exp. 2 obtained by transforming the above-described Exp. 1.
ΔVwl={C2/(C4+C3·Cr)}ΔVt [Exp. 2]
In Exp. 2, ΔVt is the threshold voltage change amount due to the interference effect. Rewriting it into another threshold shift amount ΔVt_swing due to data writing in the adjacent and unselected cell, the following Exp. 3 is obtained.
ΔVwl={C2/(C4+C3·Cr)}ΔVt_swing [Exp. 3]
A detailed numerous example is as follows. Assuming that the coefficient of AVt_swing is defined as: C3·Cr/(C4+C3·Cr)=0.41; and assuming that ΔVt_swing is about 3V as defined by the cell data change from E-level to A-level, ΔVwl=1.24V is obtained.
As explained above, by increasing the potential of word line WLn+1 by 1.24V, it becomes possible to cancel the interference effect due to the threshold shift amount, 3V, of the adjacent cell.
Further, to make the influence of the back pattern noise on the word line WLn+1 due to the selected word line WLn, as explained with reference to
A setting example of pass voltage Vread2 is as follows. Since, as shown in the calculation example, the threshold voltage of the adjacent cell appears to be shifted with an order of 0.3V or 0.6V, keeping constant the difference between Vread2 and Vread3, Vread2 should be set at a voltage higher than Vread by 0.3V or 0.6V.
At Step1, prior to the read operation of the selected word line WLn, data read for correcting data is performed for word line WLn+1, and read data is latched at node PDC. At Step2, Read1 shown in
At Step3, data at node PDC is transferred to node DDC, and the product of data at TDC by inverted data at DDC is obtained. This is achieved in the operation circuit 34 in the sense amplifier shown in
That is, if DDC=“H”, TDC is discharged to be “L”. If DDC=“1”, TDC is not discharged, and keeps the last data level as it is. This operation result is transferred to and held at node PDC.
At Step4, this beingwhich is a read step, Read2, shown in
Therefore, the threshold of “cell2” in Read1 and that of “cell1” in Read2 become substantially equal to each other. Latched data of (cell1, cell2, cell3) at node TDC are (L, L, H).
Next, at Step5, data previously latched at node PDC is transferred to node DDC, and an addition operation of data at node TDC and data at node DDC is performed at node TDC. Explaining that in detail, in the operation circuit 34 in
As a result, if DDC=“H”, TDC is forced to be “H” due to a bootstrap operation. If DDC=“L”, the last TDC data will be kept as it is. The operation result at TDC is transferred to node PDC, and latched as the lower page data.
Therefore, according to this operation, in case “L” is initially stored at node PDC in the sense amplifier, finally latched data at the node PDC is read data in Read1, while in case “H” is initially stored at node PDC, read data in Read2 is finally latched at the node PDC.
As described above, data read with threshold correction may be performed for the respective bit lines, i.e., for the respective selected cells, which are coupled to a selected word line to be simultaneously read.
The sense amplifier configuration and the operational function are not limited to those shown in
As another embodying mode in this embodiment, it is possible to correct the interference effect between cells at multiple steps, i.e., two or more steps. This is, for example, achieved by disposing another operational circuit between node N1 (PDC) and TDC in the sense amplifier shown in
Fourth R/W Scheme in the Embodiment
So far, it has been explained such a case has been explained that the write order is selected to make the interference between adjacent cells as small as possible. By contrast, in case word lines are selected in order from the source line side, and the lower page write and the upper page write are completed for each selected word line, each cell's threshold will be shifted due to the interference between adjacent cells after writing.
However, in the above-described case, by precisely controlling the read pass voltage applied to the unselected word lines WLn+1 disposed adjacent to the selected word line WLn on the bit line side in accordance with cell data, the influence of the interference between cells will be reduced.
In detail, as similar to the third R/W scheme explained above, the read pass voltage of the adjacent and unselected word line at a write-verify time is set to be lower than the read pass voltage, Vread, applied to the remaining unselected word lines. After data writing for WLn+1, the read pass voltage applied to the unselected word line WLn+1 at a read time for the selected word line WLn is optimized in accordance with whichthe level isof cell data in E, A, B and C levels.
As a result, the influence of the interference between cells will be reduced.
In the third R/W scheme, the read pass voltage applied to the unselected word line WLn−1 is set to be Vread2, higher than Vread. According to the explanation for the first R/W scheme, it is not necessary to set the unselected word line WLn−1 at Vread2. Using Vread in place of Vread2, it will be expected the same operation and effect as described above can be realized.
In the above-described embodiment, the operation control example has been explained for a four-level data storage scheme (i.e., 2 bits/cell). However, this invention is in a method for controlling aan unselected word line disposed adjacent to a selected word line, and is not limited to the four-level storage scheme. That is, this invention may be adapted to other memory devices of a binary data storage scheme (1 bit/cell), an eight-level storage scheme (3 bits/cell) and other multi-level data storage schemes.
Application Devices
As an embodiment, an electric card using the non-volatile semiconductor memory devices according to the above-described embodiment of the present invention and an electric device using the card will be described bellowbelow.
The case of the digital still camera 1001 accommodates a card slot 1002 and a circuit board (not shown) connected to this card slot 1002. The memory card 61 is detachably inserted in the card slot 1002 of the digital still camera 1001. When inserted in the slot 1002, the memory card 61 is electrically connected to electric circuits of the circuit board.
If this electric card is a non-contact type IC card, it is electrically connected to the electric circuits on the circuit board by radio signals when inserted in or approached to the card slot 1002.
To monitor the image, the output signal from the camera processing circuit 1005 is input to a video signal processing circuit 1006 and converted into a video signal. The system of the video signal is, e.g., NTSC (National Television System Committee). The video signal is input to a display 1008 attached to the digital still camera 1001 via a display signal processing circuit 1007. The display 1008 is, e.g., a liquid crystal monitor.
The video signal is supplied to a video output terminal 1010 via a video driver 1009. An image picked up by the digital still camera 1001 can be output to an image apparatus such as a television set via the video output terminal 1010. This allows the pickup image to be displayed on an image apparatus other than the display 1008. A microcomputer 1011 controls the image pickup device 1004, analog amplifier (AMP), A/D converter (A/D), and camera signal processing circuit 1005.
To capture an image, an operator presses an operation button such as a shutter button 1012. In response to this, the microcomputer 1011 controls a memory controller 1013 to write the output signal from the camera signal processing circuit 1005 into a video memory 1014 as a flameframe image. The flameframe image written in the video memory 1014 is compressed on the basis of a predetermined compression format by a compressing/stretching circuit 1015. The compressed image is recorded, via a card interface 1016, on the memory card 61 inserted in the card slot.
To reproduce a recorded image, an image recorded on the memory card 61 is read out via the card interface 1016, stretcheddecompressed by the compressing/stretchingcompressing/decompressing circuit 1015, and written into the video memory 1014. The written image is input to the video signal processing circuit 1006 and displayed on the display 1008 or another image apparatus in the same manner as when image is monitored.
In this arrangement, mounted on the circuit board 1000 are the card slot 1002, image pickup device 1004, analog amplifier (AMP), A/D converter (A/D), camera signal processing circuit 1005, video signal processing circuit 1006, display signal processing circuit 1007, video driver 1009, microcomputer 1011, memory controller 1013, video memory 1014, compressing/stretching circuit 1015, and card interface 1016.
The card slot 1002 need not be mounted on the circuit board 1000, and can also be connected to the circuit board 1000 by a connector cable or the like.
A power circuit 1017 is also mounted on the circuit board 1000. The power circuit 1017 receives power from an external power source or battery and generates an internal power source voltage used inside the digital still camera 1001. For example, a DC-DC converter can be used as the power circuit 1017. The internal power source voltage is supplied to the respective circuits described above, and to a strobe 1018 and the display 1008.
As described above, the electric card according to this embodiment can be used in portable electric devices such as the digital still camera explained above. However, the electric card can also be used in various apparatus such as shown in
This invention is not limited to the above-described embodiments. It will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit, scope, and teaching of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-239089 | Sep 2007 | JP | national |
More than one reissue application has been filed for the reissue of U.S. Pat. No. 7,916,547. These applications are the present application, application Ser. No. 15/848,772 and application Ser. No. 13/852,792. The present application is a reissue continuation of application Ser. No. 15/848,772, filed Dec. 20, 2017, now RE48,244, which is a reissue continuation of application Ser. No. 13/852,792, filed Mar. 28, 2013, now RE46,749, which is a reissue of U.S. Pat. No. 7,916,547.
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| Number | Date | Country | |
|---|---|---|---|
| Parent | 15848772 | Dec 2017 | US |
| Child | 17004584 | US | |
| Parent | 13852792 | Mar 2013 | US |
| Child | 15848772 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12209486 | Sep 2008 | US |
| Child | 13852792 | US | |
| Parent | 12209486 | Sep 2008 | US |
| Child | 17004584 | US |
