Claims
- 1. A non-volatile semiconductor memory comprising:
a memory cell array having a plurality of electrically-rewritable non-volatile memory cells, provided with an initially-setting data area, written in which is initially-setting data for deciding memory operation requirements; a first decoder that selects memory cells in the memory cell array according to address signals; a sense-amplifier that detects and amplifies data stored in at least a memory cell selected by the first decoder; a latch circuit having a plurality of initially-setting data latches that latches the initially-setting data; and a controller that reads out the initially-setting data via the first decoder and the sense-amplifier and transfers the initially-setting data to the latch circuit.
Priority Claims (2)
Number |
Date |
Country |
Kind |
1999-351396 |
Dec 1999 |
JP |
|
2000-330971 |
Oct 2000 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of prior U.S. patent application Ser. No. 10/241,468, filed Sep. 12, 2002, which is a continuation of prior U.S. patent application Ser. No. 09/731,910, filed Dec. 8, 2000, which claims benefit of priority under 35 U.S.C. § 119 to Japanese Patent Application No. 1999-351396 filed on Dec. 10, 1999 in Japan and also Japanese Patent Application No 2000330971 filed on Oct. 30, 2000 in Japan, the entire contents of which are incorporated by reference herein.
Continuations (2)
|
Number |
Date |
Country |
Parent |
10241468 |
Sep 2002 |
US |
Child |
10703503 |
Nov 2003 |
US |
Parent |
09731910 |
Dec 2000 |
US |
Child |
10241468 |
Sep 2002 |
US |