This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2004-354943, filed on Dec. 8, 2004, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device. Among nonvolatile semiconductor memories, it especially relates to nonvolatile semiconductor memories of NAND cell type, NOR cell type, DINOR cell type and AND cell type EEPROM and others.
2. Description of Related Art
The EEPROM which can perform electric rewriting has been known as one of the semiconductor memory devices. Especially, the NAND cell type EEPROM which a plurality of memory cell are connected in series to constitute a NAND cell block attracts attention because higher integration is possible compared with other memories. A technology relating to data erasing of the NAND cell type EEPROM is described in Japanese Laid Open Patent Publication 2000-348492.
Here, referring to
As mentioned above, the data erasing operation is performed collectively by per block in the NAND cell type EEPROM. However, since the memory cells before erasing data are intermingled with data of “0” or “1” (whose threshold voltages are positive or negative), the threshold voltage distribution after erasing data will spread widely as is shown in
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, and before erasing data of all of said memory cells in the memory block selected from said plurality of memory blocks, threshold voltages of all of said memory cells in said selected memory block are shifted to be positive.
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, and said plurality of the memory blocks are constituted of the first domain and the second domain respectively, when data of a specific memory cell of said memory cells in said second domain of the memory block selected from said plurality of memory blocks is the first value, writing or erasing of the data to said selected memory block is permitted, when the data of said specific memory cell is the second value, writing or erasing of the data to said selected memory block is prohibited, when writing or erasing of the data to said memory block is permitted, before erasing the data of all of said memory cells in said selected memory blocks, all threshold voltages of all of said memory cells in said first domain in said selected memory block are shifted to be positive.
According to a semiconductor memory device of an aspect of the present invention, “0” data is written per block before the data erasing operation, and threshold voltage distribution of the memory cells in the selected block is shifted to be positive. Then, by performing the data erasing operation successively, threshold voltage distribution after the erasing operation can be narrower. Therefore, variation of time to complete writing of each memory cell at the time of writing the data performed successively after the data erasing operation can be smaller.
According to a semiconductor memory device of an aspect of the present invention, before the data erasing operation, “0” data is written in to the memory cells except for the area where identification flags and others are memorized, and while preventing incorrect erasing of the identification flag, threshold voltage distribution after the data erasing operation can be narrower, and variation of time to complete writing of each memory cell at the time of writing the data performed successively after the data erasing operation can be smaller. In addition, defect in writing the data can be restrained.
The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one or more embodiments of the present invention, together with the description, serve to explain the principals of the invention. The drawings are only for the purpose of illustrating one or more preferred embodiments of the invention and are not to be construed as limiting the invention. In the drawings:
In this embodiment, a NAND cell type nonvolatile semiconductor memory device is used as an example of a nonvolatile semiconductor memory device of the present invention.
A data writing operation and a data erasing operation of the NAND cell type EEPROM is as follows. The data writing operation is mainly performed in order from a memory cell in the position most distant from a bit line. Firstly, when the data writing operation is started, according to a writing data, 0V (“0” data writing) or a power supply voltage Vcc (“1” data writing) is given to a bit line, and Vcc is given to the select gate line at the selected bit line side. In this case, when the bit line is 0V, in the connected select NAND cell, a channel region in the NAND cell is fixed at 0V via a select gate transistor. When the bit line is Vcc, in the connected select NAND cell, the channel region in the NAND cell will be in a floating state, after being charged up to [Vcc−Vtsg] (provided that, Vtsg is a threshold voltage of the select gate transistor) via the select gate transistor.
Next, a control gate line of the select memory cell in the select NAND cell is set to Vpp (=about 20V: a high voltage for writing) from 0V, and the control gate line of the unselected memory cell in the select NAND cell is set to Vmg (=about 10V: a middle voltage) from 0V.
Here, when the bit line is 0V, in the connected select NAND cell, since the channel region in the NAND cell is fixed at 0V, large potential difference (=about 20V) occurs between a gate of the selected memory cell in the select NAND cell (=Vpp potential) and the channel region (=0V), and electron injection occurs from the channel region into a floating gate. Thereby, threshold voltage of the select memory cell is shifted to positive direction, and writing of “0” data is completed.
On the other hand, when the bit line is Vcc, in the connected select NAND cell, since the channel region in the NAND cell is in a floating state, along with voltage rise (from 0V to Vpp, Vmg) of the control gate line caused by the effect of capacity coupling between the control gate line in the select NAND cell and the channel region, while potential of the channel region maintains the floating state, [Vcc−Vtsg] potential is increased to Vmch (=about 8V). At this time, since potential difference between the gate of the select memory cell in the select NAND cell (=Vpp potential) and the channel region (=Vmch) is comparatively as small as about 12V, electron injection does not occur, and therefore threshold voltage of the select memory cell is not shifted but is maintained in the negative state, and the writing of “1” data is completed.
Next, the data erasing operation of the NAND cell type EEPROM is explained. A flowchart of the erasing operation of the NAND cell type EEPROM is shown in
Next, as shown in
In the nonvolatile semiconductor memory device 10 concerning this embodiment, data and a control signal are inputted into the command interface 17 and the column control circuit 12 through the data input and output buffer 16 from the external I/O pad 19. The state machine 18 controls the column control circuit 12, the row control circuit 13, the source line control circuit 14 and the P well control circuit 15 based on the control signal and the data. The state machine 18 outputs access information regarding memory cells of the memory cell array 11 to the column control circuit 12 and the row control circuit 13. The column control circuit 12 and the row control circuit 13 activate the memory cells based on the subject access information and the data, and reading, writing or erasing of the data is performed. The column control circuit 12 includes a sense amplifier and a data cache, and the sense amplifier connected to each bit line of the memory cell array 11 loads the data to a bit line and detects the potential of the bit line and holds it in the data cache. The data read from the memory cells by the sense amplifier controlled by the column control circuit 12 is outputted to the external I/O pad 19 through the data input and output buffer 16.
Next,
In this embodiment, each NAND type memory unit is configured by connecting four memory cells M in series, and one end is connected to the bit lines BL (BLe0 to BLe4255, BLo0 to BLo4255) via the select gate S connected to the select gate line SGD, and the other end is connected to the common source line C-source via the select gate S connected to the select gate line SGS. The control gate of each memory cell M is connected to the word lines WL (WL0_i to WL3_i). The even-numbered bit line BLe and the odd-numbered bit line BLo counted from 0 perform writing and read-out of data while mutually independent. Writing and read-out of data are simultaneously performed to 4256 units of memory cells connected to the even-numbered bit line BLe among 8512 units of the memory cells connected with one word line WL. The data of 1 bit which each memory cell memorizes will be 4256 units of the memory cells to constitute the unit of a page.
Similarly, another page is constituted of 4256 memory cells connected to the odd-numbered bit line BLo, and writing and read-out of data are simultaneously performed to the memory cells in a page. 4256 units of memory cells in 1 page will have a storage capacity of 532 bytes.
Although this embodiment includes the number of the blocks constituting a memory cell is set to 1024 and the NAND type memory unit composed of four memory cells which one block is 8512, it is not necessarily limited to this and the number of blocks, the number of memory cells and the number of memory units can be changed according to desired capacity.
Next,
After the data erasing operation is performed, verification is conducted whether the data of all memory cells in the selected block are erased completely. When it is verified that the data of all memory cells in the selected block are erased completely, erasing of the data is completed. On the other hand, when it is verified that a part of the data in all memory cells in the selected block are not erased, the data erasing operation is performed again. Accordingly, the data of the selected block is erased.
In this embodiment, another embodiment of a semiconductor memory device of the present invention is explained. The general configuration of the nonvolatile semiconductor memory device 10 of this embodiment is the same as the ones explained in the above-mentioned embodiment and
In this embodiment, each NAND type memory unit is configured to connect m units of the memory cells M in series, and one end is connected to the bit lines BL (BLo0 to BLe (n−1), BLo0 to BLo (n−1)) via the select gate S coupled to the select gate line SGD, and the other end is connected to the common source line C-source via the select gate S coupled to the select gate line SGS. The control gates of each memory cell M are connected with the word lines WL (WL0_i to WL(m−1)_i).
Here,
In this embodiment, the first domain and the second domain are used as a user area and a non-user area, respectively. The user area means a memory cell domain which can control writing, erasing and reading of the data by the command disclosed to a general user. The non-user area means a memory cell domain which can control writing, erasing and reading of the data by the command which is not open to the general user or is disclosed only to specific users, or is not open to any users.
In this embodiment, the memory cells shown by“A” and“B” of the second domain (the non-user area) of
For information, details regarding the protection flag are described in Japanese patent application 2003-336058 and Japanese laid-open publication 2005-108273, the entire contents of this reference being incorporated herein by reference.
Next,
As shown in
Next, the preprogram of the first domain is performed. By this preprogram, all of the memory cells in the first domain will be the positive threshold voltages (“0” data) Then, the data erasing operation is performed.
By performing the data erasing operation of the memory cells by such flow, incorrect writing and incorrect erasing of the protection memory cells “A” and “B” of the second domain can be prevented. To be more specific, suppose that preprogram is performed to all of the memory cells in the first and the second domain, after preprogram is finished, if a reset action is carried out before the data erasing operation starts, all of the memory cell data in the block will end with the positive threshold voltages (“0” data). The image diagram of the data in the block at that time is shown in
By preprogramming the first domain only without preprogramming the second domain as explained in this embodiment, the data of the second domain remains “1” data (the image diagram of the data in the block at that time is shown in
In the nonvolatile semiconductor memory device concerning this embodiment, by performing preprogram before carrying out the erasing operation to the area other than the area where the identification flag and others are memorized, incorrect erasing of the identification flag is prevented, and threshold voltage distribution after erasing the data can be narrower, and variation of time to complete writing of each memory cell at the time of the writing the data performed continuously after erasing the data can be smaller. In addition, a data-writing defect can be restrained.
In the above-mentioned embodiment 1, two memory cells “A” and “B” in the second domain are set as the writing operation protection flag cell and as the erasing operation protection flag cell, respectively. However, in this embodiment, combination of a plurality of memory cells is set to a protection flag cell. That is, the protection flag is set to stand according to combination of “0” and “1” data of a plurality of the memory cell.
For example, when a data pattern “0101” is memorized using four memory cells in the second domain, the protection flag is set to stand. By setting the protection flag to stand according to the data pattern of at least 2 bits or more, even if a reset action is performed before starting the data erasing operation after the preprogram ends, it can be set that the protection flag is not recognized to stand. The protection flag cell is not limited to 2 bits, and it can be formed depending on the memory cell of a desired bit number.
In the above-mentioned embodiment, Embodiment 1 and Embodiment 2, the NAND cell type nonvolatile semiconductor memory device is used as an example of the nonvolatile semiconductor memory device of one embodiment of the present invention. However, nonvolatile semiconductor memory devices such as a NOR cell type, a DINOR cell type, an AND cell type EEPROM and others can be used as a semiconductor memory device of one embodiment of the present invention.
The nonvolatile semiconductor memory device of one embodiment of the present invention can minimize variation of time to complete writing of each memory cell at the time of writing the data performed continuously after erasing the data. Therefore, according to the present invention, a high-speed nonvolatile semiconductor memory device can be realized. The nonvolatile semiconductor memory device of the present invention can be used as memory storage of electronic equipment including a computer, a digital camera, a cellular phone and home electronics.
Number | Date | Country | Kind |
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2004-354943 | Dec 2004 | JP | national |