Patent Application
20080246072
This application is based upon and claims the benefit of prior Japanese Patent Application No. 2007-100124, filed on Apr. 6, 2007, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as a NAND type flash memory, for example, and a manufacturing method of the same.
2. Description of the Related Art
Nonvolatile semiconductor memory devices which do not lose data even when power supplies are turned off are semiconductor devices which have been developed with the development of microcomputers, and such devices include NAND type flash memories.
A NAND type flash memory includes a NAND cell unit configured by a memory cell column constituted by connecting in series a plurality of memory cells each having a stack gate structure in which a floating gate as a charge-storage layer and a control gate are stacked, and a first selection transistor and a second selection transistor which are respectively connected between one end of the memory cell column and a common source line and between the other end of the memory cell column and a bit line.
When data write is performed in the NAND type flash memory, a write voltage is applied to the word line of the memory cell in which the data is written, and an intermediate voltage is applied to the word lines of the memory cells in which the data are not written. A predetermined positive voltage is applied to the common source line, and 0 V is applied to the gate of the selection transistor connected to the common source line. A predetermined positive voltage is applied to both of the bit line and the gate of the selection transistor connected to the bit line in the case of the bit line on which the data are not written.
On this occasion, both of the selection transistors are in off states, and channel potential of the memory cell column is boosted to positive voltage due to capacitive coupling between the floating gates of the memory cells and the channel. As a result, a memory cell adjacent to the selection transistor connected to the common source line receives an influence of a strong electric field in a lateral direction formed between the memory cell and the selection transistor, and electrons which are generated in the interface of the gate oxide film of the selection transistor and the silicon substrate become hot electrons which move to the adjacent memory cell along the surface of the silicon substrate. The hot electrons which thus generate flow into the floating gate of the memory cell adjacent to the selection transistor, and cause the phenomenon of programming the data of the adjacent memory cell, that is, erroneous write. This phenomenon occurs in the memory cell adjacent to the selection transistor, and hardly occurs in the other memory cells to which the memory cells are adjacent. The memory cell adjacent to the selection transistor and the memory cells other than this memory cell show different characteristics. This is due to the disturb phenomena which is caused by the above described hot electrons.
In order to prevent erroneous write in the memory cell adjacent to the selection transistor due to such a disturb phenomenon, Japanese Patent Laid-Open No. 2006-191017 discloses the invention relating to a NAND type flash memory with the configuration in which the distance between the selection transistor and the memory cell adjacent to this is increased. Japanese Patent Laid-Open No. 2006-186359 discloses the invention relating to a NAND type flash memory with the configuration in which a dummy memory cell is provided between the selection transistor and the memory cell adjacent to this. However, each of the inventions disclosed in these documents has the problem that the circuit area increases.
A nonvolatile semiconductor memory device according to one embodiment of the present invention comprises a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the aforesaid semiconductor substrate and connected between one end of the aforesaid memory cell column and a common source line, and a second selection transistor formed on the aforesaid semiconductor substrate and connected between the other end of the aforesaid memory cell column and a bit line, wherein a recessed portion is formed on a surface of the aforesaid semiconductor substrate between the aforesaid first selection transistor and a memory cell adjacent to the aforesaid first selection transistor, an edge at a side of the aforesaid first selection transistor in the aforesaid recessed portion reaches an end portion at a side of said memory cell in a gate of the aforesaid first selection transistor.
A nonvolatile semiconductor device according to another embodiment of the present invention comprises a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the aforesaid semiconductor substrate and connected between one end of the aforesaid memory cell column and a common source line, and a second selection transistor formed on the aforesaid semiconductor substrate and connected between the other end of the aforesaid memory cell column and a bit line, wherein an impurity diffusion layer for supplying a carrier formed in the aforesaid semiconductor substrate between the aforesaid first selection transistor and a memory cell adjacent to the aforesaid first selection transistor is positioned in a deeper layer-separated from a surface of the aforesaid semiconductor substrate.
A nonvolatile semiconductor memory device according to still another embodiment of the present invention comprises a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the aforesaid semiconductor substrate and connected between one end of the aforesaid memory cell column and a common source line, and a second selection transistor formed on the aforesaid semiconductor substrate and connected between the other end of the aforesaid memory cell column and a bit line, a write voltage being applied to a control gate of a selected memory cell of the aforesaid memory cell column, a pass voltage lower than the aforesaid write voltage being applied to a control gate of a non-selected memory cell of the aforesaid memory cell column, a ground voltage being applied to a gate of the aforesaid first selection transistor, a predetermined voltage which turns on or off said second selection transistor in accordance with data on the aforesaid bit line being applied to a gate of the aforesaid second selection transistor, and thereby the data on the aforesaid bit line being written in the aforesaid selected memory cell, wherein at least a part of a top surface of an impurity diffusion layer for supplying a carrier formed in said semiconductor substrate between the aforesaid first selection transistor and a memory cell adjacent to the aforesaid first selection transistor is deeper than a surface level of the aforesaid semiconductor substrate.
As shown in
Specifically, as shown in
The memory cells MC0 to MC15 are formed on the lower side from intersection portions of the word lines WL0 to WL15 and the bit line BL, and the selection transistors ST1 and ST2 are formed on the lower side from intersection portions of the selection gates SGS and SGD and the bit line BL.
As shown in
The floating gate 13 is separated for each memory cell MC, and the control gates 15 are formed continuously in a direction orthogonal to the bit line BL as the word lines WL or the selection gate SGS and SGD common to a plurality of memory cells MC or selection transistors ST1 and ST2, which are arranged in the direction orthogonal to the bit line BL. For the selection transistors ST1 and ST2, the floating gates 13 and the control gates 15 are short-circuited, and the transistors having normal gates 17 are configured.
In an area between the bit line BL and the bit line BL on the upper layer of the silicon substrate 11, an element isolation insulating film (STI (Shallow Trench Isolation)) 25 extending parallel with the bit line BL is formed. Thereby, stripe-shaped element formation regions separated from each other in the direction of the word line WL are defined on the upper layer of the silicon substrate 11.
Channel regions of the memory cells MC are formed in portions of the upper layers of the element formation regions, which are opposed to the floating gates 13 via the gate oxide films 12, and between these channel regions, first conductive type (for example, n-type) impurity diffusion layers 18 which become drains and sources shared by the adjacent memory cells MC are formed. A recessed portion 19 is formed on the surface of the silicon substrate 11 between the selection transistor ST1 at the common source side, and the memory cell MC0 adjacent to this, and an impurity diffusion layer 20 is formed at the lower side from the recessed portion 19. The recessed portion 19 is formed so that an edge at the side of the selection transistor ST1 reaches an edge of the gate 17 of the selection transistor ST1 at the side of the memory cell MO, and an edge at the side of the memory cell MC0 reaches an edge of the layered stack, which is constituted of the gate oxide film 12, the floating gate 13, the inter-gate insulating film 14 and the control gate 15, at the side of the selection transistor ST1. In spite of formation of the recessed portion 19, the channels of the memory cells MC0 to MC15 and the selection transistors ST1 and ST2 are formed at the surface level of the silicon substrate 11.
The layered stacks of the electrodes each constituted of the gate oxide film 12, the floating gate 13, the inter-gate insulating film 14 and the control gate 15, and the top surface of the silicon substrate between the layered stacks are covered with an interlayer insulating film 21. An interlayer insulating film 22 is formed on the interlayer insulating film 21, and the bit line BL is selectively formed on the interlayer insulating film 22.
In the NAND type flash memory thus configured, a plurality of memory cells MC extending along the direction of the word line WL are set as one page, and data write is performed by page. Specifically, at the time of data write, the substrate potential is set at 0 V first, and a write voltage Vpgm of, for example, 20 V is applied to the word line WL8 of the memory cells MC8 of the page for which write is performed, while an intermediate voltage Vpass of, for example, 12V is applied to the word lines WL0 to WL7, and WL9 to WL15 of the memory cells MC0 to MC7 and MC9 to MC15 for which write is not performed. Further, 0 V is applied to the gate of the selection transistor ST1 connected to the common source line CELSRC, and a predetermined voltage at which the gate is turned on or off in accordance with the data on the bit line BL is applied to the gate of the selection transistor ST2 connected to the bit line BL.
0 V is applied to the bit line BL connected to the memory cell MC in which “0” is to be written, and Vdd is applied to the bit line BL connected to the memory cell MC in which “1” is to be written.
Thereby, when “0” is written, the channels of the selection transistors ST2 and the memory cells MC15 to MC0 are at 0 V, and a large potential difference occurs between the floating gate and the channel of the memory cell MC8 in which data is to be written. Therefore, a tunnel current flows into the gate oxide film, and electrons are injected into the floating gate. Thereby, the threshold value of the memory cell MC8 in which the data is written increases, and the write is completed.
When “1” is written, both of the selection transistors ST1 and ST2 are brought into the OFF state, and therefore, the memory cell column MCC is brought into the floating state. Since the intermediate voltage Vpass is applied to the word lines connected to the non-selected memory cells, the channel potential of the non-selected memory cells is raised by capacitive coupling among the word lines, the floating gates and the semiconductor substrate. Thereby, the potential difference between the channels and the floating gates is made small, and erroneous write is prevented. This is called boosting.
According to the NAND type flash memory according to this embodiment, the recessed portion 19 is formed on the surface of the silicon substrate 11 between the selection transistor ST1 at the source side and the memory cell MC0 adjacent to it so that its edge is in contact with the selection transistor ST1, and therefore, the gate 17 of the selection transistor ST1 and the impurity diffusion layer 20 can be separated from each other in the vertical direction without increasing the circuit area. Thereby, even if the potential difference occurs between the selection transistor ST1 and the memory cell MC0, occurrence of GIDL can be suppressed, and the occurrence rate of erroneous write due to flow of hot electrons into the floating gate 13 of the memory cell MC0 can be reduced to the value equivalent to those of the other memory cells MC1 to MC15.
Next, based on
As shown in
Next, after polysilicon (not illustrated) is thinly deposited on the insulating film 14A, photoresist (not illustrated) is coated entirely thereon to perform prebake, exposure is performed by using a photomask 31 for forming an opening for short-circuiting the stacked gate of the selection transistor as shown in
Next, as shown in
Next, after photoresist (not illustrated) is coated on the second polysilicon film 15A, prebake is performed, a photomask 32 having openings for gate formation as shown in
Next, after photoresist (not illustrated) is coated on the entire surface, prebake is performed, exposure is performed by using a photomask 33 having an opening for forming a recessed portion in a part of the silicon substrate 11 as shown in
Next, by the same method, the silicon oxide film 12A is separated for each of the memory cells MC0 to MC15, and the gate oxide film 12 is formed as shown in
Subsequently, as shown in
The interlayer insulating film 21 such as a silicon nitride film and TEOS (tetraethoxysilane) is formed on the layered stacks of the electrodes each constituted of the gate oxide film 12, the floating gate 13, the inter-gate insulating film 14 and the control gate 15, and on the top surface of the silicon substrate 11 between these layered stacks, the common source line CELSRC (not illustrated) is selectively formed on the interlayer insulating film 21, the interlayer insulating film 22 is formed on the interlayer insulating film 21, and further, the bit line BL is selectively formed on the interlayer insulating film 22, whereby the NAND type flash memory shown in
As the method for preventing occurrence of GIDL, the method for controlling the profile of the impurity concentration in the diffused layer is conceivable. This method is used for relaxing the electric field in the diffusion layer, and is used for reducing the channel concentration and the impurity diffusion layer concentration. When the channel concentration is reduced, however, the short channel effect of the selection transistor and the memory cell becomes obvious, and write and erase characteristics and reliability are degraded. Reduction of the diffusion layer concentration works in the direction to decrease GIDL, but the electric field strength in the diffusion layer may rather increase. In addition to which, diffusion probability is reduced, and more electrons with high energy are likely to occur. Therefore, the method has the problem that optimization of the profile of the impurity concentration is difficult.
In this regard, according to this embodiment, the advantage of being able to suppress occurrence of GIDL without controlling the impurity concentration is provided.
Next, a second embodiment will be described.
According to such a configuration, in addition to the effect of the previous embodiment, acceleration and injection of the electrons into the floating gate 13 by the vertical electric field at the side of the memory cell MC0 can be mitigated.
Next, based on
The steps from
After the step of
Next, after photoresist (not illustrated) is coated on the entire surface, prebake is performed, exposure is performed by using a photomask 34 having an opening smaller than the previous photomask 33, as shown in
Subsequently, by performing isotropic etching such as wet etching by directly using the above described mask pattern, the recessed portion 41 which has a gentle curved section as shown in
Next, a third embodiment will be described.
This embodiment differs from the previous two embodiments in the respect that a recessed portion 44 in contact with the selection transistor ST1 is formed only at the side of the selection transistor ST1 in the surface of the silicon substrate 11 between the selection transistor ST1 and the memory cell MC0. An impurity diffusion layer 45 is formed from under the recessed portion 44 to the side of the memory cell MC0. In the selection transistor ST1, the inter-gate insulating film 14 at the side of the memory cell MC in the gate 17 does not exist.
In this embodiment, not only occurrence of GIDL can be prevented, but also acceleration and injection of the electrons into the floating gate 13 in the memory cell MC0 by the vertical electric field can be mitigated.
Next, based on
After photoresist (not illustrated) is coated on the insulating film 14A first and prebake is performed, in the states in
Next, as shown in
Next, after photoresist (not illustrated) is coated on the second polysilicon film 15A, prebake is performed, exposure is performed by using a photomask 36 having an opening for stacked gate formation as shown in
Thereafter, when etching for the insulating film 14A and the first polysilicon film 13A is performed, and etching advances to such an extent that the silicon oxide film 12A is exposed as shown in
Next, a fourth embodiment will be described.
In this embodiment, an impurity diffusion layer 47 for supplying a carrier formed between the selection transistor ST1 and the memory cell MC0 is formed in the deeper layer separated from the surface layer of the silicon substrate 11 by controlling the depth of ion-implantation of an impurity (for example, n-type), as shown in
In the above described embodiment, only the impurity diffusion layer 47 formed in the silicon substrate 11 between the selection transistor ST1 and the memory cell MC0 is formed to be separated from the surface of the silicon substrate 11, but as shown in, for example,
In this case, ion-implantation of the impurity diffusion layers by a mask does not need to be performed separately, and the advantage of being able to simplify the manufacture process is provided.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-100124 | Apr 2007 | JP | national |
