This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2009-151248, filed Jun. 25, 2009, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device having charge storage layers and a manufacturing method thereof.
2. Description of the Related Art
In a nonvolatile semiconductor memory device represented by a flash memory, it is indispensable to improve the quality thereof. The flash memory has memory cells that are formed as FG cells or MONOS cells. It is described in a pamphlet of International Publication No. 2004/023559 that each cell has a charge storage layer and control gate. Whether the characteristic of the cell is good or not is determined according to the charge holding characteristic of the charge storage layer used as one standard.
A nonvolatile semiconductor memory device according to an aspect of the invention includes:
first gate electrodes each having a charge storage layer formed above a semiconductor substrate with a tunnel insulating film interposed therebetween and a control gate electrode formed above the charge storage layer with an inter gate insulating film interposed therebetween;
a second gate electrode and a third gate electrode formed above the semiconductor substrate with a gate insulating film interposed therebetween, the second and the third gate electrodes are located oppositely in a gate length direction;
a first insulating film formed on each sidewall of the second and the third gate electrodes and formed on the surface of the semiconductor substrate in a region between the second gate electrodes and the third gate electrodes;
a first inter layer insulating film filled in a gap between the second gate electrodes and the third gate electrodes;
a second inter layer insulating film filled in a gap between the first gate electrode which is adjacent to the second gate electrode and the second gate electrode, and gaps between the first gate electrodes; and
a second insulating film formed on the first gate electrodes, the second gate electrode, the third gate electrode, the first insulating film, the first inter layer insulating film, and the second inter layer insulating film to suppress diffusion of hydrogen atoms included in the first inter layer insulating film.
A manufacturing method of a nonvolatile semiconductor memory device according to an aspect of the invention includes:
forming a first gate electrode having a charge storage layer, a inter gate insulating film and a control gate electrode sequentially formed above a semiconductor substrate with a tunnel insulating film interposed there between;
forming a second gate electrode and a third gate electrode above the semiconductor substrate with a gate insulating film interposed therebetween, the second and the third gate electrodes are located oppositely in a gate length direction;
filling a first inter layer insulating film in a gap between the first gate electrode and the second gate electrode;
forming a first insulating film along the surface of the semiconductor substrate and on sidewalls of the second gate electrode and the third gate electrode;
filling a second inter layer insulating film in a gap between the second gate electrode and third gate electrode; and
forming a second insulating film on the first gate electrode, the second gate electrode, the third gate electrode, the first insulating film, the first inter layer insulating film and second inter layer insulating film to suppress diffusion of hydrogen atoms included in the second inter layer insulating film.
An embodiment of this invention will be described with reference to the accompanying drawings. In this explanation, common reference symbols are attached to common portions throughout the drawings.
A nonvolatile semiconductor memory device according to one embodiment of this invention and a manufacturing method thereof are explained with reference to
<Memory Cell Array 1>
As shown in
As shown in
The control gate electrodes of the memory cell transistors MT that are arranged on the same row are commonly connected to a corresponding one of word lines WL0 to WL15. The gate electrodes of the select transistors ST1, ST2 of the memory cell transistors MT that are arranged on the same row are commonly connected to select gate lines SGD1, SGS1, respectively. For simplifying the explanation, if the word lines WL0 to WL15 are not distinguished, the word line may be simply referred to as a word line WL in some cases. Further, the drains of select transistors ST1 that are arranged on the same column in the memory cell array 1 are commonly connected to a corresponding one of bit lines BL0 to BLn. Further, if the bit lines BL0 to BLn are not distinguished, the bit line may be simply referred to as a bit line BL (n: natural number). The sources of select transistors ST2 are commonly connected to a source line SL.
Further, data is simultaneously written to the plural memory cell transistors MT connected to the same word line WL and the unit is called a page. In addition, data items in the plural NAND strings 11 are simultaneously erased in the block BLK unit.
<Cross-Sectional View of Memory Cell Array 1>
Next, the cross-sectional view of the memory cell array 1 with the above configuration is explained with reference to
Likewise, insulating films 109 are formed on the sidewalls of the gate electrodes of select transistors ST2 of blocks BLK0 and BLK1 and insulating films 110 with a film thickness of approximately 65 nm are formed on the surfaces of the insulating films 109. For example, an insulating film 111 of, for example, approximately 5 nm is formed on the surfaces of the insulating films 110 and the gate insulating film 104 that lies between select transistors ST2. For example, the insulating film 111 is formed of TEOS. An insulating film 112 is formed on the surface of the insulating film 111. The insulating film 112 is formed on each of sidewalls of the adjacent select transistors ST2 which are opposite in a gate length direction and is formed along the surface of p-type semiconductor substrate 100 in a region between the adjacent select transistors ST2. For example, the insulating film 112 is formed of SiN. Further, an insulating film 113 is formed to fill a gap between select transistors ST2 of blocks BLK0 and BLK1. For example, the insulating film 113 is an insulating film formed by using boron phosphor silicate glass BPSG) as a material. For example, a phospho-silicate glass (PSG) film, boron-silicate glass (BSG) film or none-doped silicate glass (NSG) film may be used other than the BPSG film. For example, an insulating film 114 with a film thickness of approximately several tens of nanometers is formed to coat the select transistors ST1, ST2, memory cell transistors MT and insulating films 109 to 112. In this embodiment, for example, the insulating film 114 is a film formed of SiN. The insulating film 114 may be formed of Al2O3. Thus, the insulating film 113 is isolated from the insulating films 109 and 110 formed between the memory cell transistors MT. That is, the insulating films 109 and 110 filled in the gaps between the respective memory cell transistors MT are isolated from the insulating film 113 by coating them with the insulating film 114.
In each of the memory cell transistors MT explained above, the gate insulating film 104 functions as a tunnel insulating film. The polysilicon film 105 functions as a floating gate and the polysilicon film 107 functions as a control gate. Those of the polysilicon films 107 that are adjacent with respect to the word line WL direction intersecting at right angles with the bit line direction in
In the select transistors ST1, ST2, those of the polysilicon films 105 that are adjacent in the word line WL direction are commonly connected. The polysilicon films 105 functions as the select gate lines SGS, SDS. Only the polysilicon film 105 may function as the select gate line. In this case, the potentials of the polysilicon films 107 of the select transistors ST1, ST2 are set at preset potentials, that is, the polysilicon films are set in a floating state.
In the surface areas of portions of the p-well region 102 each lying between the gate electrodes, n+-type impurity diffusion layers 103 are formed. The n+-type impurity diffusion layer 103 is commonly used by the two adjacent transistors and functions as a source (S) or drain (D). Further, the region between the adjacent source and drain functions as a channel region used as an electron mobile region. Thus, transistors used as the memory cell transistors MT and select transistors ST1, ST2 are formed of the above gate electrodes, n+-type impurity diffusion layers 103 and channel regions.
For example, an inter layer insulating film 115 formed of TEOS is formed to coat the memory cell transistors MT and select transistors ST1, ST2 on the p-type semiconductor substrate 100. On the inter layer insulating film 115, for example, an insulating film 116 formed of SiN is formed. The inter layer insulating film 115 is formed with a film thickness of approximately 50 nm, for example, and the insulating film 116 is formed with a film thickness of approximately 30 nm, for example.
A contact plug CP2 (not shown) that reaches the n+-type impurity diffusion layer 103 that is formed between select transistors ST2 respectively formed in the adjacent blocks BLK0 and BLK1 is formed in the p-well 102. Further, contact plug CP2 may be formed in the inter layer insulating film 115 and insulating film 116 and may be electrically connected to the source. In this case, a metal interconnect layer (not shown) that is connected to contact plug CP2 is formed on the surface of the inter layer insulating film 115. The metal interconnect layer acts as part of the source line SL. Further, a contact plug CP3 (not shown) that reaches the n+-type impurity diffusion layer (drain) 103 of select transistor ST1 on the drain side is formed in the inter layer insulating film 115 and insulating film 116. Contact plug CP3 is electrically connected to the bit line BL. Gate length means the direction where a sauce, a channel, and drain are located in a line.
<Manufacturing Process of Memory Cell Array 1>
Next, the manufacturing process of the memory cell array 1 is explained with reference to
First, as shown in
Next, as shown in
Subsequently, as shown in
Next, as shown in
Next, as shown in
The reliability of the operation can be enhanced by means of the nonvolatile semiconductor memory device according to this embodiment and the manufacturing method thereof. With the nonvolatile semiconductor memory device according to this embodiment and the manufacturing method thereof, hydrogen atoms can be suppressed from being diffused from the insulating film 113 at the anneal time. Next, a case wherein the SiN film 114 is not formed in this embodiment is explained.
In the manufacturing steps of
Further, when an insulating film 116 (SiN film) is formed directly on the select transistors ST1, ST2, the memory cell transistors MT and insulating films 109 to 113 instead of the SiN film 114, it can be expected to suppress hydrogen atoms in the insulating film 113 from being diffused due to the presence of the insulating film 116. However, at this time, the following problem occurs. In this case, the insulating film 116 is not formed above the insulating film 114 with the inter layer insulating film 115 interposed therebetween and the insulating film 116 (SiN film) is formed directly on the select transistors ST1, ST2, memory cell transistors MT and insulating films 109 to 113. As described before in the manufacturing process, after the insulating film 116 is formed, an insulating film is formed on the insulating film 116 and then a CMP process is performed with the insulating film 116 used as a stopper. Then, pressure caused by the CMP process is directly applied to the select transistors ST1, ST2 and memory cell transistors MT because the inter layer insulating film 115 is not formed. Therefore, there occurs a possibility that the select transistors ST1, ST2 and memory cell transistors MT may be destroyed.
In this respect, with the nonvolatile semiconductor memory device according to this embodiment and the manufacturing method thereof, the insulating film 114 is formed to coat the BPSG film 113 formed between select transistors ST2, the insulating films 109 to 112, the memory cell transistors MT and the select transistors ST1, ST2. Specifically, the SiN film 114 is formed to isolate the gate insulating film 104 and the insulating films 109, 110 formed between the memory cell transistors MT from the exterior. The SiN film 114 functions as a block film that suppresses passage of hydrogen atoms. Therefore, hydrogen atoms fetched by the BPSG film 113 in the manufacturing process can be suppressed from being discharged to the exterior from the BPSG film 113 at the anneal time. Specifically, hydrogen atoms in the BPSG film 113 can be suppressed from reaching the gate insulating film 104 functioning as a tunnel oxide film of the adjacent memory cell transistor MT. Further, hydrogen atoms diffused from the inter layer insulating film 115 and insulating film 116 formed on the SiN film 114 can be suppressed from reaching the gate insulating film 104. Therefore, the characteristic of the gate oxide film 104 lying directly under the memory cell transistor MT can be enhanced. Further, in the nonvolatile semiconductor memory device according to this embodiment and the manufacturing method thereof, the inter layer insulating film 115 and insulating film 116 are sequentially formed on the SiN film 114. Therefore, even if the CMP process is performed with the insulating film 116 used as a stopper, the inter layer insulating film 115 functions as an absorber and, as a result, a problem that the select transistors ST1, ST2 and memory cell transistors MT are destroyed can be suppressed.
In order to cause the SiN film 114 to function as a block film for suppressing passage of hydrogen atoms with respect to the gate insulating film 104, the SiN film 114 may be formed above the gate insulating film 104. However, as the SiN film is formed above and farther apart from the gate insulating film 104, the effect of the film used as the block film may become more significant.
Further, since diffusion of hydrogen atoms in the BPSG film 113 is also blocked by the insulating film (SiN) 112 that lies below the above film, it is desirable that the insulating film 112 be formed with such a film thickness that can suppress diffusion of hydrogen atoms.
The memory cell transistor MT is not limited to the FG structure or MONOS structure and can be formed with a NOR structure. Further, it can be applied to an EEPROM structure.
The material of the insulating film 114 formed on select transistors ST2, memory cell transistors MT, insulating films 109 to 112 and insulating film 113 is not limited to SiN or Al2O3 and various combinations of materials can be made according to the material of the insulating film 113. In other words, the material of the insulating film 114 can be changed according to the material of the insulating film 113. Specifically, if the insulating film 113 is formed of a material other than the material such as BPSG explained in the above embodiment, a material that suppresses atoms diffused from the insulating film 113 from reaching the gate insulating film might be applied to the insulating film 114.
Further, if atoms other than the hydrogen atoms are diffused from the insulating film 113, a material that suppresses the above atoms from being diffused may be applied to the insulating film 114.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Number | Date | Country | Kind |
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2009-151248 | Jun 2009 | JP | national |