Embodiments described below relate to a nonvolatile semiconductor memory device.
In recent years, in the field of NAND type flash memory, a stacked type (three-dimensional type) NAND type flash memory has been attracting attention as a device capable of achieving a high degree of integration without being limited by a resolution limit of lithography technology.
In such a three-dimensional type NAND type flash memory, ON/OFF characteristics (selection characteristics) of a select transistor are important, and it is required to pass a sufficient cell current during selection (during ON). On the other hand, during non-selection (OFF), it is desired that a leak current of the select transistor is made as small as possible.
A nonvolatile semiconductor memory device according to an embodiment described below comprises: a semiconductor substrate; a semiconductor columnar portion extending in a perpendicular direction to the semiconductor substrate; a memory gate insulating layer covering a side surface of the semiconductor columnar portion; a stacked body disposed so as cover a periphery of the semiconductor columnar portion and including a conductive layer and an inter-layer insulating layer stacked alternately in a stacking direction on the semiconductor substrate; and an epitaxial layer disposed on a surface of the semiconductor substrate and disposed so as to be electrically connected to a lower end of the semiconductor columnar portion. The semiconductor columnar portion comprises: an insulating film core; and a semiconductor portion disposed so as to cover a periphery of the insulating film core and electrically connected to the epitaxial layer at a lower end portion. The epitaxial layer includes a concave portion in a surface thereof, and the insulating film core has a lower end thereof positioned inside the concave portion.
Next, nonvolatile semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that these embodiments are merely examples, and are not shown with the intention of limiting the present invention. Moreover, each of the drawings of the nonvolatile semiconductor memory devices employed in the embodiments below is schematic, and thicknesses, widths, ratios, and so on, of layers differ from those of the actual nonvolatile semiconductor memory devices.
The embodiments below relate to a nonvolatile semiconductor memory device having a structure in which a plurality of MONOS type (Metal-Oxide-Nitride-Oxide-Semiconductor) memory cells (memory transistors) are provided in a height direction, each of the MONOS type memory cells including: a semiconductor layer acting as a channel provided in a column shape perpendicularly to a substrate; and a gate electrode layer provided on a side surface of the semiconductor layer via a charge accumulation layer. However, this also is not intended to limit the present invention, and the present invention may be applied also to a memory cell of another form of charge accumulation layer, for example, a SONOS type (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) memory cell or a floating gate type memory cell.
The nonvolatile semiconductor memory device 100 includes: a memory cell array 11; a word line drive circuit 12; a source side select gate line drive circuit 13; a drain side select gate line drive circuit 14; a sense amplifier 15; a word line WL; a source side select gate line SGS; a drain side select gate line SGD; a bit line BL; a word line wiring line portion, and so on.
The memory cell array 11 comprises the following, on a semiconductor substrate (not illustrated in
As will be mentioned later, the memory cell MC has a structure in which a control gate electrode (word line) is provided, via a memory layer including a charge accumulation layer, on a side surface of a columnar semiconductor film acting as a channel; and the drain side select transistor S1 and source side select transistor S2 have a structure in which a select gate electrode (select gate line) is provided, via a gate insulating film, on a side surface of a columnar semiconductor portion. To simplify illustration,
The word line WL is commonly connected to memory cells adjacent in the XY plane. Moreover, similarly, the source side select gate line SGS is also commonly connected to source side select transistors S2 adjacent in the XY plane, and similarly, the drain side select gate line SGD is also commonly connected to drain side select transistors S1 adjacent in the XY plane.
Note that in the description below, the source side select gate line SGS and the drain side select gate line SGD are sometimes collectively written simply as “select gate line”. Moreover, the source side select transistor and the drain side select transistor are sometimes collectively written simply as “select transistor”.
In addition, sometimes, one or a plurality of the memory cells MC close to the source side select gate line SGS and the drain side select gate line SGD, of the memory cells MC in the memory string MS, is treated as a dummy cell not employed in data storage. In the example described below, one dummy cell is respectively provided to both ends of the memory string MS, but the present invention is not intended to be limited to this configuration and there may be two or more dummy cells, moreover, it is also possible for the dummy cell to be omitted. Note that it is also possible for a plurality of the drain side select transistors S1 and/or the source side select transistors S2 to be connected to one memory string MS. To simplify description, an example where one drain side select transistor S1 and one source side select transistor S2 are connected to one memory string MS is mainly described below.
Furthermore, the bit lines BL are disposed so as to extend having the Y direction that intersects the X direction as their longer direction, and are arranged with a certain pitch in the X direction. The bit line BL is connected to a plurality of the memory strings MS via the drain side select transistor S1. Although illustration thereof is omitted in
The word line drive circuit 12 is a circuit that controls a voltage applied to the word line WL; and the source side select gate line drive circuit 13 is a circuit that controls a voltage applied to the source side select gate line SGS. Furthermore, the drain side select gate line drive circuit 14 is a circuit that controls a voltage applied to the drain side select gate line SGD. Moreover, the sense amplifier 15 is a circuit that amplifies a signal (voltage) read in the bit line BL from a selected memory cell.
A wiring line portion 20 is a wiring line portion for connecting the word line WL and the select gate lines SGD and SGS to a contact. The word line WL and the select gate lines SGS and SGD have a structure of being processed in steps so as to each be capable of being connected to the contact independently at their upper portions.
Next, details of a structure of the memory cell array 11 will be described with reference to
As shown in
The conductive layer 22 may be formed by, for example, tungsten (W), tungsten nitride (WN), tungsten silicide (WSix), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSix), palladium silicide (PdSix), erbium silicide (ErSix), yttrium silicide (YSix), platinum silicide (PtSix), hafnium silicide (HfSix), nickel silicide (NiSix), cobalt silicide (CoSix), titanium silicide (TiSix), vanadium silicide (VSix), chromium silicide (CrSix), manganese silicide (MnSix), iron silicide (FeSix), ruthenium (Ru), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), or copper (Cu), or by a compound of these. However, the conductive layer 22 may also be formed by polysilicon to which an impurity is added.
Moreover, as shown in
These semiconductor layers 23 are connected at their upper ends to the bit line BL via a contact Cb. The bit lines BL are arranged with a certain pitch in the X direction having the Y direction as their longer direction.
In addition, a lower end of the semiconductor layer 23 is electrically connected to the semiconductor substrate SB. The lower end of the semiconductor layer 23 is connected to the source line SL via a later-to-be-described epitaxial layer 108 (not illustrated in
Note that the stacked body of the inter-layer insulating film 21 and the conductive layer 22 in the memory cell array 11 is divided on a block-by-block basis, the block being a minimum unit of data erase. A trench Tb is formed at a boundary of division, this trench Tb is implanted with an unillustrated inter-layer insulating film, and the previously mentioned source contact LI is further formed penetrating that inter-layer insulating film. This source contact LI has its lower end connected to the semiconductor substrate SB while having its upper end connected to the source line SL.
An example of a specific structure of one memory cell MC is shown in
Formed in a periphery of this semiconductor columnar portion 102 so as to surround the semiconductor columnar portion 102 are a tunnel insulating layer 103, a memory layer 104 (charge accumulation layer), and a block insulating layer 105. The tunnel insulating layer 103, the memory layer 104, and the block insulating layer 105 configure a memory gate insulating layer GL. The tunnel insulating layer 103 is configured from, for example, a silicon oxide film (SiOx), and functions as a tunnel insulating layer of the memory cell MC. The memory layer 104 includes, for example, a silicon nitride film (SiN), and functions to trap (accumulate) electrons injected via the tunnel insulating layer 103 from the semiconductor columnar portion 102 by a write operation. The block insulating layer 105 may be formed from, for example, a silicon oxide film. In this example, the block insulating layer 105 differs from the tunnel insulating layer 103 and the memory layer 104, and is formed so as to surround a periphery of the conductive layer 22.
The above-described tunnel insulating layer 103, memory layer 104, and block insulating layer 105 are referred to collectively as the memory gate insulating layer GL. In the case of
Note that also employable as a material of the tunnel insulating layer 103 and the block insulating layer 105, besides a silicon oxide film (SiOx), are, for example, Al2O3, Y2O3, La2O3 Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, AlSiO, and so on.
Moreover, the epitaxial layer 108 is formed so as to surround a lower end of the semiconductor columnar portion 102. The epitaxial layer 108 is, for example, a silicon layer of single crystals that may be formed by epitaxial growth using as an underlayer the semiconductor substrate SB configured from monocrystalline silicon. In the case of using the semiconductor substrate SB as an underlayer, the epitaxial layer 108 becomes a monocrystalline silicon layer formed continuously from the semiconductor substrate SB.
Contrary to the epitaxial layer 108, the semiconductor columnar portion 102 is usually formed by polysilicon which is different from monocrystalline silicon. In this case, a crystal grain boundary does not exist in the epitaxial layer 108, and a current may be more easily passed compared to in the semiconductor columnar portion 102.
A lower end of the epitaxial layer 108 is positioned lower than a surface of the substrate SB. On the other hand, an upper surface of the epitaxial layer 108 is positioned at least higher than an upper surface of the lowermost layer conductive layer SGSB of the plurality of conductive layers 22 configuring the select gate line SGS (refer to
Such an epitaxial layer 108 is configured for the following reason. Due to progress of miniaturization, in the case of forming a memory hole MH for forming the semiconductor layer 23, it is generally difficult to stop processing of that memory hole MH close to the surface of the substrate SB, and the memory hole MH ends up digging deeply into the surface of the substrate SB. In the case that the memory hole MH has ended up digging deeply into the surface of the substrate SB, there is a risk that if the semiconductor layer 23 configured from the likes of polysilicon is formed in that memory hole unchanged in such a state, a resistance value of the memory string MS ends up increasing and a cell current ends up being reduced.
Accordingly, in the present embodiment, the above-mentioned kind of epitaxial layer 108 is formed in a bottom of the memory hole MH, and the semiconductor layer 23 is electrically connected to the substrate SB via this epitaxial layer 108. As a result of such an epitaxial layer 108 that has a monocrystalline structure being formed in the memory hole MH formed by digging deeply into the substrate SB, an increase in the resistance value of the memory string MS can be suppressed and a lowering of the cell current can be prevented.
Moreover, the epitaxial layer 108 of the present embodiment includes a concave portion 108E close to the center of its upper end. Lower end portions of the insulating film core 101 and the semiconductor columnar portion 102 are formed so as to penetrate inside this concave portion 108E. The semiconductor columnar portion 102 is disposed at a position between the epitaxial layer 108 and the insulating film core 101, inside the concave portion 108E.
The concave portion 108E is configured such that at least a lower end of the insulating film core 101 reaches any one of the plurality of conductive layers 22 configuring the select gate line SGS. In the illustrated example, the lower end of the insulating film core 101 reaches the lowermost layer conductive layer SGSB (has an end portion at a position of the conductive layer SGSB).
As a result of the concave portion 108E and the insulating film core 101 being formed in this way, a current flowing in the source side select transistor S2 is limited to close to the gate electrode. This makes it possible for the leak current during OFF of the select transistor S2 to be reduced. In the case that the epitaxial layer 108 does not include the concave portion 108E, and the whole of the base of the memory hole MH is filled by the epitaxial layer 108, a current may also flow close to the center of the memory hole MH. In this case, the OFF leak current of the select transistor S2 cannot be sufficiently reduced. Due to the present embodiment, the insulating film core 101 can be formed close to the center of the epitaxial layer 108, hence a current can be prevented from flowing close to the center of the memory hole MH, and the OFF leak current during OFF of the select transistor S2 can be reduced.
Note that in the illustrated example, the lower end of the insulating film core 101 reaches the lowermost layer conductive layer SGSB, but the present embodiment is not intended to be limited to this configuration. It is also possible to adopt instead a configuration in which, for example, the lower end of the insulating film core 101 reaches at least one of the conductive layers SGS1 through SGS3, but does not reach the conductive layer SGSB. In this case also, the leak current during OFF of the source side select transistor S2 can be sufficiently suppressed.
This epitaxial layer 108 may be formed by an epitaxy method using the substrate SB as an underlayer (homo-epitaxial growth), but may be formed also by an epitaxy method employing a material different from that of the substrate SB (hetero-epitaxial growth). In the case of hetero-epitaxial growth, an unillustrated buffer layer may be disposed between the epitaxial layer 108 and the substrate SB. By configuring in this way, the epitaxial layer 108 becomes electrically connected to each of the substrate SB and the semiconductor columnar portion 102, resulting in electrical contact being achieved between the semiconductor columnar portion 102 and the substrate SB.
Moreover, the previously mentioned source contact LI is implanted via the inter-layer insulating film 21′ in the trench Tb dividing the memory cell array 11. Although illustration thereof is omitted, the source contact LI may also be formed such that its lower end electrically contacts the substrate SB via a diffusion layer (not illustrated) formed in the surface of the substrate SB.
[Method of Manufacturing Memory Cell MC]
Next, a method of manufacturing the memory cell MC will be described with reference to
First, as shown in
Then, as shown in
Next, as shown in
Subsequently, as shown in
Subsequently, as shown in
Then, as shown in
[Charge Accumulation Layer]
In the above described embodiment, a silicon nitride film (SiN) was given as an example of a material of the charge accumulation layer included in the memory layer 104. However, the following oxides may also be selected as the material of the charge accumulation layer, namely:
SiO2, Al2O3, Y2O3, La2O3 Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, AlSiO;
AB2O4 (where A and B are the same or different elements, and are one of Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, and Ge; for example, Fe3O4, FeAl2O4, Mn1|xAl2-xO4|y, CO1|xAl2-xO4|y, MnOx, and so on); and
ABO3 (where A and B are the same or different elements, and are one of Al, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, and Sn; for example, LaAlO3, SrHfO3, SrZrO3, SrTiO3, and so on).
Moreover, the following oxynitrides may also be selected as the material of the charge accumulation layer, namely:
SiON, AlON, YON, LaGN, GdON, CeON, TaON, HfON, ZrON, TiON, LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON, and AlSiON.
Furthermore, it is also possible to adopt a material in which some of the oxygen elements of the above-described oxides are substituted by a nitrogen element. Specifically, single and multiple insulating layers are each preferably selected from the group of SiO2, SiN, Si3N4, Al2O3, SiON, HfO2, HfSiON, Ta2O5, TiO2, and SrTiO3.
Specifically, concentrations of oxygen elements and nitrogen elements in silicon system insulating films such as SiO2, SiN, SiON may each be set to 1×1018 atoms/cm3 or more. However, barrier heights of the multiple insulating layers differ from each other. Moreover, the insulating layer may include a material that includes an impurity atom forming a defect level or a semiconductor/metal dot (quantum dot).
As described above, due to the present embodiment, the epitaxial layer 108 is formed in the base of the memory hole MH, and this epitaxial layer 108 is connected to a lower end of the semiconductor layer 23 configuring a channel portion of the memory string MS. As a result, a sufficient cell current can be obtained at the lower end of the memory string. Moreover, the concave portion 108E is formed in the surface of the epitaxial layer 108, and the insulating film core 101 is formed so as to penetrate inside this concave portion 108E. This makes it possible to suppress the leak current flowing in the center of the memory string MS far from the select transistor S2, during OFF operation of the select transistor S2.
Next, a nonvolatile semiconductor memory device according to a second embodiment will be described with reference to
This second embodiment differs from the first embodiment in having a solid phase epitaxial layer 102A formed inside the concave portion 108E of the epitaxial layer 108. This solid phase epitaxial layer 102A can be formed by setting appropriate amorphous deposition conditions and annealing conditions in the case where the semiconductor columnar portion 102 configured from polysilicon is formed by depositing an amorphous film similarly to in
Due to the configuration of this second embodiment, similar advantages to those of the first embodiment are obtained. In addition, the solid phase epitaxial layer 102A makes it possible to further improve conductivity at the base of the memory string MS and to increase an ON current during conductivity of the select transistor S2.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based on and claims the benefit of priority from prior US prior provisional Patent Application No. 62/134,638, filed on Mar. 18, 2015, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
62134638 | Mar 2015 | US |