Patent Application
20210376034
The application claims priority to Chinese patent application No. 201710785779.6 filed on Sep. 4, 2017, the entire disclosure of which is incorporated herein by reference as part of the present application.
Embodiments of the present disclosure relates to an OLED display panel and a manufacturing method thereof, and an OLED display device.
By bonding an OLED (organic light emitting diode) display panel to a FPC (flexible printed circuit), the OLED display panel connects to a PCB (printed circuit board), and therefore connects to a mainboard.
Bonding the OLED display panel to the FPC may be realized through the following processes: before forming a source-drain pattern, forming a via-hole penetrating through an insulation layer at the periphery area of the OLED display panel; and then forming a source-drain electrode layer to overlay the via-hole; next, sequentially forming a planarization layer, a pixel define layer, a spacer layer, and exposing the source-drain electrode layer, forming a connection wire in a via-hole region, and allowing the connection wire to electrically connect the source-drain electrode layer and to electrically connect the IC (integrated circuit) of the FPC.
However, the planarization layer, the pixel define layer and the spacer layer are relatively smooth in the via-hole region, and therefore the connection wire cannot firmly adhere to the via-hole region, the connection wire is subject to fall off, which results in the bonding defect between the OLED display panel and the FPC.
The embodiments of the present disclosure provide an OLED display panel and a manufacturing method thereof, and an OLED display device, which can be at least partially used to solve the problem that the connection wire for bonding the OLED display panel and FPC is easy to fall off.
According a first aspect of the present disclosure, an OLED display panel is provided and the OLED display panel comprises a base substrate, a connection wire, and an insulation layer, a source-drain electrode layer and a planarization layer which are sequentially provided on the base substrate, wherein a first via-hole penetrating through the insulation layer is provided in the insulation layer, the source-drain electrode layer overlays the first via-hole, and the connection wire is provided in the first via-hole, wherein a second via-hole penetrating through the planarization layer is provided in the planarization layer at a position corresponding to the first via-hole, and the second via-hole is in communication with the first via-hole, and wherein the planarization layer and the source-drain electrode layer form a first step at a position of the second via-hole, and the connection wire overlays the first step.
According a second aspect of the present disclosure, an OLED display device is provided, and the OLED display device includes the above-mentioned OLED display panel.
According a third aspect of the present disclosure, a method for manufacturing an OLED display panel is provided, and the method comprises: forming an insulation layer on a base substrate, and forming a first via-hole penetrating through the insulation layer; forming a source-drain electrode layer at a first via-hole region of the insulation layer; forming a planarization layer, and forming a second via-hole penetrating through the planarization layer at a position of the planarization layer corresponding to the first via-hole, wherein the second via-hole is in communication with the first via-hole, the planarization layer and the source-drain electrode layer form a first step at a position of the second via-hole; and forming a connection wire at a position corresponding to the second via-hole and the first via-hole, so as to allow the connection wire to overlay the first step.
In order to clearly illustrate the technical solution of the embodiments of the disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the disclosure and thus are not limitative of the disclosure.
In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.
Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present application for disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. “On.” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly.
As illustrated in
For example, both the first via-hole 6 and the second via-hole 7 are provided at the periphery area of the OLED display panel, the connection wire 5 is used to electrically connect with a flexible printed circuit (FPC) 12, and the connection wire 5 is, for example, made of a conductive material. For example, the source-drain electrode layer 3 is provided in the same layer as the source electrode and the drain electrode of the thin film transistor array in an active area (AA) region and manufactured at the same time with the source electrode and the drain electrode of the thin film transistor array in the AA region.
In the OLED display panel provided by the embodiment of the present disclosure, the first via-hole 6 is formed in the insulation layer 2, and the source-drain electrode layer 3 overlays the first via-hole 6. The planarization layer 4 is on the insulation layer 2 and the source-drain electrode layer 3. The second via-hole 7 is in the planarization layer 4, and the second via-hole 7 is in communication with the first via-hole 6. The first step 41 made up of the planarization layer 4 and the source-drain electrode layer 3 is at the position of the second via-hole 7. The connection wire 5 is in at least the first via-hole 6 and the second via-hole 7 and overlays at least the first step 41, that is, the connection wire 5 is connected to the planarization layer 4 via the first step 41; in this way, the connection wire 5 is not easy to fall off the via-hole area, and the adhesion between the connection wire 5 and the planarization layer 4 is more firm. As a result, the bonding effect between the OLED display panel and the FPC and the stability of signal transmission are both increased.
For example, as illustrated in
For example, as illustrated in
For example, the first via-hole 6, the second via-hole 7, the third via-hole 10 are concentric, and the diameter of the third via-hole 10 is greater than the diameter of the second via-hole 7. The third via-hole 10, the diameter of which is greater than the diameter of the second via-hole 7, is in the pixel define layer 8, and the third via-hole 10 is in communication with the second via-hole 7 and the first via-hole 6. The pixel define layer 8 and the planarization layer 4 form a closed loop second step 81 at the position of the third via-hole 10. The connection wire 5 is further provided in the third via-hole 10 and overlays the second step 81, that is, the connection wire 5 is connected to the pixel define layer 8 through the second step 81. In this way, the connection wire 5 is not easy to fall off the via-hole area, and the adhesion between the connection wire 5 and the pixel define layer 8 is more firm. As a result, the bonding effect between the OLED display panel and the FPC and the stability of signal transmission are both further increased. As illustrated in
For example, as illustrated in
For example, the first via-hole 6, the second via-hole 7, the third via-hole 10 and the fourth via-hole 11 are concentric, and the diameter of the fourth via-hole 11 is greater than the diameter of the third via-hole 10. The fourth via-hole 11, the diameter of which is greater than the diameter of the third via-hole 10, is in the spacer layer 9, and the fourth via-hole 11 is in communication with each of the third via-hole 10, the second via-hole 7 and the first via-hole 6. The spacer layer 9 and the pixel define layer 8 form the third step 91 at the position of the fourth via-hole 11. The connection wire 5 is further provided in the fourth via-hole 11 and overlays the third step 91, that is, the connection wire 5 is connected to the spacer layer 9 through the third step 91. In this way, the connection wire 5 is not easy to fall off the via-hole area, and the adhesion between the connection wire 5 and the spacer layer 9 is more firm. As a result, the bonding effect between the OLED display panel and the FPC and the stability of signal transmission can be further increased. As illustrated in
For example, as illustrated in
For example, the base substrate 1 is a flexible substrate, and the base substrate 1 is provided at the side of the insulation layer 2 away from the planarization layer 4. A through-hole 13 is provided in the source-drain electrode layer 3 and the base substrate 1 at the position corresponding to the bottom of the first via-hole 6, and the through-hole 13 runs through the source-drain electrode layer 3 and the base substrate 1.
For example, the OLED display panel further includes the FPC 12. The FPC 12 is provided at the side of the base substrate 1 away from the insulation layer 2, and a signal line 121 is provided on the FPC 12. The connection wire 5 is connected to the signal line 121 via the through-hole 13, such that a display module and the FPC are bonded to each other.
For example, the region, on which the signal line are not provided, of FPC 12 adheres to the base substrate 1.
For example, the position of the signal line 121 corresponds to the position of the through-hole 13, that is, the signal line 121 is exactly provided at the position of the through-hole 13, or the signal line 121 overlays the through-hole 13. In this way, the connection wire 5 is directly connected to the signal line 121 under the through-hole 13.
It should be noted that, the insulation layer 2 may include a plurality of layers. For example, in an embodiment of the present disclosure illustrated in
The embodiments of the present disclosure further provide an OLED display device, the OLED display device includes the above-mentioned OLED display panel, and the OLED display device, for example, is a flexible OLED display device.
In the OLED display device provided by the embodiments of the present disclosure, the first via-hole 6 is formed in the insulation layer 2, and the source-drain electrode layer 3 overlays the first via-hole 6. The planarization layer 4 is on the insulation layer 2 and the source-drain electrode layer 3. The second via-hole 7 is in the planarization layer 4, and the second via-hole 7 is in communication with the first via-hole 6. The first step 41 made up of the planarization layer 4 and the source-drain electrode layer 3 is at the position of the second via-hole 7. The connection wire 5 is in at least the first via-hole 6 and the second via-hole 7 and overlays at least the first step 41, that is, the connection wire 5 is connected to the planarization layer 4 via the first step 41; in this way, the connection wire 5 is not easy to fall off the via-hole area, and the adhesion between the connection wire 5 and the planarization layer 4 is more firm. As a result, the bonding effect between the OLED display panel and the FPC and the stability of signal transmission are both increased.
The embodiments of the present disclosure further provide a method for manufacturing an OLED display panel, and the method is used to manufacture the above-mentioned OLED display panel. For example, a method for manufacturing the OLED display panel is described in detail with reference to
In the embodiments of the present disclosure, no specific limitations will be given to the method for fabricating each layer. For example, a film pattern may be formed through a patterning process with respect to a film which is formed by a physical film formation method or a chemical film formation method. The patterning process includes a lithography patterning process, an inkjet printing process, and so on. For example, the lithography patterning process may include the following processes: coating a photoresist layer onto a film to be patterned; performing exposure to the photoresist layer with a mask, developing the photoresist layer after exposure, so as to obtain a photoresist pattern; etching the film with the photoresist pattern as a mask; finally, removing the remaining photoresist to obtain the desired film pattern. Descriptions are given to the following embodiment by taking the lithography patterning process (the patterning process for short) as an example.
As illustrated in
For example, a photoresist layer is coated onto the insulation layer 2, and the first via-hole 6 penetrating through the insulation layer 2 is obtained through performing exposure with a mask, development and etching to the base substrate 1 which has gone through the above-mentioned steps.
For example, the insulation layer 2 includes a buffer layer 21, a gate insulation layer (GI) 22 and an interlayer insulation layer (ILD) 23. The buffer layer 21, the gate insulation layer 22 and the interlayer insulation layer 23 are sequentially formed on the base substrate 1, and the first via-hole 6 runs through each of the buffer layer 21, the gate insulation layer 22 and the interlayer insulation layer 23.
As illustrated in
For example, depositing a metal film for forming the source-drain electrode at a first via-hole region of the insulation layer 2, coating a photoresist layer onto the metal film for forming the source-drain electrode, and forming the pattern of the source-drain electrode layer 3 at the first via-hole region of the insulation layer 2 through performing exposure with a mask, development and etching to the base substrate 1 which has gone through the above-mentioned steps. It should be noted that, the pattern of the source-drain electrode layer 3 may be manufactured at the same time with the source electrode pattern and the drain electrode pattern of the thin film transistor array in the AA region, and therefore no additional patterning step is needed.
As illustrated in
As illustrated in
As illustrated in
As illustrated in
For example, the through-hole 13 penetrating through both the source-drain electrode layer 3 and the base substrate 1 may be formed, in the base substrate 1 and the source-drain electrode layer 3 at the position corresponding to the bottom of the first via-hole 6, by using laser.
As illustrated in
As illustrated in
It should be noted that, the first step 41, the second step 81 and the third step 91 may also be formed by half-tone mask technology with a halftone mask, and in this case, the number of the patterning processes can be reduced by two correspondingly.
If the OLED display panel includes only the first step 41, and does not include the second step 81 and the third step 91, the connection wire 5 overlays the first step 41. If the OLED display panel includes only the first step 41 and the second step 81, and does not include the third step 91, the connection wire 5 overlays the first step 41 and the second step 81.
In the method for manufacturing an OLED display panel, the first via-hole 6 is formed in the insulation layer 2, and the source-drain electrode layer 3 overlays the first via-hole 6. The planarization layer 4 is on the insulation layer 2 and the source-drain electrode layer 3. The second via-hole 7 is in the planarization layer 4, and the second via-hole 7 is in communication with the first via-hole 6. The first step 41 made up of the planarization layer 4 and the source-drain electrode layer 3 is at the position of the second via-hole 7. The connection wire 5 is in at least the first via-hole 6 and the second via-hole 7 and overlays at least the first step 41, that is, the connection wire 5 is connected to the planarization layer 4 via the first step 41; in this way, the connection wire 5 is not easy to fall off the via-hole area, and the adhesion between the connection wire 5 and the planarization layer 4 is more firm. As a result, the bonding effect between the OLED display panel and the FPC and the stability of signal transmission are both increased. The manufacturing processes for the OLED display panel is simple, the above-mentioned layers of the OLED display panel can be manufactured at the same time with corresponding film structures of the thin film transistor array in the AA region, and therefore no additional manufacturing process is needed.
In the present disclosure, the following statements should be noted:
(1) The accompanying drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).
(2) For the purpose of clarity only, in accompanying drawings for illustrating the embodiment(s) of the present disclosure, the thickness of a layer or area may be enlarged or narrowed, that is, the drawings are not drawn in a real scale.
(3) In case of no conflict, features in one embodiment or in different embodiments can be combined to obtain new embodiments.
What is described above is related to the illustrative embodiments of the disclosure only and not limitative to the scope of the disclosure; the scopes of the disclosure are defined by the accompanying claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201710785779.6 | Sep 2017 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/090093 | 6/6/2018 | WO | 00 |
