Claims
- 1. A method of forming a metal-insulator-metal capacitor structure over an insulative layer having an exposed via the method comprising:depositing a metal-insulator-metal capacitor stack on top of the via; masking and etching an upper electrode of the metal-insulator-metal capacitor stack; depositing and etching a first spacer on an edge surface of the upper electrode; defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer; and depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode.
- 2. The method of forming a metal-insulator-metal capacitor structure of claim 1, further comprising:forming a wiring layer on a surface of the upper electrode and a surface of the second spacer.
- 3. The method of forming a metal-insulator-metal capacitor structure of claim 1, wherein the upper electrode is formed outside an edge portion of the via.
- 4. The method of forming a metal-insulator-metal capacitor structure of claim 1, wherein the first and second spacers comprise an insulative material.
- 5. The method of forming a metal-insulator-metal capacitor structure of claim 1, wherein the upper electrode and the lower electrode comprise titanium nitride.
Parent Case Info
The present Application is a Divisional Application of U.S. patent application Ser. No. 10/063,140, filed on Mar. 25, 2002 now U.S. Pat. No. 6,452,779.
US Referenced Citations (13)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2000-22083 |
Jan 2000 |
JP |