BRIEF DESCRIPTION OF THE DRAWINGS
The above and other aspects of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:
FIG. 1 is an exploded perspective view showing an embodiment of an optical waveguide device according to an exemplary embodiment of the present invention;
FIG. 2(
a) to FIG. 2 (l) is a sectional view showing a method of manufacturing the optical waveguide device according to an exemplary embodiment of the present invention;
FIG. 3 is an exploded perspective view showing a related art optical waveguide device; and
FIG. 4(
a) to FIG. 4(h) is a sectional view showing the method of manufacturing the related art optical waveguide device of FIG. 3.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE PRESENT INVENTION
FIG. 1 is an exploded perspective view showing an optical waveguide device according to an exemplary embodiment of the present invention.
FIG. 1 shows that an optical waveguide device 10 comprises an optical waveguide part 16, which includes an optical waveguide forming layer 15 with lower cladding layers 121 and 122, a core layer 13, and an upper cladding layer 14 formed on a silicon substrate 11. The optical waveguide device 10 also includes a photonic device mounting part 17 formed by eliminating a part of the optical waveguide forming layer 15. A light emitting device 18, which is mounted on the photonic device mounting part 17, is optically connected to an end face of the optical waveguide part 16, which is exposed by the elimination of a part of the optical waveguide forming layer 15.
The photonic device mounting part 17 comprises a pedestal block 19, an alignment marker 20, and a mask 22. The pedestal block 19 and the alignment marker 20 consist of the partially remaining lower cladding layer 121. In the upper part of the pedestal block 19 and the alignment marker 20, the lower cladding layer 122, the core layer 13, and the upper cladding layer 14 are eliminated. The mask 22 comprises a chromium film 21 provided on the lower cladding layer 121. The light emitting device 18 contacts the mask 22. The mask 22 functions as an etching mask to partially leave the lower cladding layer 121.
The lower cladding layers 121 and 122 and the core layer 13 consist of a plasma CVD film. The plasma CVD film is annealed at 1,000° C. or over after the film formation. By using this film, it is possible to increase a refractive index difference between the core layer 13 and the lower cladding layer 122. Therefore, a flexibility in designing an optical waveguide is significantly improved.
FIG. 2 shows a method of manufacturing the optical waveguide device of FIG. 1, where the operations proceed in order of FIG. 2(a) to FIG. 2(l). Hereinafter, an explanation according to an exemplary embodiment of the present invention will be given based on FIG. 1 and FIG. 2.
In FIG. 2(a), the lower cladding layer 121 is formed as a first layer on the silicon substrate 11 by a plasma CVD. If necessary, a high-temperature annealing process at about 1,100° C. can be performed after the formation of the layer.
In FIG. 2 (b), a SiN film 31, which later becomes an etching stop layer 32, is formed on the lower cladding layer 121 by the plasma CVD. Subsequently, the SiN film 31 is patterned, to leave the SiN film 31 in an area for mounting the light emitting device 18. For instance, a thermal phosphoric acid can be used as an etchant in this case. The reason for using SiN is that it is highly heat-resistant, and has high selectivity with SiO2 in wet etching with a hydrofluoric acid mixture, such as a buffered hydrofluoric acid (NH4F/HF/H2O). However, because the stress of the SiN film is generally very high, it is important to reduce the stress by patterning it once in this operation. Another reason for using SiN is that it can also be formed by the plasma CVD. It is also possible to use a SiON film of which N substitution is large, instead of the SiN film.
In FIG. 2 (c), the lower cladding layer 122 is formed as a second layer by the plasma CVD. If necessary, a high-temperature annealing process at about 1,100° C. can be performed after the formation of the layer.
In FIG. 2 (d), a SiON film, which becomes the core layer 13, is deposited by the plasma CVD again, and the waveguide is patterned on the core layer 13 by dry etching. Thereafter, the high-temperature annealing process at about 1,100° C. may be performed. The high-temperature annealing process may be performed before patterning the waveguide if the thermal stress is not problematic.
In FIG. 2 (e), an upper cladding layer 141 is deposited as the first layer for embedding the core layer 13. The upper cladding layer 141 is then reflow-processed at about 850° C. to embed the core layer 13. The upper cladding layer 141 may be a low melting film, such as BPSG film.
In FIG. 2 (f), an upper cladding layer 142 is formed as the second layer to complete the optical waveguide forming layer 15.
In FIG. 2 (g), a photoresist film 23 is formed on the optical waveguide forming layer 15, which becomes the optical waveguide part 16. The silicon dioxide films, including the lower cladding layer 122, the core layer 13, and the upper cladding layer 14 on the etching stop layer 32, are eliminated by dry etching. However, because the selectivity of SiN with SiO2 is low, it would be preferable to perform dry etching performed up to a state where a little SiO2 is left. Reactive Ion Etching (RIE) is suitable for this dry etching.
In FIG. 2 (h), the remaining SiO2 is eliminated by wet etching of a hydrofluoric acid mixture, such as a buffered hydrofluoric acid, by using the SiN film 31 as the etching stop layer. Thus, the portion to become the photonic device mounting part 17 is clearly separated from the portion to become the optical waveguide part 16.
In FIG. 2 (i), the SiN film 31 used as the etching stop layer is eliminated by the thermal phosphoric acid. This is to prevent a deterioration of the height accuracy of the pedestal block 19. This is because the SiN film 31 is etched a little in FIG. 2 (h) and the amount of the etching of the SiN film 31 cannot be controlled.
In FIG. 2 (j), the mask 22 for forming the pedestal block 19 is formed by depositing the chromium film 21 and a photoresist film 24 on the exposed lower cladding layer 121 and patterning the chromium film 21. The mask 22 for forming the alignment marker 20, which is required when mounting the light emitting device 18, is simultaneously formed. In addition, the chromium film 21 is simultaneously patterned as an etching mask for forming the end face of the core layer 13.
In FIG. 2 (k), the end face of the core layer 13 is newly exposed by dry etching by using the chromium film 21 patterned in FIG. 2 (j) as an etching mask. Also, the pedestal block 19 and the alignment marker 20 are simultaneously formed. To achieve accurate etching, an etching rate of the chromium film 21 should desirably be 1/10 or less of the etching rate of the lower cladding layer 121. The reactive ion etching (RIE) is suitable for this dry etching.
In FIG. 2 (l), the light emitting device 18 is mounted on the mask 22 of the pedestal block 19 to set an active layer 181 of the light emitting device 18 and the core layer 13 opposed, and to complete the optical waveguide device 10. In this case, the chromium film may be eliminated, and an insulating film or an electrode metal may be formed and patterned as required. For example, in FIG. 2 (l), the chromium film 21 on the optical waveguide part 16 is eliminated. Incidentally, in FIG. 2, the heat treatment temperature of each individual operation is indicated.
As described above, the apparatus and manufacturing method for providing an optical waveguide device according to exemplary embodiments of the present invention can obtain the following effects. The chromium film 21, which becomes the mask 22, is formed on the lower cladding layer 121 after the lower cladding layer 122, the core layer 13, the upper cladding layer 14, and the etching stop layer 32 are eliminated. Therefore, there is no influence on the chromium film 21, even if the lower cladding layers 121 and 122 and the core layer 13 undergo the heat treatment at a high temperature before forming the chromium film 21. The lower cladding layer 121, which determines the height accuracy of the pedestal block. 19, is protected by the etching stop layer 32 or the mask 22 during the manufacturing process. Therefore, it is possible to make the pedestal block 19 with high accuracy without damaging the functions of the mask 22, even when a heat treatment at a high temperature is required.
In other words, according to exemplary embodiments of the present invention, the chromium film 21, which becomes the mask 22, is patterned after the high-temperature annealing process to form the pedestal block 19. Therefore, it becomes possible to make the pedestal block 19 with high accuracy.
While exemplary embodiments of the present invention have been described above, it is to be understood that numerous modifications to the exemplary embodiments of the invention will be apparent to those skilled in the art without departing from the spirit and scope of the present invention, as defined in the following claims and their legal equivalents.
Patent Application
20070253670
