Patent Application
20200309845
The disclosure herein relates to the field of a test and inspection technology, in particular to an optimization method for an integrated circuit wafer test.
ATE (Automatic Test Equipment): an automatic testing machine for semiconductor integrated circuits (IC), used to check the integrity of the functions of integrated circuits. Wafer: wafer refers to a silicon wafer used in the manufacture of silicon semiconductor integrated circuits, because its shape is circular, it is called a wafer. Die: an independent integrated circuit chip on the wafer.
Due to the advancement of integrated circuit design and manufacturing technology, the chip size is getting smaller and smaller, but the silicon wafer size has been increased from 200 mm to 300 mm. There are 100,000 chips, and due to the large number of integrated circuit test parameters and long test time, it is usually necessary to test a large number of integrated circuit wafers for all dies, which requires a large amount of test time, which increases the test cost accordingly.
Secondly, the probe card used for wafer testing has a certain service life. When the probe card contacts the die on the wafer once, there will be a certain loss, and after a certain number of times, it will affect the test results and cannot be used. The cost of designing and manufacturing test probe cards is also quite expensive. In the face of the testing needs of a large number of wafers, frequent production of probe cards also increases the cost of hardware expenditure.
The present invention proposes an optimization method for an integrated circuit wafer test to solve the problem of low wafer test efficiency. The method is used in integrated circuit wafer testing, pre-specifying the die coordinates to be tested and storing them in the test system, testing the specified die during the test and adjusting in real time according to test results, finally getting the required test coordinate graphic reference to the generated test, thereby reducing test time, improving testing efficiency, reducing the frequency of testing hardware usage and increasing service life.
The technical solution of the present invention is: an optimization method for an integrated circuit wafer test, it includes the following steps:
1) pre-designing a number of dies and coordinates of a die for a wafer to be tested by means of the size of the wafer, the number of dies and the number of test stations that the probe card can test;
2) storing the coordinates of a die to be tested in a coordinate library to be tested, storing the other coordinates in a coordinate library not to be tested and designing the walking sequence of the wafer test;
3) obtaining the coordinates of a die to be tested from the coordinate library to be tested by a test system, starting the test, controlling the wafer prober to test at a specified coordinates by the control system, by means of the coordinates sent by the test system;
4) the test result is returned to the test system and the test result is judged by the test system:
5) continue to return to step 3) for the next coordinate die test until the coordinate library to be tested is tested;
6) processing all the coordinates testing result in the coordinate library not to be tested as being qualified;
7) merging the coordinate library that has completed the test and the coordinate library not to be tested, if the coordinates exist in the two libraries at the same time, the coordinate library that has completed the test is taken as the final result, and combining coordinate libraries to generate actual test graphics for subsequent processes.
The specific step of pre-designing the test graphics in step 1) includes the following steps: designing the test graphics by means of the overall chip yield and the test efficiency to be achieved, firstly pre-setting the coordinates, and the edge of the wafer is the area that must be tested, take 1 or 2 die on the edge as a unit, setting one circle of the edge of the wafer as the test coordinate; secondly setting the middle position as required, designing the test position module and spacing value according to the product yield of the product and the required test efficiency, setting the coordinates of the whole wafer according to the test coordinates; finally combine test coordinates as design test graphics.
The beneficial effects of the present invention are: the optimization method for an integrated circuit wafer test, for products with more mature technology and higher wafer yield, the method of the present invention can significantly improve test efficiency and reduce test time. Through proper calculation of the number of coverage, less FAIL chips will flow to the package without increasing the cost of the package. At the same time, the number of times the needle card is lowered is reduced, and the hardware life is increased.
Different types of chips and different manufacturing processes result in a huge difference in wafer yield. It may be 99% for product A, 70% for product B, and 20% to 30% for product C. But the test need to test all die of the whole wafer. For product A, 1% of defective products need to be picked, but the test time of the whole piece needs to be paid, and the test efficiency and cost ratio are poor.
From the statistics of a large number of wafer test results, there is a large correlation between the failure of adjacent die, that is, if the die with (X=100, Y=100) coordinates is in a failed state, with the die as the center, There is a high probability of failure of the 8 die around it.
By pre-specifying the die coordinates to be tested and storing them in the test system, testing the specified die during the test and adjusting in real time according to test results, finally getting the required test coordinate graphic reference to the generated test, thereby reducing test time, improving testing efficiency, reducing the frequency of testing hardware usage and increasing service life.
1. pre-designing a number of dies and coordinates of a die for a wafer to be tested by means of the size of the wafer, the number of dies and the number of test stations that the probe card can test;
2. storing the coordinates of a die to be tested in a coordinate library to be tested, storing the other coordinates in a coordinate library not to be tested and designing the walking sequence of the wafer test;
3. obtaining the coordinates of a die to be tested from the coordinate library to be tested by a test system, starting the test, controlling the wafer prober to test at a specified coordinates by the control system, by means of the coordinates sent by the test system;
4. the test result is returned to the test system and the test result is judged by the test system, (1) if the test result is qualified, then put the coordinates of the die into a coordinate library that has completed the test; (2) if the test result is failed, then put the coordinates of the die into a coordinate library that has completed the test, the test system generates 8 die coordinates around the center of the coordinates of the die, mark the position of the chip coordinates around the die to be tested and failed die 4 as shown in
5. continue to return to step 3) for the next coordinate die test until the coordinate library to be tested is tested;
6. processing all the coordinates testing result in the coordinate library not to be tested as being qualified;
7. merging the coordinate library that has completed the test and the coordinate library not to be tested, if the coordinates exist in the two libraries at the same time, the coordinate library that has completed the test is taken as the final result, and combining coordinate libraries to generate actual test graphics for subsequent processes.
Firstly pre-setting the coordinates in step 1, the test graphics can be set flexibly. Normally, it should be designed according to the previous piece yield and the test efficiency to be achieved. Normally, the edge of the wafer is prone to failure due to processes and cutting, and this part of the area must be tested (taking 1 or 2 on the edge), secondly setting the middle position according to the requirements. The module and the spacing value are designed according to the product yield of the product itself. Taking the schematic diagram of two preset coordinates at the edge of the wafer as shown in
A single test time is 4.56 s, a single wafer has a total of 1220 die, a lot has a total of 25 wafers, the test efficiency statistics are shown in Table 1:
The algorithm of test graphics can not only consider the reduction of test time, but should comprehensively consider the coverage of failed chips, so the complete test of this batch, the statistical results are shown in Table 2:
From a statistical point of view, the higher the yield, the lower the FAIL Miss yield (test failure rate), which will cause the Fail chip to flow to the next level for packaging fewer, which will not cause the packaging cost to rise.
Secondly, the test graphics can also be changed by appropriately increasing the number of test dies. For example, the previous 2×2 module is spaced at 3×3; when it is modified to 2×2, 1×1, the statistical results are shown in Table 3 and Table 4:
From the statistical results, increasing the number of tests can significantly improve FAIL Miss yield. According to this, the design test graphics can be adjusted to achieve a reasonable detection accuracy rate, which saves time and guarantees the accuracy rate in the later period.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201810264068.9 | Mar 2018 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/081529 | 4/2/2018 | WO | 00 |
