Patent Application
20080246134
The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits.
A variety of techniques are used to stack packaged integrated circuits into a module. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. Both leaded and BGA (e.g., CSP) type packaged integrated circuits (ICs) have been stacked. Although array packaging has become widely adopted, leaded packages are still employed in large volumes in low cost applications such as, for example, flash memory, which typically is packaged in thin small outline packages otherwise known as TSOPs.
When leaded packages such as TSOPs are stacked, a variety of techniques have been employed. In some cases, the leads alone of packaged circuits have been used to create the stack and interconnect its constituent elements. In other techniques, structural elements such as printed circuit boards (PCBs) are used to create the stack and interconnect the constituent elements.
Circuit boards and rail-like structures in vertical orientations have been used for years to provide interconnection between stack elements. For example, in U.S. Pat. No. 5,514,907 to Moshayedi, a technique is described for creating a multi-chip module from surface-mount packaged memory chips. The devices are interconnected on their lead-emergent edges through printed circuit boards oriented vertically to a carrier or motherboard that is contacted by connective sites along the bottom of the edge-placed PCBs. The PCBs have internal connective rail-like structures or vias that interconnect selected leads of the upper and lower packaged memory chips. Japanese Patent Laid-open Publication No. Hei 6-77644 discloses vertical PCBs used as side boards to interconnect packaged circuit members of the stack. In U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack. Another technique for stacking leaded packaged ICs with carrier structures or interposers oriented along lead bearing sides of packaged devices such as TSOPs is disclosed by the present assignee, Staktek Group L.P., in U.S. Pat. No. 6,608,763 issued Aug. 19, 2003, to Burns et al., which is incorporated herein by reference for all purposes.
Many of the previously cited and known techniques for using PCBs and similar interposer structures for stacking leaded packaged devices into modules have evolved to meet the increased connective complexity presented by, for example, stacking memory components that have two or more chip enables per packaged device. Connectivity complexities, however, can arise in any applications where there is a need to connect non-adjacent leads of the module ICs. In some cases, this evolution has included use of interposer designs that employ four metal-layer designs to implement the more complex connection strategies required by more complex devices. Size limitations and other factors applicable to packaged IC stacking, however, have led to complexities in via and connection strategies. For example, trace routing and other connective requirements for interposers or carrier structures used in many applications may require the use of buried vias and/or blind vias. In various applications, the micro vias are used for blind vias. The use of multi-layer PCBs with buried vias and blind vias to address complex routing and other connective demands, however, increases costs and may present quality issues due to tight tolerances required.
What is needed, therefore, is a new system and method for stacking leaded packaged devices that accommodates interconnection between the constituent ICs of a multi-package stacked module without use of an interposer or carrier structure but yet can implement more complex connection strategies.
The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the body of one or more leaded packaged ICs bears circuitry to provide stacking-related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs. In a preferred two-IC stack embodiment, at least some connections between respective upper and lower ICs are implemented by interconnection of respective leads of the upper and lower stack ICs while stacking-related connections are implemented with the circuitry borne by the body of the upper one of the ICs.
Each of ICs 10 and 20 are, in the described preferred embodiment, encapsulated memory circuits disposed in thin small outline packages known as TSOPs. Each of the constituent ICs of the depicted exemplar module 5 exhibit IC bodies 12, while upper IC 20 exhibits leads 22 and lower IC 10 exhibits leads 24. In the depicted embodiment of stacked module 5, as shown in further detail in later FIGS., leads 22 of upper IC 20 differ from leads 24 of lower IC 10 in that leads 22 of upper IC 20 extend down from the upper IC 20 to lower IC 10 at certain respective lead positions along edges or sides 271 and 272 of module 5. Those of skill will recognize that techniques other than direct lead-to-lead connection may be employed to effectuate the connections illustrated as direct lead-to-lead connection shown in the embodiment shown in
Other package types may be used with the present invention as well as packaged circuits other than memories but, as described here with examples, many embodiments will be implemented with memories in TSOP packaging. Flash memory circuits implemented in TSOP packaging are one type of preferred constituent ICs 10 and 20. In the illustrated embodiment, there is no gap between IC 10 and IC 20, but embodiments may exhibit an air gap between constituent ICs or, alternatively, a heat transference material or adhesive between the ICs. The employed adhesive may be thermally conductive.
Circuitry 25 may be implemented in a variety of ways including, as a non-limiting example, printing conductive traces 31 with a conductive ink that is preferably curable. Other exemplar alternative constructions for traces 31 may include dispensable conductive materials, for example, such as conductive particles suspended in an adhesive, a conductive ink, or conductive epoxy. Solder paste is one type of such conductive material that could be used for traces 31. Conductive traces 31 may also be devised with a conductive pattern that is constructed on a release liner, laminated or transferred to the body of the IC and then the release liner pulled away. In any case, traces are typically to be borne by the surface of body 12 of IC 20. Exemplar conductive traces that are borne by the surface 28 of an IC are identified in the Figs as 31A while traces that reside in channels or grooves imposed in body 12 will be identified as traces 31B. Later
Following is a description of an exemplar connection in which trace 31B1 participates. MF1 is a contact pad in a mounting field MF to which module 5 is connected. MF may be, for example, on a motherboard. MF1 is connected to lead 241 (through the foot of that lead 241). Lead 241 is connected to lead 221 which is connected to trace 31B1 that is borne by body 12 of IC 20 and extends about to lead 24E1. Thus, if site MF1 is the source for an enable signal and leads 221 and 241 are in a N/C position on ICs 20 and 10, respectively, and lead 24E1 is an enable pin for IC 20, persons of skill will understand that IC 20 can be enabled by a signal applied to MF1. Those of skill will notice that lead 24E1 has been truncated or clipped to avoid connection with the corresponding lead 24 of IC 10 because the enable signal conveyed through trace 31B1 is devised to enable IC 20 while leaving IC 10 unaffected. No carrier structure or interposer was required to selectively enable IC 20. Another exemplar connection identified between MF2 and 24E2 is realized through trace 31A1 as shown. Provision of multiple such connective paths such as the example of one such path as illustrated between MF1 and 24E1 illustrate the flexibility of the embodiments through which realization of a variety of intra-stack and/or stacking related connections in circuit module 5 can be implemented.
Although the present invention has been described in detail, it will be apparent that those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.
