The field of invention pertains generally to the semiconductor arts, and, more specifically, to a package on package structure having package to package interconnect composed of packed wires having a polygon cross section.
The semiconductor arts has traditionally faced the challenge of attempting to integrate electronic functionality into as small a volume as possible. Package on package structures have recently emerged as a popular packaging technology for integrating multiple semiconductor die into a same semiconductor package.
A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
Pads 104 and collapsed micro-solder balls 105 reside on the upper surface of the lower substrate 101 to electrically connected a lower die 106 to the top surface of the lower substrate 101. The lower die 106 is encapsulated with a mold compound 107. Off the periphery of the lower die 106, stacked solder ball structures 108 within through mold vias (TMVs) form an electrical connection (through mold interconnect (TMI)) between the lower substrate 101 of the PoP structure and the I/O pads 109 on the underside of an upper substrate 110 of an upper packaged die 111 that is mounted on the lower packaged die 106.
As semiconductor chip minimum feature dimensions continue to shrink, die sizes may become smaller which should provide for smaller package-on-package structures. However, also because of the smaller minimum feature sizes, the number of I/Os that a die may entertain can increase. For example, a memory die with reduced minimum feature size may integrate more storage cells and therefore may be designed to include more address lines. The increased number of I/Os, in turn, causes a need for more stacked solder ball structures such as structure 108 within the package on package structure 100.
Another semiconductor die manufacturing trend that is driving package-to-package interconnect upwards in PoP structures is the emergence of three dimensional monolithic semiconductor circuits. As an example, some memory technologies are building the storage cells in the interconnect metallurgy rather than within the semiconductor substrate. As a consequence, the storage cells are not only arranged in arrays in a same plane, but arrays of storage cells are stacked on top of one another to produce a three dimensional memory array rather than a two dimensional memory array. As with reduced minimum feature sizes, the emergence of three dimensional circuits is also integrating more function into a single die which can increase the I/O count of an upper die 111, which, in turn, drives the number of package to package interconnects 108 in a package on package structure 100 upward.
A problem with traditional PoP structures is the spatial inefficiency of the stacked solder ball 108 technology. Specifically, stacked solder ball technology has a relatively large pitch (e.g., approximately 0.4 mm to 0.5 mm). Stacked solder ball pitch, as is understood in the art, is the distance between the respective centers of two neighboring stacked solder ball structures.
As such, the packing density of the package-to-package interconnect 108 within a package-on-package structure is not keeping up with the increasing number of package-to-package interconnects 108 that need to be integrated into the PoP structure 100. As such, more and more of the footprint dimensions of a PoP structure 100 is determined by the interconnect structures 108 that surround the lower die 106 rather than the surface area dimensions of the die 106.
The relatively large pitch of the stacked solder ball 108 solution is generally due to the immaturity of through mold via technology. Further still, the solder balls 108 themselves have a relatively large height (e.g., 0.3 mm per solder ball which corresponds to a stacked solder ball structure of approximately 0.6 mm). Here, note that reducing the dimension of the solder balls, e.g., to effect smaller pitch for higher interconnect packing density, can also result in stacked solder ball heights that are not high enough.
With a stacked solder ball structure 108 height of approximately 0.6 mm, the entire package-on-package structure from the top of the upper package to the bottom of the lower package die can have a total height of approximately 1.0 mm which may be too high for certain applications (especially handheld device applications). Alternative solutions to stacked solder balls, such as wire bonding or high copper pillars (HCP) do not demonstrate significantly better pitch tolerances at least over stacked solder ball 108 structures.
However, with pitch reduction improvements of 0.3 mm, 0.25 mm and 0.2 mm, the number of rows that can be supported on the same sized lower substrate increases to four rows, five rows and six rows, respectively. Here, each additional row that can be integrated into the package corresponds to an entire row's worth of additional interconnections. Additionally, also generally observed in
As can be seen in
In an embodiment, the square wires have a cross width distance 520 of less than 0.2 mm which approximately corresponds to a wire-to-wire pitch of 0.2 mm. With interconnect pitches of less than 0.3 mm, interconnect densities such as those enumerated in region 310 of
The particular embodiment of
According to the embodiment of
In embodiments having a top side lid, the top side lid may have openings to expose the upper faces of the interposers 521 which act as the topside I/O for the lower package. In such embodiments, one or more outer layers of the stacked wires of the interposers 521 are not used an electrical contacts but rather as a landing area for such a topside lid. Here, an adhesive may be applied on the landing area to ensure hermetic sealing of the lower package around the openings in the lid where the interposers are exposed. More details concerning application of a top side lid to a lower package are described below with respect to
The bottom-side I/Os 525 of the upper package are mounted directly onto the exposed interposers 521 (with, e.g., solder balls/bumps 524 in sandwiched in between). For the upper package connection, in an embodiment, solder bumps/balls 524 are placed on pads 525 formed on the bottom side of the substrate of the upper package.
As observed in
As observed in
Referring to
Where the solder/balls are preformed may vary from embodiment to embodiment. For example, in some embodiments all solder balls/bumps are formed on the underside of the die and the interposer, in other embodiments all solder balls/bumps are formed on the topside of the lower substrate, in yet other embodiments, some solder balls/bumps are formed on the underside of the die or interposer whereas other solder balls/bumps are formed on the topside of the lower substrate.
In various embodiments, as alluded to above, to attach an interposer 721 to the lower substrate 701, the interposer 721 is placed over a pad array formed on the top surface of lower substrate 701 in an aligned fashion. That is, for example, in an embodiment where the solder balls/bumps are preformed on the pad array, the lower face of each square wire of the interposer 721 is aligned with its own respective pad array location and corresponding solder bump/ball. The interposer 721 is then lowered onto the array of bumps/balls such that each square wire face rests on its corresponding bump/ball.
The ambient is then heated to collapse the bumps/balls and electrically connect each square wire face to its corresponding pad. In an embodiment, the ambient is flash heated to a higher than usual temperature so that each bump/ball associated with a particular interposer 721 collapses at approximately the same time or, at least, an attempt is made to limit the time difference between when outer balls of a same interposer collapse versus when inner solder bumps/balls of the interposer collapse. Alternatively, an attempt is made to uniformly collapse bumps/balls a same approximate distance from the center of the array at the same time.
Here, with ambient heating, solder bump/balls within the inner portions of the array may heat more slowly than the outer portions of the array. If the solder balls fail to collapse in a uniform way, the weight of an interposer 721 could cause the interposer to lean or list (although extended heating should cause the interposer to eventually settle correctly). The solder balls/bumps underneath the die 706 should be designed to approximately match the collapse dynamics of the interposer solder bumps/balls (although, again, an extended elevated temperature range should ensure that all solder bumps/balls eventually collapse).
In another embodiment, after an interposer 721 is resting on the bump/ball array, the exposed upper faces of the square wires of the interposer 721 are put in contact with a hot iron that uniformly heats each of the wires approximately equally over time. In a further embodiment, the hot iron is applied after the die's solder balls/bumps have been collapsed and the die 706 is fully mounted to the lower substrate.
By way of thermal conduction of the iron's heat through the square wires themselves, the respective temperatures of the lower faces of the square wires heat to approximately same temperatures over time and uniformly collapse their respective solder balls at approximately the same time. In an embodiment, the iron has a specially structured face having an array of blunt tips where each tip makes individual contact with its respective one of the wires to ensure that the uniform heating of all the wires to approximately same temperatures over time.
After the interposers 721 and die 706 are mounted on the lower substrate 701, as observed in
In the particular embodiment of
As observed in
A new layer of copper wire is applied to the spool each time the lateral movement of the wire as it is wound switches direction (leftwise or rightwise) across the width of the spool. Eventually, enough windings of the spool will have transpired to correspond to the number of layers called for in the design of the interposer.
Referring to
Although embodiments above have stressed square wires it is pertinent to note that other shapes wires may also be used without departing significantly from the spirit of the enclosed teachings. For example, instead of square wires, wires having any of a triangular, pentagonal, hexagonal, or octagonal cross section may be packed together to form an interposer. That is, more generally, the cross sections of the wires may be a polygon.
An applications processor or multi-core processor 950 may include one or more general purpose processing cores 915 within its CPU 901, one or more graphical processing units 916, a memory management function 917 (e.g., a memory controller) and an I/O control function 918. The general purpose processing cores 915 typically execute the operating system and application software of the computing system. The graphics processing units 916 typically execute graphics intensive functions to, e.g., generate graphics information that is presented on the display 903. The memory control function 917 interfaces with the system memory 902.
Each of the touchscreen display 903, the communication interfaces 904-907, the GPS interface 908, the sensors 909, the camera 910, and the speaker/microphone codec 913, 914 all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the camera 910). Depending on implementation, various ones of these I/O components may be integrated on the applications processor/multi-core processor 950 or may be located off the die or outside the package of the applications processor/multi-core processor 950.
The computing system 900 may include a package on package structure having interposers composed of packed square metal wires as the package to package interconnect embodiments of which have been described at length above. The semiconductor die in either the upper or lower package may be any kind of semiconductor die. In one embodiment a system on chip having processing cores and a system memory controller is the lower die and a memory chip used for the system memory is the upper die. In yet another embodiment the lower die includes a memory controller and the upper die includes a memory chip. In various other embodiments at least one of the upper and lower die includes primarily analog circuitry. In yet other embodiments, at least one of the upper die includes is an application specific integrated circuits (ASIC). In still other embodiments at least one of the upper and lower die is any of a programmable logic device (PLD), a digital signal processor (DSP), or a field programmable gate array (FPGA).
An apparatus has been described. The apparatus includes a package on package structure. The package on package structure includes an interposer to implement electrical interconnections between an upper package of the package on package structure and a lower package of the package on package structure. The interposer includes packed wires where the packed wires have respective polygonal cross sections.
In various embodiments of the apparatus the packed wires include copper wires. In various embodiments of the apparatus respective ones of the packed wires include an insulating jacket. In various embodiments of the apparatus an adhesive is present between respective insulating jackets of respective ones of the packed wires. In various embodiments of the apparatus the packed wires include packed square wires. In various embodiments of the apparatus the packed wires have any of the following cross sectional shapes: triangular; pentagonal; hexagonal; octagonal. In various embodiments of the apparatus a compound mold surrounds a lower die of the lower package. In various embodiments of the apparatus empty space surrounds a lower die of the lower package.
A computing system has been described. The computing system includes a plurality of processing cores. The computing system includes a system memory controller. The computing system includes a system memory coupled to the memory controller. The computing system includes a network interface. The computing system includes a package on package structure. The package on package structure includes an interposer to implement electrical interconnections between an upper package of the package on package structure and a lower package of the package on package structure. The interposer includes packed wires where the packed wires have respective polygonal cross sections.
In various embodiments of the computing system the packed square wires comprise copper. In various embodiments of the computing system respective ones of the packed wires include an insulating jacket. In various embodiments of the computing system an adhesive is present between respective insulating jackets of respective ones of the packed wires. In various embodiments of the computing system the packed wires include packed square wires. In various embodiments of the computing system the packed wires have any of the following cross sectional shapes: triangular; pentagonal; hexagonal; octagonal. In various embodiments of the computing system a compound mold surrounds a lower die of the lower package. In various embodiments of the computing system empty space surrounds a lower die of the lower package.
A method has been described. The method includes building a lower package structure for a package-on-package structure. The lower package structure includes an interposer disposed on a substrate of the lower package structure. The interposer is composed of packed polygonal wires.
In various embodiments of the method the method further includes affixing an upper package structure on the lower package structure such that lower I/Os of the upper package structure align with upper surfaces of respective ones of the polygonal wires. In various embodiments of the method the method further includes building the interposer. In various embodiments of the method the polygonal wires have any of the following cross sectional shapes: triangular; square; pentagonal; hexagonal; octagonal.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.