Some conventional current sensors are positioned near a current-carrying conductor to sense a magnetic field generated by a current through the conductor. The current sensor generates an output signal having a magnitude proportional to the magnetic field induced by the current through the conductor.
According to the disclosure, a method of manufacturing a current sensor integrated circuit package includes providing a lead frame comprising a primary conductor and at least two secondary leads, wherein the primary conductor comprises an input portion and an output portion, a first die attach portion, a second die attach portion, and a current conductor portion, wherein the primary conductor is configured to carry a current from the input portion through the first die attach portion, the current conductor portion, the second die attach portion, and the output portion. The method further includes providing a first mold of an insulating material to partially enclose part of the output portion, the first and second die attach portions, and the at least two secondary leads, providing an insulator portion on the first die attach portion, second die attach portion, current conductor portion, and the first mold, providing a semiconductor die on the insulator portion, providing wire bonds to connect the semiconductor die to the at least two secondary leads, providing at least one magnetic field sensing element supported by the semiconductor die and positioned near the current conductor portion, and providing a second mold of an insulating material to enclose the semiconductor die, wire bonds, and insulator portion, wherein the second mold forms a package body.
Features may include one or more of the following individually or in combination with other features. The input portion and the output portion of the primary conductor do not extend beyond the second mold. The at least one magnetic field sensing element is a first magnetic field sensing element disposed adjacent to a first side of the current conductor portion and the method further includes providing a second magnetic field sensing element disposed adjacent to a second side of the current conductor portion opposite to the first side. The at least one magnetic field sensing element is one of a planar Hall effect element, a vertical Hall effect element, a anisotropic magnetoresistance (AMR) element, a giant magnetoresistance (GMR) element, a tunneling magnetoresistance (TMR) element, or coil. The input portion of the primary conductor is exposed from a first side of the package body and a second side of the package body that is substantially orthogonal with respect to the first side of the package body, and wherein the output portion of the primary conductor is exposed from the second side of the package body and a third side of the package body that is substantially orthogonal with respect to the second side of the package body and opposite with respect to the first side of the package body. A distance between an exposed portion of the primary conductor and an exposed portion of the secondary leads is at least 1.0 mm. A distance between an exposed portion of the primary conductor and an exposed portion of the secondary leads is at least 7.2 mm. Providing the first and second molds are performed in a single cavity for the lead frame. The method can further include singulating the molded lead frame into individual current sensor packages.
Also described is a current sensor integrated circuit package including a primary conductor having an input portion and an output portion, wherein the primary conductor is configured to carry a current from the input portion of the primary conductor to the output portion of the primary conductor, wherein the primary conductor further comprises an exposed portion, at least two secondary leads, each having an exposed portion spaced from the exposed portion of the primary conductor by an isolation distance of at least 2.0 mm, a semiconductor die disposed adjacent to the primary conductor and positioned on an insulator portion, and at least one magnetic field sensing element supported by the semiconductor die. A package body encloses the semiconductor die and at least a portion of the primary conductor, wherein the input portion of the primary conductor is exposed from a first side of the package body and a second side of the package body that is substantially orthogonal with respect to the first side of the package body, and wherein the output portion of the primary conductor is exposed from the second side of the package body and a third side of the package body that is substantially orthogonal with respect to the second side of the package body and opposite with respect to the first side of the package body.
Features may include one or more of the following individually or in combination with other features. The primary conductor and the at least two secondary leads are partially encased by a first mold portion. An isolation distance between an exposed portion of the at least two secondary leads and an exposed portion of the primary conductor can be at least 4.0 mm. An isolation distance between an exposed portion of the at least two secondary leads and an exposed portion of the primary conductor can be at least 7.2 mm. At least one secondary lead provides an output connection, at least one secondary lead provides a voltage input connection, and at least one secondary lead provides a ground connection. The current sensor integrated circuit package can further include a front-end amplifier, wherein the at least one magnetic field sensing element is coupled to the front-end amplifier. The current sensor integrated circuit package can further include at least two magnetic field sensing elements. The at least two magnetic field sensing elements can be Hall effect elements. The at least two magnetic field sensing elements can be coupled to provide a differential output. At least one of the secondary leads can provide a fault signal. The current sensor integrated circuit package can further include a wafer backside coating material on a back side of the semiconductor die. The current sensor integrated circuit package can further include a second wafer backside coating material on the back of the semiconductor die. The exposed portion of the primary conductor can be substantially orthogonal to the first side of the package body, the second side of the package body, and the third side of the package body. The insulator portion can extend beyond an edge of the primary conductor towards the at least two secondary leads. The insulator portion can extend beyond the edge of the primary conductor towards the at least two secondary leads by at least 0.1 mm. The insulator portion can extend beyond the edge of the primary conductor towards the secondary leads by at least 0.4 mm.
The foregoing features of this disclosure, as well as the disclosure itself, may be more fully understood from the following description of the drawings in which:
As used herein, the term “magnetic field sensing element” is used to describe a variety of electronic elements that can sense a magnetic field. The magnetic field sensing element can be, but is not limited to, a Hall effect element, a magnetoresistance element, or a magnetotransistor. As is known, there are different types of Hall effect elements, for example, a planar Hall effect element, a vertical Hall effect element, and a Circular Vertical Hall (CVH) element. As is also known, there are different types of ‘magnetoresistance elements, for example, a semiconductor magnetoresistance element such as Indium Antimonide (InSb), a giant magnetoresistance (GMR) element, for example, a spin valve, an anisotropic magnetoresistance element (AMR), a tunneling magnetoresistance (TMR) element, and a magnetic tunnel junction (MTJ). The magnetic field sensing element may be a single element or, alternatively, may include two or more magnetic field sensing elements arranged in various configurations, e.g., a half-bridge or full (Wheatstone) bridge, configured for single-ended or differential sensing. Depending on the device type and other application requirements, the magnetic field sensing element may be a device made of a type IV semiconductor material such as Silicon (Si) or Germanium (Ge), or a type III-V semiconductor material like Gallium-Arsenide (GaAs) or an Indium compound, e.g., Indium-Antimonide (InSb). A coil may also be used to sense magnetic fields, which may be referred to as inductive sensing. Using a coil to sense a magnetic field is more typical as the frequency of the magnetic field to be sensed increases.
As is known, some of the above-described magnetic field sensing elements tend to have an axis of maximum sensitivity parallel to a substrate that supports the magnetic field sensing element, and others of the above-described magnetic field sensing elements tend to have an axis of maximum sensitivity perpendicular to a substrate that supports the magnetic field sensing element. In particular, planar Hall effect elements tend to have axes of sensitivity perpendicular to a substrate, while metal based or metallic magnetoresistance elements (e.g., GMR, TMR, AMR) and vertical Hall effect elements tend to have axes of sensitivity parallel to a substrate.
As used herein, the term “magnetic field sensor” is used to describe a circuit that uses a magnetic field sensing element, generally in combination with other circuits. Magnetic field sensors are used in a variety of applications, including, but not limited to, an angle sensor that senses an angle of a direction of a magnetic field, a current sensor that senses a magnetic field generated by a current carried by a current-carrying conductor, a magnetic switch that senses the proximity of a ferromagnetic object, a rotation detector that senses passing ferromagnetic articles, for example, magnetic domains of a ring magnet or a ferromagnetic target (e.g., gear teeth) where the magnetic field sensor is used in combination with a back-biased or other magnet, and a magnetic field sensor that senses a magnetic field density of a magnetic field.
The primary current conductor portion 114, or primary current path, has input and output portions that can include die attach portions 106, 108, respectively, and a current path portion 107. The primary conductor portion 114 supports an insulator, or insulator portion 104, and a semiconductor die 130. Die attach portions 106, 108 can alternatively be referred to as die attach pads or paddles. Die 130 supports at least one magnetic field sensing element, and, in an example embodiment, supports two magnetic field sensing elements 132, 134. The die 130 can also support circuitry to amplify and process signals from the magnetic field sensing elements 132, 134 and provide an output of the current sensor integrated circuit 100. As current flows through the primary conductor, a magnetic field is generated and may be sensed by magnetic field sensing elements 132, 134.
The primary conductor portion 114 includes inputs 116a, 116b, 116c on a first side of the packaged integrated circuit 100 and inputs 116d, 116e, 116f on a second side of the package. The primary conductor portion 114 further includes outputs 118a, 118b, 118c on a third side of the package and outputs 118d, 118e, 118f on the second side of the package. Inputs 116a-f are connected to die attach portion 106 and outputs 118a-f are connected to die attach portion 108. In embodiments, the input portion of the primary conductor 114 is exposed from the first side of the package body and the second side of the package body that is substantially orthogonal with respect to the first side of the package body, and the output portion of the primary conductor is exposed from the second side of the package body and the third side of the package body that is substantially orthogonal with respect to the second side of the package body and opposite with respect to the first side of the package body.
The current sensor integrated circuit 100 has secondary leads 110a, 110b, 100c, 110d, 110e, 110f, and 110g. In other embodiments, where fewer than the illustrated seven leads are required or more leads are required for providing more power, ground, output signals, a fault signal, or other input and output pins, there may be fewer or more than seven secondary leads. For example, there may be other numbers of secondary leads, such as two secondary leads, or eight secondary leads, or more than eight secondary leads. Wire bonds 126a 126b, 126c, 126d, 126e, 126f, and 126g connect the die 130 to the secondary, or signal leads, 110a, 110b, 100c, 110d, 110e, 110f, and 110g, respectively.
In an embodiment, the insulator portion 104 extends beyond an edge 109 of the die attach portions 106, 108 toward or adjacent to the secondary leads 110a, 110b, 110c, 110d, 110e, 110f, and 110g in order to provide voltage isolation where the edge of the die attach portions 106, 108 meet the lower package portion, or first mold compound portion 102. In general (although the illustrated insulator portion 104 extends beyond the die attach portion edge 109 in an example embodiment), the insulator portion 104 need only extend beyond the die 130 by at least 200 microns and preferably by 400 microns. In an embodiment, the insulator portion 104 may extend beyond the edge 109 of the die attach portions 106, 108 by at least 50 microns, and in another embodiment the insulator portion 104 extends beyond the edge 109 of the die attach portions 106, 108 by at least 375 microns. An embodiment may have the insulator portion 104 not extend beyond the edge 109 of the die attach portions 106, 108 where the other dimensions between the die attach portions and the secondary leads provide sufficient electrical isolation for the desired application.
In an embodiment, one or more secondary leads 110a, 110b, 110c, 110d, 110e, 110f, and 110g can be connected to die 130 using two or more wire bonds. This may be advantageous when a potential for higher current may exist in the operation of the integrated circuit, such as for a power or ground connection to die 130.
Referring also to
The current path portion 107 of the primary conductor 114 can interconnect die attach pads 106, 108 can be narrowed, as shown. Die attach pads 106, 108 may also act as primary current input and output portions, like a primary current lead. The primary conductor 114 has a partial current path that forms line across the package body from the first side of the package with leads 116a-c to the third side of the package with leads 118a-c. If die attach pads 106, 108 are used for primary current input and output leads or portions, then the current may not go through, or may be reduced through the side package leads 116a-f and 118a-f.
The magnetic field sensing elements 132, 134 are positioned off of or to the side of the current conductor portion 107 so that the magnetic field generated by the current flowing in the current conductor portion 107 has a direction component that is perpendicular, or in an embodiment near perpendicular (e.g., in some embodiments within +/−20 degrees of perpendicular and in other embodiments more than +/−20 degrees), to the die 130 such that planar Hall effect elements may be used for magnetic field sensing elements 132, 134. If the magnetic field sensing elements 132, 134 are Hall effect elements, one Hall effect element may be designed to have a positive voltage output when the magnetic field sensed is out of the die 130 (where for clarity “out” is the direction away from the current conductor portion 107), and the second Hall effect element may have a negative voltage when the magnetic field sensed is out of the die 130. Various processing circuitry is responsive to signals from the magnetic field sensing elements for generating an output signal indicative of the current through the current conductor portion 107. Such processing circuitry can include, but is not limited to an amplifier, and in some embodiments a differential amplifier, supported by the integrated circuit die 130 and configured to generate a signal indicative of the difference between the two Hall effect element output voltages. Using the difference between the two magnetic field sensing element output voltages when they are Hall effect elements allows for the integrated circuit to reduce or eliminate the effects of external magnetic fields that are not a result of current through the primary current path, including the current conductor portion 107 (i.e., stray magnetic fields). In other embodiments, the magnetic field sensing elements, or a magnetic field element may be positioned on die 130 over the primary current conductor portion 107 to sense a magnetic field with a component parallel to the surface of die 130. In a case where the magnetic field component to be sensed is parallel to the surface of the die 130, a vertical Hall effect element or a magnetoresistance element such as a GMR, TMR, or AMR element may be used.
Referring also to
The lower package body 102 and secondary leads 110a-110g may have cutouts or recessed portions 113, which in an embodiment may be around all the bottom edges of the packaged current sensor integrated circuit 100. This recessed portion 113 can be used when the packaged current sensor integrated circuit 100 is assembled to a printed circuit board or other assembly to inspect or check for solder connections between the package 100 and the PC Board or assembly.
Die 130 is supported by one or both of the primary conductor die attach portions 106, 108. Die 130 may be attached to the insulator portion 104 by a non-conductive coating (not shown), such as a wafer backside coating (WBC) or a non-conductive epoxy and the insulator portion 104 is attached to die attach portions 106, 108. Alternatively, the die 130 can be attached to the insulator portion 104 by a conductive material as may reduce the effects of partial discharge from voids in the die attach material. Die 130 may be attached to die attach portions 106, 108 by insulator portion 104 where the insulator is a dielectric tape, for example a Kapton® or other insulating tape with a layer of adhesive on one side of the tape or on each side of the dielectric tape layer. In another embodiment, an epoxy die attach material a die-attach film (DAF), or an insulating coating material may be applied as the insulator portion 104 in place of the tape. Aspects of insulator portion 104 can be the same as or similar to insulation structures described in U.S. Pat. No. 10,753,963, issued on Aug. 25, 2020, entitled “Current Sensor Isolation” and hereby incorporated herein by reference in its entirety.
In manufacturing, if two layers of wafer backside coating are used, a first wafer backside coating layer 105 may be fully cured (or partially cured if only one layer of a wafer backside coating is used) before a second layer of wafer backside coating is partially cured (also known as B stage cured) is used to eventually attach die 130 to insulator portion 104.
In another embodiment, the die 130 may be attached to the insulator portion 104 by other materials, including but not limited to a non-conductive die attach epoxy, or a tape. Multiple layers of wafer backside coating, tape, DAF and non-conductive epoxy may be used for electrical isolation. A combination of wafer backside coating, tape, DAF, or non-conductive epoxy may be used to achieve electrical isolation and attachment to the die attach portion 106, 108.
Die 130 can be electrically connected to secondary lead 110c with a wire bond 126c. Secondary leads 110a-110g, as illustrated in
Creepage refers to the shortest distance between primary and secondary conductors along a surface of any insulation material common to both parts, such as the surface of the lower package body 102 outside of the package. In
Clearance refers to the shortest distance between conductors of differing voltage levels, such as between primary and secondary conductors, through an insulating material, such as air outside of the package or through an insulating material inside or outside the package.
Increased clearance distance in the described embodiments can be facilitated by the insulator portion 104 extending beyond edge 109 of the primary conductor 114 since such extended portion increases the clearance distance between the lower voltage level semiconductor die 130 and the higher voltage primary conductor 114.
The insulator portion 104 can provide a second layer of isolation between the primary conductor 114 and wire bonds 126a-g and secondary leads 110a-g, which allows a thinner package than if a 0.4 mm distance were required. It will be appreciated that the isolation distances can be readily varied by stretching or shortening the length of the enclosed portion of the secondary leads in order to achieve a desired isolation voltage.
As noted above, the insulator portion 104 can extend beyond the edge 109 of the primary conductor 114 in the direction of, or from the side of the primary conductor towards, the secondary leads 110a-g. For example, in embodiments, the insulator portion 104 may extend beyond the edge 109 of the primary conductor 114 in the direction of the secondary leads 110a-g by at least 0.1 mm, 0.2 mm, or 0.4 mm depending on the voltage isolation requirements.
Referring to
In embodiments, lead frame 200 can be stamped from a copper sheet and can be relatively thick (e.g., at least 15 mils thick) in order to support high current (e.g., 200 amps) applications. Alternatively, lead frame 200 can include interconnected metal layers as may be part of a so-called molded interconnect substrate (MIS) that includes a pre-molded structure with one or more layers, with each layer is configured with plating or interconnects to provide electrical connections in the package. In this scenario, stage 330 in the process described below in connection with
Referring also to
Referring also to
Referring also to
In stage 330, the first mold (e.g., first mold 102 or 202) is performed with an insulating mold material including but not limited to an epoxy mold compound. The result of stage 330 is the pre-molded lead frame subassembly shown in
At stage 340, an insulation layer, that may be the same as or similar to insulator portions 104, 204, 205, is applied. The insulation may comprise one or more of a dielectric tape, an insulating epoxy material, or a piece of insulating material including but not limited to alumina or glass substrate material.
At stage 350, an integrated circuit die, as may be the same as or similar to die 130, 230, is attached to the subassembly. Attachment of the die can include, but is not limited to, use of a wafer backside coating material, a tape attachment material, and/or an insulating epoxy material, which may also be referred to as a non-conductive epoxy material. In an embodiment, the first insulator layer step 340 and the die attach step 350 may both utilize wafer backside coating layers, where the first wafer backside coating material is applied to the integrated circuit die, or die, and this first layer is fully cured and then the second wafer backside material is partially cured before attachment to the molded lead frame subassembly.
The integrated circuit die is electrically connected to the signal leads in stage 360. Other electrical connections, including flip-chip assembly methods, may be be used provided they meet the isolation requirements of the package.
At stage 370, a second mold material (as may be the same as or similar to mold material 103, 203), or other final package material, is applied to the subassembly including the lead frame, integrated circuit die, and wire bonds.
Advantageously, in the case of the illustrated molded leadless package (MLP) embodiments of this disclosure, many integrated circuit packages can be molded at the same time in a single mold cavity, or in a number of cavities less than one per final package, in order to increase the number of molded packages per mold shot. This fabrication technique is in contrast to processes in which every integrated circuit is individually molded, thereby resulting in higher cost and reduced density of units per mold shot.
After the mold process of stage 370, the packages are cut, or singulated, with a process such as a saw, or laser cutter, to form a single integrated circuit package. Because multiple units are molded in a single cavity, singulation results in the above-described configuration in which the primary conductor does not extend beyond the molds. At stage 380, the integrated circuit package is complete.
Other steps may follow manufacturing, which include, but are not limited to a final test procedure, or programming the integrated circuit package. In the case of a current sensor integrated circuit package there may be a test step and may be programming of the integrated circuit die at the integrated circuit package level, and then a second test and programming may be performed, for example, when the current sensor integrated circuit package is applied to a printed circuit board or other assembly where the current sensor integrated circuit package is used. This second programming after assembly of the current sensor integrated circuit package onto a PC board or other assembly, allows a more accurate measurement of the current to be made as other influences such as PC board currents can be accounted for in the current sensor integrated circuit.
It is understood that any of the above-described processing may be implemented in hardware, firmware, software, or a combination thereof. Processing may be implemented in computer programs executed on programmable computers/machines that each includes a processor, a storage medium or other article of manufacture that is readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. Program code may be applied to data entered using an input device to perform processing and to generate output information.
Having described exemplary embodiments of the disclosure, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. The embodiments contained herein should not be limited to disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.
Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
This application is a continuation-in-part of and claims priority to and the benefit of U.S. patent application Ser. No. 17/654,254, entitled “Packaged Current Sensor Integrated Circuit” and filed on Mar. 10, 2022, which is a continuation-in-part of and claims priority to and the benefit of U.S. patent application Ser. No. 17/409,011, entitled “Packaged Current Sensor Integrated Circuit” and filed Aug. 23, 2021, the entirety of which are hereby incorporated herein by reference in their entireties.
Number | Name | Date | Kind |
---|---|---|---|
5255157 | Hegel | Oct 1993 | A |
5557504 | Siegel et al. | Sep 1996 | A |
5570273 | Siegel et al. | Oct 1996 | A |
6211462 | Carter, Jr. et al. | Apr 2001 | B1 |
6326243 | Suzuya et al. | Dec 2001 | B1 |
6356068 | Steiner et al. | Mar 2002 | B1 |
6781359 | Stauth et al. | Aug 2004 | B2 |
6995315 | Sharma et al. | Feb 2006 | B2 |
7005754 | Howarth | Feb 2006 | B2 |
7075287 | Mangtani et al. | Jul 2006 | B1 |
7166807 | Gagnon et al. | Jan 2007 | B2 |
7265531 | Stauth et al. | Sep 2007 | B2 |
7372147 | Dai et al. | May 2008 | B2 |
7476816 | Doogue et al. | Jan 2009 | B2 |
7554180 | McKerreghan et al. | Jun 2009 | B2 |
7598601 | Taylor et al. | Oct 2009 | B2 |
7709754 | Doogue et al. | May 2010 | B2 |
7816905 | Doogue et al. | Oct 2010 | B2 |
8080994 | Taylor et al. | Dec 2011 | B2 |
8604777 | Doogue et al. | Dec 2013 | B2 |
8629539 | Milano et al. | Jan 2014 | B2 |
8907437 | Milano et al. | Dec 2014 | B2 |
9190606 | Liu et al. | Nov 2015 | B2 |
9299915 | Milano et al. | Mar 2016 | B2 |
9383425 | Milano et al. | Jul 2016 | B2 |
9494660 | David et al. | Nov 2016 | B2 |
9620705 | Milano et al. | Apr 2017 | B2 |
9666788 | Taylor et al. | May 2017 | B2 |
9788403 | Mrusek | Oct 2017 | B2 |
9812588 | Vig et al. | Nov 2017 | B2 |
9865807 | Liu et al. | Jan 2018 | B2 |
10230006 | Vig et al. | Mar 2019 | B2 |
10234513 | Vig et al. | Mar 2019 | B2 |
10333055 | Milano et al. | Jun 2019 | B2 |
10345343 | Milano et al. | Jul 2019 | B2 |
10509058 | Cadugan et al. | Dec 2019 | B2 |
10578684 | Cadugan et al. | Mar 2020 | B2 |
10718794 | El Bacha et al. | Jul 2020 | B2 |
10753963 | Milano et al. | Aug 2020 | B2 |
10916665 | Vig et al. | Feb 2021 | B2 |
11024576 | West et al. | Jun 2021 | B1 |
11085952 | Cadugan et al. | Aug 2021 | B2 |
11519946 | Rock | Dec 2022 | B1 |
11768229 | Boden | Sep 2023 | B2 |
20020190703 | Goto et al. | Dec 2002 | A1 |
20030193018 | Tao et al. | Oct 2003 | A1 |
20040124505 | Mahle et al. | Jul 2004 | A1 |
20050030018 | Shibahara et al. | Feb 2005 | A1 |
20050124185 | Cromwell et al. | Jun 2005 | A1 |
20070126092 | San Antonio et al. | Jun 2007 | A1 |
20070279053 | Taylor et al. | Dec 2007 | A1 |
20080297138 | Taylor et al. | Dec 2008 | A1 |
20100156394 | Ausserlechner et al. | Jun 2010 | A1 |
20110049685 | Park et al. | Mar 2011 | A1 |
20110234215 | Ausserlechner | Sep 2011 | A1 |
20110248711 | Ausserlechner | Oct 2011 | A1 |
20120089266 | Tomimbang et al. | Apr 2012 | A1 |
20130015843 | Doogue et al. | Jan 2013 | A1 |
20130020660 | Milano et al. | Jan 2013 | A1 |
20130138372 | Ausserlechner | May 2013 | A1 |
20140253103 | Racz et al. | Sep 2014 | A1 |
20140264678 | Liu et al. | Sep 2014 | A1 |
20140266181 | Milano et al. | Sep 2014 | A1 |
20150108967 | Barczyk | Apr 2015 | A1 |
20150270198 | Cuoco et al. | Sep 2015 | A1 |
20160187388 | Suzuki et al. | Jun 2016 | A1 |
20160216296 | Nakayama et al. | Jul 2016 | A1 |
20160223594 | Suzuki et al. | Aug 2016 | A1 |
20160282388 | Milano et al. | Sep 2016 | A1 |
20160282425 | Haas et al. | Sep 2016 | A1 |
20160313375 | Etschmaier | Oct 2016 | A1 |
20170179067 | Aoki et al. | Jun 2017 | A1 |
20170336481 | Latham et al. | Nov 2017 | A1 |
20180149677 | Milano et al. | May 2018 | A1 |
20180166350 | Racz et al. | Jun 2018 | A1 |
20180306843 | Bussing et al. | Oct 2018 | A1 |
20190049527 | Vig et al. | Feb 2019 | A1 |
20190109072 | David et al. | Apr 2019 | A1 |
20190154737 | Nobira | May 2019 | A1 |
20190204363 | Suzuki et al. | Jul 2019 | A1 |
20190369144 | Mauder et al. | Dec 2019 | A1 |
20200033384 | Kishi et al. | Jan 2020 | A1 |
20200064382 | Takata et al. | Feb 2020 | A1 |
20200191835 | Bilbao de Mendizabal et al. | Jun 2020 | A1 |
20210082789 | Briano et al. | Mar 2021 | A1 |
20210111284 | Vig et al. | Apr 2021 | A1 |
20210243911 | Tang et al. | Aug 2021 | A1 |
20210263077 | Hirano et al. | Aug 2021 | A1 |
20210397015 | Moon | Dec 2021 | A1 |
20220018880 | Houis | Jan 2022 | A1 |
Number | Date | Country |
---|---|---|
3671228 | Jun 2020 | EP |
4141451 | Mar 2023 | EP |
3090121 | Jun 2020 | FR |
Entry |
---|
U.S. Appl. No. 18/182,434, filed Mar. 13, 2023, Liu. |
Office Action dated Mar. 15, 2023 for U.S. Appl. No. 17/654,254, 19 pages. |
Response to Office Action dated Mar. 15, 2023 filed on Mar. 22, 2023 for U.S. Appl. No. 17/654,254, 10 pages. |
Steve Bush, DNP claims world's thinnest chip package, https://www.electronicsweekly.com/news/products/micros/ dnp-claims-worlds-thinnest-chip-package-2009-03/ (Year: 2009). |
U.S. Appl. No. 17/657,135, filed Mar. 30, 2022, Liu, et al. |
U.S. Appl. No. 17/817,796, filed Aug. 5, 2022, Briano, et al. |
Notice of Allowance dated Aug. 9, 2023 for U.S. Appl. No. 17/654,254; 5 pages. |
U.S. Appl. No. 17/654,254, filed Mar. 10, 2022, Boden, et al. |
U.S. Notice of Allowance dated Aug. 23, 2022 for U.S. Appl. No. 17/409,011; 10 pages. |
European Extended Search Reporting dated Dec. 22, 2022 for European Application No. 22183450.0; 7 pages. |
U.S. Appl. No. 18/490,815, filed Oct. 20, 2023, Briano, et al. |
Response to European Examination Report dated Aug. 28, 2023 for European Application No. 22183450.0 as filed on Oct. 30, 2023; 18 pages. |
Office Action dated May 19, 2023 for U.S. Appl. No. 17/654,254; 15 pages. |
Response to Office Action dated May 19, 2023 filed on May 25, 2023 for U.S. Appl. No. 17/654,254; 9 pages. |
Search Report and Written Opinion dated Apr. 25, 2023 for PCT Application No. PCT/US2022/051968; 16 pages. |
European Examination Report dated Aug. 28, 2023 for European Application No. 22183450.0, 4 pages. |
European Response filed on Jun. 14, 2023 for European Application No. 22183450.0; 24 pages. |
Number | Date | Country | |
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20230060219 A1 | Mar 2023 | US |
Number | Date | Country | |
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Parent | 17654254 | Mar 2022 | US |
Child | 18053480 | US | |
Parent | 17409011 | Aug 2021 | US |
Child | 17654254 | US |