Patent Application
20160229689
The disclosure generally relates to microchips and, more particularly, the disclosure relates to packaging techniques for microchips.
Microelectromechanical systems (“MEMS”) are used in a growing number of applications. For example, MEMS currently are implemented as gyroscopes to detect pitch angles of airplanes, and as accelerometers to selectively deploy air bags in automobiles. In simplified terms, such MEMS devices typically have a structure suspended above a substrate, and associated electronics that both senses movement of the suspended structure and delivers the sensed movement data to one or more external devices (e.g., an external computer). The external device processes the sensed data to calculate the property being measured (e.g., pitch angle or acceleration).
The associated electronics, substrate, and movable structure typically are formed on one or more dies (referred to herein simply as a “die”) that are secured within a package. For example, the package, which typically protects the die, may be produced from any number of materials, such as ceramic or plastic. The package includes interconnects that permit the electronics to transmit the movement data to the external devices. To secure the die to the package interior, the bottom surface of the die commonly is bonded (e.g., with an adhesive or solder) to an internal surface of the package. Accordingly, substantially all of the area of the bottom die surface is bonded to the internal surface the package.
Problems can arise, however, when the temperatures of the two surfaces change. In particular, because both surfaces typically have different coefficients of thermal expansion, the package can apply a mechanical stress to the substrate of the die. This stress undesirably can bend or flex the substrate to an unknown curvature. Substrate bending or flexing consequently can affect movement of the die structures and the functioning of the electronics, thus causing the output data representing the property being measured (e.g., acceleration) to be erroneous. In a similar manner, mechanically induced linear or torsional stress applied to the package also can be translated to the die, thus causing the same undesirable effects.
SUMMARY OF VARIOUS EMBODIMENTS
In accordance with one embodiment of the invention, a packaged microchip has a base, a die with a mounting surface, and an electrically inactive interposer between the base and the die. The interposer has a first side with at least one recess that extends no more than part-way through the interposer from the first side. Accordingly, the recess defines a top portion (of the first side) with a top area. The die mounting surface, which is coupled with the interposer, correspondingly has a die area. The top area of the interposer preferably is less than the die area.
The top surface of the interposer can be mounted to either the die or the base. To that end, the mounting surface of the die may couple with the first side of the interposer. Alternatively, the first side of the interposer may couple with the base. Moreover, adhesive may couple the interposer to the base and/or the die. For example, adhesive may be within the at least one recess to connect the interposer to the base or the die. In this case, at least a part of the top portion of the interposer may directly contact the base or the die mounting surface (i.e., substantially no adhesive between that portion and the surface it directly contacts). As another example, a very thin adhesive film may be positioned on the top portion of the interposer. In that latter case, the adhesive film connects the interposer to the base or the die.
As an electrically inactive element, the interposer is configured not to electrically connect the die and the base. In addition, the die can implement any of a variety of types of dice. For example, the MEMS may include MEMS microstructure protected by a lid coupled with the base.
To further mitigate the adverse effects of stress, the top area may be less than half of the die area. The coefficients of thermal expansion (“CTE”) of the elements of the packaged microchip also may be selected to further mitigate stress. As such, the die may have a die CTE that is substantially equal to the interposer CTE. In related embodiments, the interposer CTE may be between the die CTE and base CTE.
In accordance with another embodiment, a method of forming a packaged microchip couples an electrically inactive interposer between a base and a die. The interposer has a first side with at least one recess that defines a top portion with a top area. The at least one recess extends no more than part-way through the interposer from the first side. The die has a mounting surface, coupled with the interposer, having a die area. The top area of the interposer is less than the die area.
Those skilled in the art should more fully appreciate advantages of various embodiments of the invention from the following “Description of Illustrative Embodiments,” discussed with reference to the drawings summarized immediately below.
In illustrative embodiments, a packaged microchip has an intermediate structure positioned between its die and package base to mitigate and/or redirect undesirable stress transmitted to the die from the base. To that end, the intermediate structure has one or more faces formed with recessed surfaces. Details of illustrative embodiments are discussed below.
The components 12A, 12B, and 14 shown include a first packaged microchip 12A surface mounted to the printed circuit board 10, a second packaged microchip 12B, and other active or passive circuit components (generally identified by reference number “14”). Among other things, the first and second packaged microchips 12A and 12B each may include one or more MEMS dice (see subsequent figures) having microstructure integrally formed with the substrate, and circuitry that cooperates with the microstructure. In illustrative embodiments, the integral structure is formed using conventional micromachining processes, which use additive and/or subtractive processes to form a generally monolithic die/substrate.
Among other things, the first packaged microchip 12A may be an inertial sensor, such as a MEMS accelerometer or MEMS gyroscope, a MEMS optical switch, or a MEMS electrostatic switch. Exemplary MEMS gyroscopes are discussed in greater detail in U.S. Pat. No. 6,505,511, which is assigned to Analog Devices, Inc. of Norwood, Mass. Exemplary MEMS accelerometers are discussed in greater detail in U.S. Pat. No. 5,939,633, which also is assigned to Analog Devices, Inc. of Norwood, Mass. The disclosures of U.S. Pat. Nos. 5,939,633 and 6,505,511 are incorporated herein, in their entireties, by reference.
The second packaged microchip 12B may include functionality that requires access to the ambient environment, but still requires some environmental protection. For example, the second packaged microchip 12B may include a microphone or pressure sensor. As noted, one or both of the devices 12A and 12B may include circuitry, such as that included in IMEMS devices distributed by Analog Devices, Inc.
Unlike the first packaged microchip 12A, the second packaged microchip 12B has pins to electrically connect to the printed circuit board 10. Either type of electrical interconnect method should suffice for various embodiments. In illustrative embodiments, each package is formed from a base 18 and lid 20 that together form a package chamber for securing the microchip. In the example of a MEMS die, the package chamber may contain the MEMS die alone, or with additional circuitry, such as an application specific integrated circuit.
Some embodiments may omit the lid 20 entirely. In such embodiments, the cap 24 alone may provide appropriate environmental protection for the die 16.
The MEMS die 16 may be formed using any of a variety of materials. For example, the MEMS die 16 may implement an accelerometer having a conventional single crystal silicon substrate supporting fragile and highly sensitive microstructure. Illustrative embodiments bond the cap 24 to the substrate to form an interior die chamber that hermetically seals and protects the fragile microstructure. The interior chamber also may include a seal gas to buffer the microstructure, or form a vacuum. Other embodiments do not cap the substrate and thus, rely on the larger package to protect the MEMS microstructure. In those embodiments, the package chamber may contain the seal gas, if seal gas is used.
To mitigate stress caused by thermal changes, illustrative embodiments form the interposer 22 from a material having a coefficient of thermal expansion (“CTE”) that is the same as, or very close to, that of silicon. Accordingly, the interposer 22 preferably may be formed from silicon. For example, the interposer 22 may be formed from a single crystal bulk silicon wafer that is patterned and diced to form the interposer 22. Other embodiments may form the interposer 22 from a material having a comparable CTE to that of silicon. For example, the interposer 22 may be formed from a ceramic material having a CTE similar to that of silicon. The interposer 22 also may be formed from a material having the CTE of the base 18 and/or the die 16 if those components 12 and 16 are not formed from silicon, or another material having a CTE similar to that of silicon.
Other embodiments may form the interposer 22 from a material with a CTE (or from a plurality of materials with a collective CTE) that is different from that of the base 18 and/or the die 16. For example, the interposer 22 may have a CTE that is between the CTEs of the base 18 and the die 16. In the case of a silicon-based die 16, the material would have a different CTE than that of silicon. In some embodiments, the interposer 22 also is formed from a material with a lower Young's Modulus, which should help reduce stress transfer from the base 18 toward the die 16.
Like the die 16, the base 18 may be formed from any of a variety of materials. For example, the base 18 may be formed from a printed circuit board material (e.g., FR-4), ceramic, an application specific integrated circuit (“ASIC”), or a lead frame (e.g., a premolded lead frame). Together with other components, such as the lid 20, the base 18 preferably forms a cavity package that protects the MEMS die 16 from the environment.
The recesses 26 have the effect of reducing the contact area between the interposer 22 and the surface to which it is attached (e.g., the die bottom surface of the first packaged microchip 12A). This reduced contact area mitigates stress transmission between the base 18 and the die 16, effectively improving performance.
In this embodiment of
Rather than contacting the die with the interposer surface having recesses, some embodiments orient the interposer 22 so that the upper surface of the embodiment of
To that end,
It should be noted that features of
As noted above, changing temperatures or torsional stress can cause the base 18 to transmit stress toward the MEMS die 16. Illustrative embodiments mitigate the impact of that stress by specially configuring the interposer 22 with the recesses 26, which are configured to redirect and/or mitigate transmission of the stress from the base 18 to the substrate of the MEMS die 16.
To that end, the top surface of the interposer 22 has some prescribed recess pattern that controls stress transmission from the base 18 to the substrate of the MEMS die 16. This pattern preferably is designed based on the features of the die 16. For example, if the die 16 has MEMS microstructure with high stress-sensitive regions (e.g., regions with anchors), then the pattern may direct stress away from these high stress-sensitive regions. Some embodiments may simply direct the stress to a region of the die 16 that can handle the stress, toward the edge of the die 16, and/or away from the edge of the die 16.
Those skilled in the art would consider preferred embodiments of the interposer 22 to be electrically inactive. Specifically, the interposer 22 has a main body with no added circuitry, including active and passive circuit elements, vias, or traces, that are operating (i.e., not transmitting charge) during use of the first packaged microchip 12A. For example, although the interposer body itself may be formed from a conductive material, such an interposer body has no circuits that electrically interact with circuitry on the die 16 during use, and/or it does not electrically connect the die 16 to the base 18. In fact, illustrative embodiments of the interposer 22 are configured not to electrically connect the die 16 with the base 18. Instead, other components may electrically connect the die 16 with the base 18 (not through the interposer 22), if necessary. For example, wirebonds may extend from die pads to pads on the base 18. Thus, the body itself may be conductive, and still be electrically inactive. Such an interposer 22 does not electrically interact with circuitry on the die 16 (acting as ground is not considered electrically interacting with circuitry in these embodiments) and does not connect the die 16 with the base 18.
The specific pattern of
As shown and noted above, the patterned surface is considered to form a recessed region, and an elevated region (the prior noted upper surface). The recessed region may be discontinuous or continuous. This is exemplified by the pattern of
Those skilled in the art can select an appropriate shape, width, length, and depth for the recessed region. For example, one of the recesses 26 may have a depth from the top of the elevated region to its bottom of between 25 and 50 percent of the largest thickness of the interposer 22 itself. The recess widths can be relatively wide, such as on the order of 5-15 percent of the total interposer 22 width. Various dimensions are in the figures as examples. Those dimensions, however, are not intended to limit various embodiments.
Some embodiments, however, may extend the recesses 26 deeper, such as 50 percent, 60 percent, 70 percent, or 80 percent of the total thickness. Other embodiments may extend some of the recesses all the way though the interposer 22, although such embodiments are not as easy to handle as the partial thickness embodiments and thus, are less desirable. In yet other embodiments, a single recess 26 may have a varying depth (e.g., an irregular or concave bottom surface), or different recesses 26 of the same interposer 22 may have different depths. The recesses 26 can take on a variety of shapes and sizes. For example, the recesses 26 can at least in part be in the form of a trench, channel, groove, rounded dimple, etc.
Although the many examples noted above have substantially symmetrical patterns, those skilled in the art can use any of a variety of different patterns that are not symmetrical. Accordingly, discussion of any of the patterns noted above is for exemplary purposes only and not intended to limit various embodiments of the invention.
The interposers 22 discussed above are considered to have two levels; namely, an elevated region (e.g., the noted upper surface) and a recessed region. Some embodiments of the interposer 22 may have more than these two levels. For example, some embodiments may have three or more levels.
The recesses 26 may be formed by any of a wide variety of conventional techniques known in the art. For example, the recesses 26 may be etched, patterned, or otherwise cut into a flat surface of a material, such as a bulk silicon wafer. Alternatively, the recesses 26 may be formed by additive processes that add the elevated region to a generally flat surface of a material, such as a bulk silicon wafer.
Some embodiments position adhesive within the recesses 26 to secure the stack of components together (the adhesive is not shown in the figures to better show other components). In such case, the upper surface preferably is substantially free of adhesive. During assembly of the first packaged microchip 12A, some adhesive may seep onto the upper surface. In such case, at least a portion of the upper surface is substantially free of adhesive. Some implementations may apply a surface treatment to the surface of the upper surface to prevent adhesive from forming on such surface. In these and related embodiments, at least a portion of the upper surface may directly abut or contact the die 16 or base 18, whichever the case may be. In other words, no more than a negligible amount of other material (e.g., adhesive) may separate the upper surface from its corresponding surface on the base 18/die 16. This should assist in leveling the die 16 relative to the upper surface of the interposer 22.
Other embodiments may apply an adhesive to the upper surface only and thus, leave the regions within the recesses 26 substantially free of adhesive. For example, such embodiments may use a thin adhesive film (e.g., a material substrate having an integrated adhesive). As an adhesive film, its application should be substantially uniform, enabling the die 16 to be substantially level.
Either way of applying adhesive should substantially mitigate stress transmission. Some embodiments, however, may apply adhesive to both the recess 26 and the upper surface.
Those skilled in the art can use conventional assembly processes to secure the components together to form the ultimate packaged microchip.
Moreover, as noted above and below, many of the materials and structures noted are but one of a wide variety of different materials and structures that may be used. Those skilled in the art can select the appropriate materials and structures depending upon the application and other constraints. Accordingly, discussion of specific materials and structures is not intended to limit all embodiments.
The process of
The process begins at step 1300, which attaches the interposer 22 to the base 18. As noted, the process either attaches the upper surface of the interposer 22 to the base 18, or to the bottom surface of the die 16. In this example, the process does not attach the upper surface of the interposer 22 to the base 18. Thus, the process applies an adhesive (e.g., an epoxy) to the bottom, unpatterned surface of the interposer 22, and secures it to the base 18.
After the interposer 22 is in place on the base 18, the process continues to step 1302 by applying adhesive to the appropriate side of the interposer 22—in this case, the top side from the perspective of the drawings. As noted above, the adhesive may be applied to the recesses 26 only using precise adhesive application processes, or to the upper surface with an adhesive or adhesive film. Conventional pick-an-place processes then may place the die 16 on the adhesive (step 1304), and secure the lid 20 to the base 18 (step 1306) as further protection for the first packaged microchip 12A.
Accordingly, the interposer 22 substantially mitigates and/or redirects stress from the base 18, consequently improving device performance.
Although the above discussion discloses various exemplary embodiments of the invention, it should be apparent that those skilled in the art can make various modifications that will achieve some of the advantages of the invention without departing from the true scope of the invention.
This patent application claims priority from Provisional U.S. Patent Application No. 62/114,741, filed Feb. 11, 2015, entitled, “MEMS DEVICE WITH PATTERNED INTERPOSER,” and naming Bradley C. Kaanta, John A. Alberghini, and Kemiao Jia as inventors, the disclosure of which is incorporated herein, in its entirety, by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62114741 | Feb 2015 | US |
