Patent Application
20140264266
The present invention relates to field of semiconductor technology, and more particularly, to a light emitting diode packaging structure manufactured by means of wafer level in-situ package technology and a method of manufacturing the same.
The conventional process for manufacturing a light emitting diode (LED) generally consists of three main steps including material epitaxy, chip technology and chip package. The basic function of semiconductor device package is to connect a chip electrode of a microsize chip to a relative big electrode structure so as to obtain facility for usage.
The packaging process for manufacturing a light emitting diode generally involves using a type of substrate or package or lead frame, bonding the light emitting diode chip on the substrate or package or lead frame in one way, and then connecting an electrode on the upper portion of the chip to a corresponding electrode of the substrate or package or lead frame by a ball bonding, so as to achieve electrical connection. Finally, a transparent package material is applied to the substrate or package or lead frame to finish an encapsulation or coverage in certain way, in which the transparent material is sometime formed to a certain shape in the macroscopic level to improve light extraction efficiency. Alternatively, a corresponding fluorescent material may be used for packaging or covering the chip, to achieve a certain application. As for this aspect, various package types and special functions thereof are respectively described in patents NO. US2010267174A1, US2005151142A1, CN201081157Y, CN201074776Y, US2008089064A1, CN201074776Y, CN101222012A, CN101409266A, CN10137137B, CN101060116B and EP2270889A2. As the development of the semiconductor technology, the proportion of material epitaxy and chip technology in cost to all the manufacture process of the light emitting diode decreases while the expense of package step is hard to be minished due to material expense, relative more steps and lower technological level. Therefore, it tends to develop integration and miniaturization of light emitting diode device.
Currently, some wafer level packaging methods of light emitting diode device are disclosed to use a type of wafer (e.g., silicon wafer, ceramic plate, etc.) for substrate supporting the light emitting diode, such as, a packaging pattern of light emitting diode on an AlN substrate, originated from VisEra Technoloty. A type of chip scale packaging of light emitting diode (e.g., ZL200610108560.4 filed by Advanced Semiconductor Engineering Incorporated, and US20100163907A1 filed by China's Taiwan crystal aureole electric Co. LTD) is also disclosed. However, the disclosed methods of packaging still troublesomely involve times of transfer of a wafer or a plurality of wafers and thus relative material expense and many process steps. The current most of light emitting diodes are packaged by the methods mentioned above.
To solve the problems in the art, a light emitting diode packaging structure and method of manufacturing the same are provided in the present disclosure.
It is objective of the present application to provide a light emitting diode packaging structure, formed by integrating the chip technology and chip packaging process of light emitting diode and using the own substrate of the chip as a packaging substrate, from which simplified process path, decreased entire process cost, a smallest packaging volume, decreased package thermal resistance for the light emitting diode packaging structure can be achieved, thereby enabling improvement in controlling the electrical and optical properties of the light emitting diode. The light emitting diode packaging structure further has advantages of simpler structure and lower cost. It is also disclosed a method of manufacturing the light emitting diode packaging structure.
According to the present invention, there is provided a light emitting diode packaging structure, comprising:
an insulating substrate with through holes formed on each side of the upper surface of the insulating substrate, the through hole being filling with conductive metal;
a n-type layer formed on the insulating substrate and configured to cover most of area of an upper surface of the insulating substrate such that is formed a mesa at one side of the insulating substrate while a hole is formed on the other side in the n-type layer with relative to the mesa, which is fit for the through hole in the insulating substrate and filled with conductive metal;
an active layer provided on and at one side of the n-type layer, the area of the active layer being smaller than that of the n-type layer;
a p-type layer provided on the active layer;
an insulating layer configured on one side the n-type layer, the active layer and the p-type layer and to cover part of the upper surface of the p-type layer;
a p-type electrode configured to cover the insulating layer and part of the upper surface of the p-type layer, the p-type electrode being connected with the conductive metal in the through hole in the insulating substrate; a n-type electrode provided on a side of the upper surface of the n-type layer and configured to connect with the conductive metal in the through hole in the insulating substrate;
a first back electrode provided at one side of back surface of the insulating substrate, the first back electrode connecting with the p-type electrode through the conductive metal in the through hole in the insulating substrate;
a second back electrode provided at the other side of back surface of the insulating substrate with relative to the first back electrode, the second back electrode connecting with the n-type electrode through the conductive metal in the through hole in the insulating substrate, thereby the above portions/parts forming the base substrate of a device;
an optical element packaged on the base substrate, forming the whole device.
According to one aspect of the present application, the material of the insulating substrate is selected from the group consisting of: sapphire or silicon carbide or aluminum nitride.
According to one aspect of the present application, the material of the n-type layer is n-type gallium nitride (GaN).
According to one aspect of the present application, the active layer includes a quantum well structure made of gallium nitride material.
According to one aspect of the present application, the material of p-type layer is p-type gallium nitride.
According to one aspect of the present application, the material of insulating layer is silicon oxide or silicon nitride.
According to one aspect of the present application, the p-type electrode, the n-type electrode, the first back electrode and the second back electrode are made of conductive metal.
According to one aspect of the present application, the optical element is made of resin, or silica gel, or glass, or the combination thereof.
According to the present application, it is provided to a method of manufacturing a light emitting diode packaging structure, comprising:
1) growing a n-type layer, an active layer and a p-type layer in turn on an insulating substrate by means of metal organic vapour phase epitaxy, forming an epitaxy layer;
2) performing a down etching at one side on the surface of the p-type layer by means of lithographic process with an etching depth so as to reach the surface of the n-type layer to form a first mesa, and performing a down etching at other side on the surface of the p-type layer with an etching depth so as to reach the surface of the insulating substrate to form a second mesa;
3) forming a conductive through hole in the first mesa and the second mesa, which are filled with a conductive metal;
4) providing an insulating layer at the side of the epitaxy layer close to the second mesa, which covers part of the upper surface of p-type layer;
5) providing a p-type electrode on the insulating layer and covering it, the p-type electrode covering part of p-type layer and connecting with the conductive metal in the conductive through hole;
6) fabricating a n-type electrode on the conductive through hole in the first mesa, the n-type electrode connecting with the conductive metal in the conductive through hole;
7) thinning the insulating substrate;
8) fabricating a first back electrode and a second back electrode on each side of the back face of the thinned insulating substrate, respectively, wherein, the first back electrode and the second back electrode are connected with the p-type electrode and n-type electrode through the conductive metal in the conductive through holes, respectively, thereby obtaining a base substrate of a device;
9) packaging an optical element on the base substrate of the device, finishing the device on the base substrate;
10) cutting the device on the base substrate into a separating device by mechanical method.
According to one aspect of the present application, the n-type layer and the p-type layer in the epitaxy structure are placed in positive or reverse order.
According to one aspect of the present application, the material of insulating substrate is selected from the group consisting of: sapphire or silicon carbide or aluminum nitride.
According to one aspect of the present application, the material of the n-type layer is n-type gallium nitride (GaN).
According to one aspect of the present application, the active layer includes a quantum well structure made of gallium nitride material.
According to one aspect of the present application, the material of p-type layer is p-type gallium nitride.
According to one aspect of the present application, the material of insulating layer is silicon oxide or silicon nitride.
According to one aspect of the present application, the p-type electrode, the n-type electrode, the first back electrode and the second back electrode are made of conductive metal.
According to one aspect of the present application, the optical element is made of resin, or silica gel, or glass, or the combination thereof.
The above and other objects, features and advantages of the present disclosure will be clearer from the following detailed description about the non-limited embodiments of the present disclosure taken in conjunction with the accompanied drawings, in which:
Refers to
an insulating substrate 11 with through holes 111 formed on each side of the upper surface of the insulating substrate 11, the through hole 111 being filling with conductive metal, wherein the material of the insulating substrate 11 is sapphire, silicon carbide or aluminum nitride and thus behaves well in insulation property, the thickness of which may be thinner than that used in conventional process, such as, thinner than 100 um, so as to increase thermal resistance a device thereon, and wherein the through holes 111 are round hole or groove, in which the filling with conductive metal may be in full or partial way, the filling in partial way refers to a layer of conductive metal being filled on the side wall of through hole 111;
a n-type layer 12 formed on the insulating substrate 11 and configured to cover most of area of the upper surface of the insulating substrate 11 such that one side of the insulating substrate 11 is formed a mesa 112 while a hole 121 is provided on the other side in the n-type layer 12 with relative to the mesa 112, which is fit for the through hole 111 in the insulating substrate 11 and filled with conductive metal, the material of the n-type layer 12 being n-type gallium nitride (GaN);
an active layer 13 provided on the n-type layer 12 and at one side of the n-type layer, the area of which is smaller than that of the n-type layer 12, and which includes a quantum well structure made of gallium nitride material;
a p-type layer 14 provided on the active layer 13, the material of which is p-type gallium nitride;
an insulating layer 15, configured on one side of the n-type layer 12, the active layer 13 and the p-type layer 14 and to cover part of the upper surface of the p-type layer 14, the material of the insulating layer 15 and being made of silicon oxide or silicon nitride;
a p-type electrode 16 configured to cover the insulating layer 15 and part of the upper surface of the p-type layer 14, the p-type electrode 16 being connecting with the conductive metal in the through hole 111 in the insulating substrate 11;
a n-type electrode 17 provided on a side of the upper surface of the n-type layer 12 and configured to connect with the conductive metal in the through hole 111 in the insulating substrate 11;
a first back electrode 18 provided at one side of back surface of the insulating substrate 11, the first back electrode 18 connecting with the p-type electrode 16 through the conductive metal in the through hole 111 in the insulating substrate 11;
a second back electrode 19 provided at the other side of back surface of the insulating substrate 11 with relative to the first back electrode 18, the second back electrode 19 connecting with the n-type electrode 17 through the conductive metal in the through hole 111 in the insulating substrate 11;
wherein the materials of the p-type electrode 16, the n-type electrode 17, the first back electrode 18 and the second back electrode 19 are non-metal conductive material or conductive metal, and wherein the first back electrode 18 and the second back electrode 19 are made of weldable metal or alloy such that the present resulting packaging structure may be expediently welded to other circuit structure, the above portions/parts forming the base substrate of a device;
an optical element 20 packaged on the base substrate of the device, forming a whole device.
The optical element 20 is made individually or in combination of resin, or silicon gel, or glass, or other transparent materials. The optical element 20 may function to adjust the external light field distribution. The optical element 20 may protect the base substrate of the device from incursion of vapor, dirt and harmful gas. Further, the optical element 20 may improve luminescence efficiency of the device, in which the optical element 20 functions to achieve fluorescence conversion.
Referring to
growing a n-type layer 12, an active layer 13 and a p-type layer 14 in turn on an insulating substrate 11 by means of metal organic vapor phase epitaxy, forming an epitaxy layer, wherein the material of the insulating substrate 11 is sapphire, silicon carbide or aluminum nitride, and the n-type layer 12 and the p-type layer 14 in the epitaxy structure are placed in positive or reverse order, in which the materials of the n-type layer 12 and the p-type layer 14 are respectively n-type gallium nitride and p-type gallium nitride and the active layer 13 includes a quantum well structure made of gallium nitride material;
performing a down etching at one side on the surface of the p-type layer 14 by means of lithographic process with an etching depth so as to reach the surface of the n-type layer 12 to form a first mesa 1122, and performing a down etching at other side on the surface of the p-type layer 14 with an etching depth so as to reach the surface of the insulating substrate 12 to form a second mesa 122, in which the etching method applied to the p-type layer 14 is a dry etching or wet etching;
forming a conductive through hole 111 in the first mesa 112 and the second mesa 122, which are provided with a conductive metal, wherein the conductive through holes 111 may be round hole or groove, and may be fabricated by means of laser beam drilling, or dry etching, or optical assistant wet etching process, and are not limited in number, and wherein the conductive through holes 111 are filled with metal by means of plasma sputtering, or electron beam evaporation, or chemical plating, or electrochemistry plating process;
providing an insulating layer 15 at the side of the epitaxy layer close to the first mesa 112 and covering part of the upper surface of p-type layer 14, wherein the material of the insulating layer 15 is silicon oxide or silicon nitride, which is fabricated by electron beam evaporation, or PECVD or iron sputtering process;
providing a p-type electrode 16 on the insulating layer 15 and covering it, the p-type electrode 16 covering part of p-type layer 14 and connecting with the conductive metal in the conductive through hole 111, wherein the p-type electrode 16 forms an ohmic contact with the p-type layer 14 and thus obtain good current expansion on the p-type layer 14;
fabricating a n-type electrode 17 on the conductive through hole 111 in the second mesa 122, the n-type electrode 17 connecting with the conductive metal in the conductive through hole 111, wherein the n-type electrode 17 forms an ohmic contact with the n-type layer 12 and thus obtain good current expansion on the n-type layer 12, and wherein the p-type electrode 16 and the n-type electrode 17 include conductive metal.
An optical element 20 is packaged on the base substrate of the device, in which the optical element 20 is made individually or in combination of resin, or silicon gel, or glass, or other transparent materials. The optical element 20 may function to support the device and protect the device from incursion of vapor, dirt and harmful gas. Further, the optical element 20 may improve luminescence efficiency of the device, in which the optical element 20 functions to achieve fluorescence conversion. The optical element 20 may also function to adjust the external light field distribution.
The insulating substrate 11 may be further processed to be thinned and thus thinner than that in conventional process due to the existence of the optical element 20, enabling to obtain a reduced thermal resistance.
A first back electrode 18 and a second back electrode 19 may be further fabricated on each side of the back face of the thinned insulating substrate 11, respectively, wherein the first back electrode 18 and the second back electrode 19 are connected with the p-type electrode 16 and n-type electrode 17 through the conductive metal in the conductive through holes 111, respectively, and are made of conductive metal, in which the first back electrode 18 and the second back electrode 19 are made of weldable metal or alloy such that the present resulting packaging structure may be welded to other circuit structure.
The objective, technical scheme and advantageous technical effect of the present application have been described in detail by the above embodiments and Figures. It is understood that the above description is just directed to embodiments of the present application and modifications, equivalent replacement and improvements may be made by those skilled in the art to the invention without departing from the scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201110198226.3 | Jul 2011 | CN | national |
| 201110198263.4 | Jul 2011 | CN | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/CN2012/072310 | 3/14/2012 | WO | 00 | 4/22/2014 |
