The application relates to the field of semiconductor packaging, in particular to a packaging substrate, a grid array package, and a preparation method therefor.
In semiconductor packaging, a land grid array (LGA) package has a structure similar to that of a ball grid array (BGA) package, except that a solder ball is not attached to the LGA package. Compared with the BGA package, the LGA package can be mounted on a printed circuit board (PCB) by using lead free paste instead of a solder ball containing lead that is harmful to human body.
Therefore, in countries where the use of some semiconductor packaging products is restricted due to environmental considerations, the LGA package has attracted attention as an environment-friendly “green” product.
However, the current LGA package is made by lamination of multilayer materials, and usually cannot be subjected to side plating, thus limiting the use of the LGA package.
Therefore, it is necessary to provide a novel packaging substrate for an LGA package to overcome the above defect.
The embodiments of the present application provide a novel packaging substrate, so as to obtain a land grid array package capable of being subjected to side plating by means of a structure design.
An aspect of the present application provides a packaging substrate, including a plurality of packaging units, each packaging unit being defined by a closed packaging line, wherein the packaging substrate includes: a base substrate having a first surface and a second surface that are opposite to each other; a plurality of solder pads provided on the first surface of the base substrate; and a metal layer provided on the second surface of the base substrate; wherein in one packaging unit, the metal layer includes a plurality of lead pads, at least one lead pad extends from an inner side of the packaging unit defined by the packaging line to an outer side of the packaging unit, the lead pad is connected to one solder pad by means of a connecting member penetrating through the base substrate, and an orthographic projection of the connecting member on the base substrate at least partially covers the packaging line.
In some embodiments, the packaging substrate further includes a solder mask, the solder mask being provided on the first surface of the base substrate and exposing each solder pad.
In some embodiments, the metal layer further includes at least one carrier portion, the carrier portion being used for carrying at least one chip.
Another aspect of the present application provides a grid array package having a body, the grid array package including: a packaging unit obtained by cutting the packaging substrate described above, and at least one chip provided on the metal layer of the packaging unit; wherein the body of the grid array package has at least one third surface perpendicular to the first surface, and the plurality of solder pads are provided at an edge of the first surface and extend from the first surface to the third surface.
In some embodiments, the grid array package further includes a solder mask, the solder mask being provided on the first surface and exposing each solder pad.
In some embodiments, the metal layer includes at least one carrier portion, and the at least one chip is provided on the carrier portion.
In some embodiments, the chip is connected to a lead pad of the metal layer by means of a lead.
In some embodiments, the grid array package further includes a sealing material, the sealing material encapsulating the packaging unit and the at least one chip provided on the metal layer of the packaging unit, and connecting the chip and the lead pad to form the body.
Another aspect of the present application provides a preparation method for a grid array package, including steps of: providing the packaging substrate described above; mounting at least one chip on the packaging substrate; forming a lead to connect the chip and the packaging substrate, and performing packaging using a sealing material; and performing cutting along the packaging line to expose the connecting member, so as to form a grid array package.
In some embodiments, after the step of performing cutting along the packaging line, the preparation method further includes a step of plating a surface of the exposed connecting member with gold.
Another aspect of the present application provides a grid array package, that includes a base substrate having a first surface and a second surface that are opposite to each other, a plurality of solder pads provided on the first surface of the base substrate, and a metal layer provided on the second surface of the base substrate. The metal layer includes a carrier portion and a plurality of lead pads. The grid array package also includes at least one connecting member disposed at an edge of the base substrate on a third surface perpendicular to the first surface, and the connecting member connects a solder pad with a corresponding lead pad. The grid array package also includes a chip attached to the carrier portion of the metal layer and a plurality of leads connecting the chip to the lead pads.
In some embodiments of the above grid array package, the connecting member, the corresponding lead pad, and the corresponding solder pad are made of the same material.
In some embodiments, the connecting member is formed integrally with the solder pad.
In some embodiments, a solder pad provided on the first surface extends from the first surface to the third surface perpendicular to the first surface.
In some embodiments, the connecting member is subjected to a side plating process and achieves side plating on a portion of a land grid array (LGA).
Another aspect of the present application provides a method for forming a grid array package. The method includes providing a packaging unit. The packaging unit includes a base substrate having a first surface and a second surface that are opposite to each other, a base substrate having a first surface and a second surface that are opposite to each other, a plurality of solder pads provided on the first surface of the base substrate, and a metal layer provided on the second surface of the base substrate. The metal layer includes a carrier portion and a plurality of lead pads and at least one connecting member disposed at an edge of the base substrate on a third surface perpendicular to the first surface, the connecting member connecting a solder pad with a corresponding lead pad. The method also includes attaching a chip to the carrier portion of the metal layer, forming a plurality of leads connecting the chip to the lead pads, and applying a sealing material to encapsulate the packaging unit.
In some embodiments of the above method, the connecting member, the corresponding lead pad, and the corresponding solder pad are made of the same material.
In some embodiments, the connecting member is formed integrally with the solder pad.
In some embodiments, a solder pad provided on the first surface extends from the first surface to the third surface perpendicular to the first surface.
In some embodiments, the connecting member is subjected to a side plating process and achieves side plating on a portion of a land grid array (LGA).
In this application, a land grid array package capable of being subjected to side plating is obtained by means of a structure design.
To more clearly illustrate the features of specific embodiments, the drawings of the embodiments are briefly described below. Obviously, the drawings described below are merely some embodiments of the present application. For ordinary researchers or practitioners in the art, other similar drawings may be obtained according to these drawings without involving inventive effort.
The present application is described below in further details with reference to specific embodiments. It is obvious that the described embodiments are merely some of the applications of the present application, rather than all of them. It should be understood that these embodiments are only used to illustrate the characteristics of the present application and are not intended to limit the scope of the present application. All other embodiments obtained by a person of ordinary skill in the art without involving inventive effort fall within the protection scope of this application.
In this embodiment, referring to
The packaging substrate 100 is described in detail below with reference to
Referring to
Referring to
Referring to
In order to achieve electrical connection between the chip 200 provided on the second surface S2 of the base substrate 110 and the solder pad 120 on the first surface S1 of the base substrate 110, referring to
Accordingly, upon provision of a package, in particular a grid array package 1, the packaging substrate 100 as shown in
Referring to
Therefore, the final grid array package 1 obtained in the present application has a solder pad on the side face thereof, in addition to the solder pad conventionally provided on the bottom surface, thereby overcoming the drawback that the LGA is incapable of being subjected to a side plating process, and achieving side plating on a portion of the LGA.
The present application has been described using the related embodiments described above. However, the above-mentioned embodiments are merely examples of the present application. It should be noted that the disclosed embodiments do not limit the scope of the present application. On the contrary, all modifications and equivalent arrangements that come within the spirit and range of the claims shall fall within the scope of the present application.
Number | Date | Country | Kind |
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202110214174.8 | Feb 2021 | CN | national |
202120421699.4 | Feb 2021 | CN | national |
This application is a continuation of International Patent Application No. PCT/CN2021/133043, filed Nov. 25, 2021, published as WO2022/179214 on Sep. 1, 2022 and entitled “PACKAGING SUBSTRATE, GRID ARRAY PACKAGE, AND PREPARATION METHOD THEREFOR”, which claims priority to Chinese patent application No. 202110214174.8, filed on Feb. 25, 2021 and entitled “PACKAGING SUBSTRATE, GRID ARRAY PACKAGE, AND PREPARATION METHOD THEREFOR”, and priority to Chinese patent application No. 202120421699.4, filed on Feb. 25, 2021 and entitled “PACKAGING SUBSTRATE AND GRID ARRAY PACKAGE”, the disclosures of which are hereby incorporated by reference in their entirety.
Number | Date | Country | |
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Parent | PCT/CN2021/133043 | Nov 2021 | WO |
Child | 18193598 | US |