1. Field of the Invention
The present invention relates to a packaging substrate having capacitor embedded therein and, more particularly, to a packaging substrate having a capacitor embedded therein which can solve the problem that a thin core is difficult to be processed.
2. Description of Related Art
Customer demands of the electronics industry continue to evolve rapidly, and the main trends of electronic devices focus on multiple functions and high performance. Moreover, in order to satisfy the requirements for high integration and miniaturization, packaging substrates have transferred from single-layered boards to multiple-layered boards, so that plenty of circuits and electronic components can be disposed in the same volume unit of the substrate. However, as the semiconductor devices have been progressively integrated, the number of pins of the package structure has increased at the same time. The increase on the number of pins and circuits may in turn cause the noise to be raised. Hence, passive components, such as resistors, capacitors, and inductors, are applied in the semiconductor package structure to diminish the noise or electrically compensate and stabilize the circuits. Therefore, the assembled semiconductor chip can meet the requirement for electrical property.
In the conventional method for manufacturing the packaging substrate, many passive components are mounted on the surface of the substrate by surface mount technology (SMT) in order to follow the trend towards miniaturization. However, when the packaging substrate is manufactured by SMT, it is hard to change the arrangement of capacitors and circuits, and the volume of the packaging substrate is hard to be reduced.
Recently, it is found that the method of lamination can solve the aforementioned problems, wherein a high dielectric material is sandwiched in copper layers to manufacture circuits, and then a capacitor is obtained.
However, there are some disadvantages about the aforementioned method. First, the content of ceramic fillers in the high dielectric layer is high, which results in poor fluidity of the high dielectric layer. When the thickness of the inner circuit layer is increased or the thickness of the high dielectric layer is reduced, some voids or dimples may be easily generated in the high dielectric layer in spaces between the circuits of the inner circuit layer 11. Second, the content of gel in the high dielectric material is low, which may cause poor reliability of the adhesion between the inner circuit layer and the high dielectric layer. Third, the thickness of the high dielectric layer is less than 30 μm, and there are no glass fibers to enhance the structure of the high dielectric layer. Hence, when circuit layers are formed on the two surfaces of the high dielectric layer respectively, the high dielectric layer may easily crack due to there being no enough support from copper foils formed on the two surfaces of the dielectric layer. Therefore, it is desirable to provide a packaging substrate to solve the aforementioned problems.
In view of the aforementioned problems, the object of the present invention is to provide a packaging substrate having capacitors embedded therein to diminish voids generated in a high dielectric material, improve the reliability of the adhesion between the high dielectric material and a circuit layer, and to solve the problem that the high dielectric material easily cracks during the process of manufacture.
To achieve the object, the present invention provides a packaging substrate having capacitors embedded therein, which comprises: two capacitor disposition layers, each respectively consisting of a high dielectric layer and two first circuit layers disposed on two opposite surfaces of the high dielectric layer respectively, wherein each of the first circuit layers has a plurality of electrode plates and a plurality of circuits; an adhesive layer disposed between the capacitor disposition layers to adhere the capacitor disposition layers to form a core board structure, wherein spaces between the circuits of every first circuit layer are filled with the adhesive layer; and a plurality of conductive through holes penetrating the capacitor disposition layers and the adhesive layer, and electrically connecting the circuits of the capacitor disposition layers respectively; wherein, pairs of the electrode plates on the opposite surfaces of each of the capacitor disposition layers are parallel and correspond to each other to form capacitors.
In the aforementioned structure, each of the capacitor disposition layers further comprises a plurality of conductive vias to electrically connect the two first circuit layers thereof. Besides, the material of the high dielectric layer is selected from polymer material, ceramic material, polymer material filled with ceramic powders, or a combination thereof.
In addition, the aforementioned packaging substrate further comprises two built-up structures respectively disposed on two opposite surfaces of the core board structure, wherein each of the two built-up structures comprises at least one dielectric layer, a second circuit layer disposed on the dielectric layer, and a plurality of conductive vias respectively, the outmost second circuit layer has a plurality of conductive pads, and at least parts of the conductive vias electrically connect to the first circuit layers of the core board structure. Besides, the aforementioned packaging substrate further comprises a solder mask disposed on the surfaces of the two built-up structures, wherein the solder mask has a plurality of openings to expose the conductive pads of the two built-up structures.
Furthermore, the present invention provides a method for manufacturing a packaging substrate having capacitors embedded therein, which comprises the following steps: providing two capacitor disposition layers, each of which respectively consisting of a high dielectric layer and two metal layers disposed on two opposite surfaces of the high dielectric layer; patterning the metal layer of the two capacitor disposition layers to form a first circuit layer, which has a plurality of electrode plates and a plurality of circuits; laminating an adhesive layer between the capacitor disposition layers to adhere the capacitor disposition layers to form a core board structure, wherein spaces between the circuits of every first circuit layer are filled with the adhesive layer; and forming a plurality of conductive through holes penetrating the capacitor disposition layers and the adhesive layer of the core board structure, and electrically connecting the circuits of the capacitor disposition layers respectively; wherein the electrode plates on the opposite surfaces of each of the capacitor disposition layers are parallel and correspond to each other to form a capacitor.
The aforementioned method may further comprise a step of: providing another capacitor disposition layer, wherein two first circuit layers are formed on the two surfaces of the capacitor disposition layer, the capacitor disposition layer is disposed between the other two capacitor disposition layers; and sandwiching in adhesion layers by lamination to adhere the three capacitor disposition layers to form a core board structure.
In the aforementioned method, each of the capacitor disposition layers further comprise a plurality of conductive vias to electrically connect the two first circuit layers thereof.
The aforementioned method may further comprise a step of: forming two built-up structures respectively on two opposite surfaces of the core board structure, wherein the built-up structures has at least one dielectric layer, a second circuit layer disposed on the dielectric layer, and a plurality of conductive vias, the outmost second circuit layer has a plurality of conductive lands, and parts of the conductive vias are electrically connecting the circuits of the core board structure respectively. In addition, the aforementioned method may further comprise a step of: forming a solder mask on the surfaces of the built-up structures, and forming a plurality of openings on the solder masks to expose the conductive pads of the built-up structures.
In the present invention, the spaces between the circuits of every first circuit layer disposed on the high dielectric layer are filled with an adhesion layer, so the problem i.e., voids may be easily generated in the high dielectric material, can be solved. In addition, the reliability of the adhesion between the high dielectric material and a circuit layer can be improved, and the problem in which the high dielectric material easily cracks during the process of manufacture also can be solved.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Because of the specific embodiments illustrating the practice of the present invention, a person having ordinary skill in the art can easily understand other advantages and efficiency of the present invention through the content disclosed therein. The present invention can also be practiced or applied by other variant embodiments. Many other possible modifications and variations of any detail in the present specification based on different outlooks and applications can be made without departing from the spirit of the invention.
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Therefore, a packaging substrate having capacitors embedded therein is obtained, which comprises: two capacitor disposition layers 21, each respectively consisting of a high dielectric layer 211 and two first circuit layers 22 disposed on two opposite surfaces of the high dielectric layer 211, wherein each of the first circuit layers 22 has a plurality of electrode plates 221 and a plurality of circuits 222; an adhesive layer 23 disposed between the capacitor disposition layers 21 to adhere the capacitor disposition layers 21 to form a core board structure 20, wherein spaces 223 between the circuits 222 of every first circuit layer 22 are filled with the adhesive layer 23; and a plurality of conductive through holes 26 penetrating the capacitor disposition layers 21 and the adhesive layer 23, and electrically connecting the circuits 222 of the capacitor disposition layers 21 respectively; wherein, pairs of the electrode plates 221 on the opposite surfaces of each of the capacitor disposition layers 21 are parallel and correspond to each other to form capacitors 28.
With reference to
The method for manufacturing a packaging substrate is similar to the method illustrated in Embodiment 1. With reference to
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the scope of the invention as hereinafter claimed.
Number | Date | Country | Kind |
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096138831 | Oct 2007 | TW | national |