Patent Application
20230062645
The present invention relates to the technical field of processors, in particular to a method for extracting instructions in parallel and a readable storage medium.
After more than 50 years of development, the architecture of microprocessor has experienced vigorous development along with the semiconductor technology, from single-core to physical multi-core and logical multi-core; from sequential execution to out-of-order execution; from single-issue to multi-issue. Especially in the server field, the performance of the processor is constantly being pursued.
At present, server chips are basically superscalar out-of-order execution architecture, and the processing bandwidth of processors is getting higher and higher, up to 8 or more instructions per clock cycle.
When multiple instructions are fetched at the same time in the instruction fetch unit, each instruction is fetched in sequence, and the logical link is relatively long. At present, high-performance processors need to extract 8 or more bandwidths per clock cycle, and the clock frequency requirements are relatively high. The current implementation method does not meet the requirements.
In view of the deficiency of the prior art, the invention discloses a parallel extraction instruction method and a readable storage medium, which is used for solving the problem that when Instruction Fetch Unit fetches multiple instructions at the same time, the logical link of serial extraction of each instruction is relatively long. At present, high-performance processors need to extract 8 or more bandwidth per clock cycle, and the clock frequency is relatively high. The current implementation method can not meet the requirements.
The present invention is achieved through the following technical solutions:
First, the invention discloses a method for parallel extracting instructions, which is characterized in that the method generates the effective vector of the extracted instruction according to the end position vector s_mark_end of the instruction, performs parallel decoding of instructions at each position through logical “AND” and logical “OR” operations, calculates the instruction address and the branch instruction target address operation, and finally fetches multiple instructions in parallel.
Further, in the method, the low 2 bit of the first instruction is first determined. If the low 2 bit is 00, 01, or 10:00, the first instruction length is 16 bit, and if the low 2 bit is 11:00, then the first instruction length is 32 bit. Then the second instruction is judged from the next byte at the end position of the instruction. The judgment process is similar to that of the first instruction, and the length of the second instruction is obtained. By analogy, the length of each instruction in cacheline is obtained. After obtaining the length of each instruction, the end position vector s_end_mark of each instruction in the instruction stream is obtained.
Further, in the method, when an instruction is written, the end position vector s_end_mark of each instruction is calculated, and the instruction returned from the writer is in cacheline units. Each cacheline is 64 byte. The high and low 32 byte of the instruction calculates the end position vector of the instruction respectively, and the high 32 byte instruction speculates that the instruction end position vector s_end_mark_0 and s_end_mark_1 with offset 0 and offset 2. According to the low 32 byte instruction end position vector, a high 32 byte vector is selected as the final instruction end vector of the high 32 byte instruction. The instruction end position vector and the instruction are written at the same time.
Further, in the method, when the Instruction Fetch Unit starts fetching fingers, the read instruction simultaneously reads the instruction end position vector to verify the prediction information of the BPU and extract the instruction. The instruction end position vector s_mark_end indicates whether the position is the end position of an instruction, a value of 1 means the end position of an instruction, and a value of 0 indicates the end position of an instruction.
Further, in the method, the bandwidth of the Instruction Fetch Unit is each clock cycle of the 32 byte, while fetching the instruction, the jump of the branch instruction is predicted, and the prediction is made according to the high 2 byte of the branch instruction, and if the jump occurs in the predicted branch instruction, then jump to the target address. After retrieving the instruction from the target address, it is necessary to check the instruction alias error, that is, to determine whether the branch instruction that predicts the jump is a branch instruction, and the type of the branch instruction is the same.
Further, in the method, multiple threads are supported, and all threads share the BPU prediction unit, so the prediction information between threads interferes with each other, and the results of interference include:
BPU may take the middle content of an instruction, that is, not the end of the branch instruction, as the end of the branch instruction where the jump occurs.
The type of branch instruction does not match if this BPU information is written by a JA, but when a JALR instruction may predict based on the information of the JAL.
Further, in the method, the BPU information includes a prediction offset pred_offset of the BPU and an instruction type pred_type. The BPU generates a refresh according to the target predicted by the BPU, and refetches the instruction to detect whether the s_mark_end [20] is 1. If not, the position predicted by pred_offset is not the end position of a branch instruction, but the middle of an instruction, then a refresh is generated from the address at the end of the most recent instruction in the pred_offset, and the instruction is refetched, while clearing the incorrect prediction information in the BPU.
Further, in the method, if the pred_offset is the end position of a branch instruction, but when fetching the instruction, it is also determined that the corresponding position of the s_mark_end is a branch instruction. If the type of branch instruction is different from the type pred_type predicted by BPU, it is also an alias error, and there is no error in the instruction that predicts the jump. But if the predicted destination address is incorrect, the instruction is refetched from the position where pred_offset plus 1 is added, and the error message corresponding to that location in the BPU is cleared. Only when the location and type predicted by BPU are correct, the prediction information of BPU is correct, otherwise it is necessary to generate a refresh and retrieve the instruction from the correct address.
Further, in the method, when each instruction has been extracted from the instruction stream, it is determined whether there is a branch instruction in the instruction and whether a jump occurs according to the prediction information of the BPU. In the instruction, if there are multiple branch instructions, the first instruction has the highest priority, followed by the second instruction, and so on, the refresh is generated according to the target address of the branch instruction. Instruction Fetch Unit refetches the instruction according to this new address, and if there is no branch instruction, all instructions are written to the instruction queue.
In a second aspect, the invention discloses a readable storage medium, which includes a memory for storing execution instructions. When the processor executes the execution instruction stored in the memory, the processor hardware executes the parallel extraction instruction method described in the first aspect.
The beneficial effects of the invention are:
The present invention generates a valid vector for extracting instructions according to the end position vector s_mark_end of the instruction, and extracts multiple instructions in parallel through logical “AND” and logical “OR” operations. It can extract multiple instructions in parallel at the same time, there is no serial dependency between each instruction, the timing is easy to converge, and a higher frequency can be obtained. The present invention is particularly suitable for high-performance processors that fetch more than 8 instructions per clock cycle.
In order to more clearly illustrate the technical scheme in the embodiment of the present invention or the prior art, the drawings that need to be used in the embodiment or the prior art description will be briefly introduced below. It is obvious that the drawings described below are only some embodiments of the invention, and other drawings can be obtained according to these drawings without creative work for those skilled in the art.
In order to make the purpose, technical scheme and advantages of the embodiment of the invention more clear, the technical scheme in the embodiment of the invention will be described clearly and completely in combination with the drawings in the embodiment of the invention. It is clear that the described embodiments are some embodiments of the present invention but not all embodiments. Based on the embodiments of the invention, all other embodiments obtained by ordinary technicians in the field without creative work fall within the scope of the protection of the invention.
The embodiment is a method of extracting multiple instructions in parallel according to the end position vector s_mark_end of the instruction and extracting the effective vector of the instruction and extracting a plurality of instructions in parallel through the logic “and” and logic OR operation.
The embodiment is not limited to chips such as CPU, GPU, DSP, etc., and is not limited to any instruction set, any implementation process and other conditions.
In order to explain the principle of this method, we mainly take the RISC-V instruction set as an embodiment.
The RISC V instruction set supports 16 bit instruction length, 32 bit instruction length, 32 bit instruction length, 48 bit instruction length and 64 bit instruction length, as shown in
The minimum 2 bit for the 16 bit instruction is 00, 01, or 10. The minimum 2 bit for the 32 bit instruction is 11. Therefore, when judging the length of the current instruction, only the lowest 2 bit of the instruction needs to be judged. First determine the low 2 bit of the first instruction. If the low 2 bit is 00, 01, or 10:00, then the length of the first instruction is 16 bit. If the low 2 bit is 11:00, then the first instruction length is 32 bit. Then the second instruction is judged from the next byte at the end of the instruction. The judgment process is similar to that of the first instruction, and the length of the second instruction can be obtained. And so on, get the length of each instruction in cacheline, as shown in
When an instruction is written from L2 to L1, the end position vector s_end_mark of each instruction is calculated. The instruction returned from L2 is in cacheline units. As shown in
The present embodiment is not limited to chips such as CPU, GPU, DSP, etc., and is not limited to any instruction set, any implementation process and other conditions. This paper mainly takes RISC-V instruction set as an embodiment to illustrate. When Instruction Fetch Unit starts to fetch fingers, when reading instructions in L1 CACHE, the instruction end position vector is read out at the same time to verify the prediction information of BPU and extract instructions.
Instruction end position vector s_mark_end, indicating whether the position is the end of an instruction. A value of 1 indicates the end position of an instruction; a value of 0 indicates that it is not the end position of an instruction, that is, it may be the operation code of the instruction or the immediate number within the instruction.
In
The bandwidth of Instruction Fetch Unit is each clock cycle of 32 byte. Because 16 bit/32 bit hybrid instructions are supported, it is possible for a branch instruction to span two adjacent instruction blocks. The low 2 byte of the branch instruction is at the end of a 32 byte instruction block block0, while the high 2 byte is at the head of the adjacent instruction block block1, as shown in
While fetching the instruction, the jump of the branch instruction is predicted. The prediction is made according to the high 2 byte of the branch instruction, and if the branch instruction is predicted to jump, it will jump to the target address. After retrieving the instruction from the target address, it is necessary to check the instruction alias error, that is, to determine whether the branch instruction that predicts the jump is a branch instruction, and the type of the branch instruction is the same.
Because multiple threads are supported and all threads share the BPU prediction unit, the prediction information between threads interferes with each other.
The results of interference include: 1 the BPU may take the middle content of an instruction, that is, not the end of the branch instruction, as the end position of the branch instruction where the jump occurs.
2, the type of branch instruction does not match, if this BPU information is written by a JA, but when a JALR instruction may predict based on the information of the JAL.
The BPU prediction information includes the prediction offset pred_offset of the BPU and the instruction type pred_type. As shown in
BPU generates a refresh based on the target predicted by BPU and refetches the finger. When fetching the instruction, it is detected whether s_mark_end [20] is 1. It is found that s_mark_end [20] is 0, that is, the position predicted by pred_offset is not the end position of a branch instruction, but the middle of an instruction.
At this point, you need to add 1 from the address at the end of the most recent instruction in pred_offset, generate a refresh, and refetch the instruction, while clearing the wrong prediction information in BPU. By the same token, if pred_offset is the end position of a branch instruction, but when fetching, it is judged that the corresponding position of s_mark_end is a branch instruction, and if the type of branch instruction is different from the type pred_type predicted by BPU, it is also an alias error.
There is no error in predicting the jump of this instruction, but the predicted target address is incorrect. It is necessary to retrieve the instruction from the position where pred_offset plus 1 is added, and clear the error message of the corresponding location in BPU. Only when the location and type predicted by BPU are correct, the prediction information of BPU is correct, otherwise it is necessary to generate a refresh and retrieve the instruction from the correct address.
The embodiment parallel generates and extracts eight instruction effective vectors according to the instruction end vector, and at the same time, the 32 byte instruction conjectures the decoding, calculates the instruction address, calculates the target address of the instruction, and so on. Then, perform “AND” and “OR” logical operations on the effective vector of 8 instructions and speculative decoding, calculate the address of the instruction, calculate the target address of the instruction, etc., to obtain the extracted instruction and related attributes, as shown in
The present embodiment takes the effective vector generation logic of the second instruction as an embodiment. S_prt represents the offset of the first instruction in the 32 byte instruction stream. S_mark_end represents the instruction end position vector in the 32 byte instruction stream, and each bit of s_mark_end is 1 to indicate the end position of an instruction. Inst_2_val represents the valid vector of the second instruction in the 32 byte instruction stream, and the position of 1 indicates the byte at the beginning of the second instruction. Taking the 4 byte from this position is a complete instruction (if it is a compressed instruction of 16 bit, it has also been decoded to an 32 bit instruction). The effective vector inst_2_val of the second instruction and the 16 instructions obtained by speculative decoding first do the “AND” operation, and then do the “OR” operation to get the second instruction.
S_ptr and s_mark_end form an instruction position identification vector of 35 bit, which is mapped to another vector inst_2_val in the form of onehot. The logical mapping relationship that produces the valid vector of the second instruction is shown in the following table:
In the same way, the effective vectors of the remaining instructions can be obtained.
The instruction fetch unit decodes 32 bytes each time, and the RISC-V instruction length is 2 or 4. So the opcodes for instructions start at the even-numbered positions 0, 2, 4, . . . 30. Similarly, the end position of the instruction is odd-numbered positions 1, 3, 5, . . . , 31.
The effective vector inst_2_val[0] for the instruction is 1 if the instruction starts at position 0. At the same time, the instruction inst0 obtained by speculative decoding is fetched, and the length is 4 bytes. When the instruction is a C extension instruction, it has been decoded into an instruction with a length of 4 bytes during speculative decoding.
If the instruction starts from position 2, the effective vector inst_2_val[2] of the instruction is 1; meanwhile, the instruction inst1 obtained by speculative decoding is fetched.
If the instruction starts from position 4, then the effective vector inst_2_val[4] of the instruction is 1; meanwhile, the instruction inst2 obtained by speculative decoding is fetched.
If the instruction starts from position 6, then the effective vector inst_2_val[6] of the instruction is 1; meanwhile, the instruction inst3 obtained by speculative decoding is fetched.
If the instruction starts from position 8, the effective vector inst_2_val[8] of the instruction is 1; meanwhile, the instruction inst4 obtained by speculative decoding is fetched.
If the instruction starts from position 10, the effective vector inst_2_val[10] of the instruction is 1; meanwhile, the instruction inst5 obtained by speculative decoding is fetched.
If the instruction starts from position 12, the effective vector inst_2_val[12] of the instruction is 1; meanwhile, the instruction inst6 obtained by speculative decoding is fetched.
If the instruction starts from position 14, the effective vector inst_2_val[14] of the instruction is 1; meanwhile, the instruction inst7 obtained by speculative decoding is fetched.
If the instruction starts from position 16, then the effective vector inst_2_val[16] of the instruction is 1; meanwhile, the instruction inst8 obtained by speculative decoding is fetched.
If the instruction starts from position 18, the effective vector inst_2_val[18] of the instruction is 1; meanwhile, the instruction inst9 obtained by speculative decoding is fetched.
If the instruction starts from position 20, the effective vector inst_2_val[20] of the instruction is 1; meanwhile, the instruction inst10 obtained by speculative decoding is fetched.
If the instruction starts from position 22, the effective vector inst_2_val[22] of the instruction is 1; meanwhile, the instruction inst11 obtained by speculative decoding is fetched.
If the instruction starts from position 24, then the effective vector inst_2_val[24] of the instruction is 1; meanwhile, the instruction inst12 obtained by speculative decoding is fetched.
If the instruction starts from position 26, the effective vector inst_2_val[26] of the instruction is 1; meanwhile, the instruction inst13 obtained by speculative decoding is fetched.
If the instruction starts from position 28, the effective vector inst_2_val[28] of the instruction is 1; meanwhile, the instruction inst14 obtained by speculative decoding is fetched.
If the instruction starts from position 30, if the current instruction does not cross the boundary, then the effective vector inst_2_val[30] of the instruction is 1; meanwhile, the instruction inst15 obtained by speculative decoding is fetched.
If the current instruction crosses the boundary, the current instruction is invalid, and this instruction is not fetched until the next 32 byte instruction stream is valid.
If the offset of the 1st instruction is not 0, it starts at a non-zero offset. Then the starting position of the 1st instruction is the position of this offset. The positions of other instructions start with the same offset in sequence.
The logical expression to get the second instruction is:
Inst0, inst1, . . . inst15 are 16 speculatively generated instructions. The circuit implemented by the second instruction is implemented by logic “AND” and logic “OR” gates, as shown in
When calculating the address and target address of an instruction in this embodiment, it is also speculative calculation. The Instruction Fetch Unit fetches 32 bytes each time, and the fetch address is fetch_address, which is the base address for calculating the instruction address. Because the length of the RISC V instruction is 2 or 4, the instruction addresses for the speculative calculation of the 16 positions are: base_address, base_address+2, base_address+4, base_address+8, base_address+10, base_address+12, base_address+14, base_address+16, base_address+18, base_address+20, base_address+22, base_address+24, base_address+28 and base_address+30. The address inst_2_addr of the second instruction is also obtained using the logic similar to the second instruction. As follows:
Inst_2_addr=({64{inst_2_val[0]}}& base_address)|
Instructions fetched in the Instruction Fetch Unit, the branch instructions in the instructions include JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, C.JAL, CJ, C.BEQZ, C.BNEZ, C.JR and C. JALR. Among them, the destination address of the instructions JAL, BEQ, BNE, BLT, BGE, BLTU, BGEU, C.JAL, C.J, C.BEQZ, C.BNEZ is the addition of the instruction address and the offset. Similarly, it is assumed that each offset of 2 byte is a branch instruction, so it is also speculated that the target address of each instruction can be obtained by parallel computation. It is speculated that the target addresses of the instructions at 16 locations are: base_address+offset, base_address+2+offset, base_address+4+offset, base_address+8+offset, base_address+10+offset, base_address+12+offset, base_address+14+offset, base_address+16+offset, base_address+18+offset, base_address+20+offset, base_address+22+offset, base_address+24+offse, base_address+28+offset and base_address+30+offset. Offset is the offset of the branch instruction. Inst is an instruction.
The conditional instruction immediate number cond_imm of the 32 bit instruction is: cond_imm: {inst[31], inst[7], inst[30:25], inst[11:8], 1′b0};
The immediate data of unconditional instruction of 32 bit instruction is: uncond_imm: {inst[31], inst[19:12], inst[20], inst[30:21], 1′b0};
The conditional instruction immediate number cond_imm_c of the 16 bit compressed instruction is: cond_imm_c: {inst[12], inst[6:5], inst[2], inst[11:10], inst[4:3], 1′b0};
The unconditional instruction immediate number uncond_imm_c of the 16 bit compressed instruction is: uncond_imm_c: {inst[12], inst[8], inst[10:9], inst[6], inst[7], inst[2], inst[11], inst[5:3], 1′b0};
Each location may be these four branch instructions, so each location first determines the instruction type, and then calculates a different type of offset offset. The target address of the second instruction, Inst_2_target_addr, can also get a logical expression similar to Inst_2_addr, as shown in
The present embodiment determines that a specific branch instruction type br_type for each location is obtained. Br_type [0] is the conditional instruction of 32 bit instruction, br_type [1] is the unconditional instruction of 32 bit instruction, br_type [2] is the conditional instruction of 16 bit instruction, and br_type [3] is the unconditional instruction of 16 bit instruction. Therefore, the offset offset of the branch instruction is obtained according to br_type and cond_imm, uncond_imm, cond_imm_c and uncond_imm_c.
Since both 16 bit and 32 bit instructions are supported, there are mixed 16 bit and 32 bit instructions in the instruction stream. Each 32 byte instruction consists of 8-16 instructions, so an 32 bit instruction may exist across consecutive adjacent 32 byte instruction streams. In the instruction extraction module, a 2 byte register is used to store the high 2 byte of the 32 byte instruction stream, and the 2 byte is used as the 2 byte of cross-boundary instructions.
At the same time, it is determined whether the cross-boundary instruction occurs in the current 32 byte instruction stream, and if so, it is necessary to generate a valid indication signal of the cross-boundary instruction. When the adjacent 32 byte instruction blocks reach the instruction fetch pipeline stage, if the cross-boundary instruction effectively indicates that the signal is 1, it indicates that the first instruction has a cross-boundary situation. At this point, the first instruction consists of two parts, as shown in
If the cross-boundary instruction effectively indicates that the signal is 0, it means that the first instruction does not cross the boundary. The first instruction is the first instruction of the current 32 byte instruction block. Other instructions are taken in turn from the subsequent instruction stream of the first instruction. When the instruction is a branch instruction across the boundary, the BPU prediction information of the instruction also needs to be saved until the adjacent instruction stream is valid, the prediction information of the first instruction is obtained, which is similar to the processing method of getting the first instruction.
When each instruction has been extracted from the instruction stream, it is judged whether there are branch instructions in the 8 instructions and whether the jump occurs according to the prediction information of the BPU. Among the 8 instructions, if there are multiple branch instructions, the first instruction has the highest priority, followed by the second instruction, and so on. A refresh is generated according to the target address of the branch instruction, and the Instruction Fetch Unit refetches the instruction according to this new address. If there are no branch instructions, all instructions are written to the instruction queue.
The present embodiment discloses a readable storage medium, including a memory for storing execution instructions. When the processor executes the execution instruction stored in the memory, the processor hardware executes a method of extracting instructions in parallel.
In summary, according to the end position vector s_mark_end of the instruction, the invention generates a method of extracting the effective vector of the instruction and extracting a plurality of instructions in parallel through the logic “and” and logic OR operation. Multiple instructions can be extracted in parallel at the same time, there is no serial dependency between each instruction, the timing is easy to converge, and a higher main frequency can be obtained. It is especially suitable for high-performance processors that extract more than 8 instructions per clock cycle.
The above embodiments are only used to illustrate the technical scheme of the present invention and not to restrict it. Although the invention is explained in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that it can still modify the technical scheme recorded in the above-mentioned embodiments, or equivalent replacement of some of the technical features; and these modifications or replacements do not deviate the essence of the corresponding technical scheme from the spirit and scope of the technical scheme of the embodiments of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011482353.1 | Dec 2020 | CN | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2021/129451 | Nov 2021 | US |
| Child | 17981336 | US |
