Patent Application
20230395488
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
As the geometry size of IC devices decreases, passive devices that require large surface areas are moved to back-end-of-line (BEOL) structures. Metal-Insulator-Metal (MIM) capacitors are among examples of such passive devices. A typical MIM capacitor includes multiple conductor plate layers that are insulated from one another by multiple insulator layers. Although existing MIM capacitors are generally adequate for their intended purposes, they are not satisfactory in every aspect.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−15% by one of ordinary skill in the art. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Metal-Insulator-Metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random-access memories (DRAMs), embedded DRAMs, and logic operation circuits. In system-on-chip (SOC) applications, different capacitors for different functional circuits may be integrated on a same chip to serve different purposes. For example, in mixed-signal circuits, capacitors may be used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors may be used for memory storage, while for RF circuits, capacitors may be used in oscillators and phase-shift networks for coupling and/or bypassing purposes. For microprocessors, capacitors may be used for decoupling.
As its name suggests, an MIM capacitor includes a sandwich structure of interleaving metal layers and insulator layers. An example MIM capacitor includes multiple conductor plate layers, each of which is insulated from an adjacent conductor plate layer by an insulator layer. First type of contact vias may be formed to electrically couple to the conductor plate layers of the MIM capacitor, second type of contact vias may be formed to electrically couple to contact features disposed under the MIM capacitor. The conductor plate layers and the contact features may have different compositions and thus an etchant may etch the conductor plate layers and the contact features at different etch rates. In some existing technologies, to form of those contact vias, some embodiments may need to form an etch stop layer on each conductor plate layer of the MIM capacitor to facilitate the formation of those contact vias.
The present disclosure provides a method to simplify the formation of an MIM capacitor and the contact vias. In an embodiment, a device structure includes a lower contact feature in a first dielectric layer, an etch stop layer on the first dielectric layer, a metal-insulator-metal (MIM) capacitor formed over the etch stop layer. A bottom plate of the MIM capacitor is in direct contact with the etch stop layer. The device structure also includes a second dielectric layer over the MIM capacitor, a contact via extending through both the second dielectric layer and the MIM capacitor and electrically coupled to the lower contact feature, and an upper contact feature over and electrically coupled to the contact via. Instead of providing an etch stop layer on the conductor plate layer of the MIM capacitor and forming a contact via directly on the conductor plate layer, forming a contact via penetrating the conductor plate layer may be advantageously simplify the fabrication process. In some embodiments, a parasitic capacitance of the device structure may be reduced.
The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,
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The workpiece 200 also includes a multi-layered interconnect (MLI) structure 210, which provides interconnections (e.g., wiring) between the various microelectronic components of the workpiece 200. The MLI structure 210 may also be referred to as an interconnect structure 210. The MLI structure 210 may include multiple metal layers or metallization layers. In some instances, the MLI structure 210 may include eight (8) to fourteen (14) metal layers. Each of the metal layers includes multiple conductive components embedded in an intermetal dielectric (IMD) layer. The conductive components may include contacts, vias, or metal lines. The IMD layer may be a silicon oxide or silicon-oxide-containing material where silicon exists in various suitable forms. As an example, the IMD layer includes silicon oxide or a low-k dielectric material having k-value (dielectric constant) smaller than that of silicon oxide, which is about 3.9. In some embodiments, the low-k dielectric material includes a porous organosilicate thin film such as SiOCH, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOCN), spin-on silicon based polymeric dielectrics, or combinations thereof.
In an embodiment, a carbide layer 220 is deposited on the MLI structure 210. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof. Any suitable type of carbide material such as silicon carbide (SiC) can be used in the carbide layer 220.
In an embodiment, an oxide layer 230 is deposited on the carbide layer 220. Any suitable deposition process for the oxide layer 230 may be used, including CVD, flowable CVD (FCVD), spin-on coating, PVD, ALD, or combinations thereof. In some embodiments, the oxide layer 230 includes undoped silicon oxide.
In an embodiment, a first etch stop layer (ESL) 240 is deposited on the oxide layer 230. The first ESL 240 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), or silicon nitride (SiN), or combinations thereof and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof.
A first dielectric layer 250 may be deposited on the first ESL 240. A composition of the first dielectric layer 250 may be similar to that of the oxide layer 230. In some embodiments, the first dielectric layer 250 includes undoped silica glass (USG) or silicon oxide. The first dielectric layer 250 may be deposited using CVD, flowable CVD (FCVD), spin-on coating, PVD, ALD, or combinations thereof. In some embodiments, the first dielectric layer 250 may be about 800 nm to about 1000 nm thick.
The workpiece 200 also includes a number of lower contact features (e.g., a lower contact feature 253, a lower contact feature 254, and a lower contact feature 255) formed in the first dielectric layer 250. In some embodiments, the lower contact feature 253 may be a dummy contact feature or a functional contact feature, and the lower contact feature 254 may be a dummy contact feature or a functional contact feature, depending on different design requirements. The formation of the lower contact features may include patterning of the first dielectric layer 250 to form trenches and deposition of a barrier layer (not separately labeled) and a metal fill layer (not separately labeled) in the trenches. In some embodiments, the barrier layer may include titanium nitride or tantalum nitride and may be conformally deposited using PVD, CVD, metalorganic CVD (MOCVD), or a suitable method. In one embodiment, the barrier layer may include tantalum nitride. The metal fill layer may include copper (Cu) and may be deposited using electroplating or electroless plating. After the barrier layer and the metal fill layer are deposited, a planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to remove excess barrier layer and metal fill layer to form the lower contact features 253, 254 and 255. Although the lower contact features 253, 254, and 255 are disposed below upper contact features (such as upper contact features 281, 282, 283 shown in
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After the partially removal of the first insulator layer 264 and the second insulator layer 268, the structure of a MIM capacitor 274 is also finalized. As illustrated in
While the MIM capacitor 274 depicted in the present disclosure includes three conductor plate layers, an MIM capacitor according to the present disclosure may include more than 3 conductor plate layers, such as 4, 5, 6, or even more conductor plate layers. Adjacent conductor plate layers are insulated from one another by an insulator layer, similar to the first insulator layer 264 and the second insulator layer 268.
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The metal line portions 281b, 282b, and 283b may be part of a redistribution layer (RDL) to reroute bond connections between upper and lower layers. The contact via portions 281a, 282a, and 283a each may penetrate through different regions of the MIM capacitor 274 or the second dielectric layer 276. The contact via portion 281a electrically couples to sidewalls of the second conductor plate layer 266 and the dummy plate layer 262a and a top surface of the lower contact feature 253 but is electrically insulated from the first conductor plate layer 262b and the third conductor plate layer 270. The contact via portion 282a electrically couples to the first conductor plate layer 262b, the third conductor plate layer 270 and the lower contact feature 254 but is electrically insulated from the second conductor plate layer 266. The contact via portion 283a may be a logic contact via that is electrically coupled to the lower contact feature 255 but is electrically insulated from the functional portion of the MIM capacitor 274. That is, the contact via portion 283a is electrically insulated from any of the first conductor plate layer 262b, the second conductor plate layer 266, and the third conductor plate layer 270.
During operation of the workpiece 200, a first voltage may be applied to the metal line portion 283b, and a second voltage may be applied to the lower contact feature 255. The second voltage is different from the first voltage such that current will flow between the metal line portion 283b and the lower contact feature 255. That is, both the metal line portion 283b and the lower contact feature 255 are functional conductive features. During operation of the MIM capacitor 274, however, a third voltage may be applied to the metal line portion 281b or the lower contact feature 253 to provide a voltage to the second conductor plate layer 266, a fourth voltage may be applied to the metal line portion 282b or the lower contact feature 254 to provide a voltage to the first conductor plate layer 262b and the third conductor plate layer 270. That is, there is no current between the metal line portion 281b and the lower contact feature 253, and there is no current between the metal line portion 282b and the lower contact feature 254. In some embodiments, the third voltage may be applied to the metal line portion 281b, and the lower contact feature 253 may be referred to as a dummy conductive feature; or the third voltage may be applied to the lower contact feature 253, and the metal line portion 281b may be referred to as a dummy conductive feature. In some embodiments, the fourth voltage may be applied to the metal line portion 282b, and the lower contact feature 254 may be referred to as a dummy contact feature; or the fourth voltage may be applied to the lower contact feature 254, and the metal line portion 282b may be referred to as a dummy conductive feature.
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In the above embodiments, the MIM capacitor 274 includes three conductor layers interleaved by two insulator layers. In some other implementations, the MIM capacitor may include more than three conductor layers to provide a higher capacitance. For example,
The present disclosure provides for many different embodiments. Semiconductor structures and methods of fabrication thereof are disclosed herein. In one exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a first lower contact feature in a first dielectric layer, an etch stop layer on the first dielectric layer, a metal-insulator-metal (MIM) capacitor formed over the etch stop layer, wherein a bottom plate of the MIM capacitor is in direct contact with the etch stop layer, a second dielectric layer over the MIM capacitor, a first contact via extending through both the second dielectric layer and the MIM capacitor and electrically coupled to the first lower contact feature, and a first upper contact feature over and electrically coupled to the first contact via.
In some embodiments, the etch stop layer may include silicon carbide or aluminum nitride. In some embodiments, the first lower contact feature and the first upper contact feature may include copper (Cu). In some embodiments, the metal-insulator-metal (MIM) capacitor may include a bottom plate directly on the etch stop layer, a first insulator layer over the bottom plate, a middle plate over the first insulator layer, a second insulator layer over the middle plate, and a top plate over the second insulator layer. In some embodiments, the first upper contact feature may extend through the top plate, the second insulator layer, the first insulator layer, the bottom plate, and the etch stop layer. In some embodiments, the semiconductor structure may also include a second lower contact feature in the first dielectric layer and spaced apart from the first lower contact feature along a first direction, a conductive layer directly on the etch stop layer and spaced apart from the bottom plate along the first direction, a second contact via penetrating the middle plate and the conductive layer and electrically coupled to the second lower contact feature, and a second upper contact feature over and electrically coupled to the second contact via. In some embodiments, the conductive layer and the bottom plate may include the same composition and the same thickness. In some embodiments, the semiconductor structure may also include a third lower contact feature in the first dielectric layer and spaced apart from the first lower contact feature along a first direction, a third contact via extending through both the second dielectric layer and the etch stop layer, and electrically coupled to the third lower contact feature, a third upper contact feature over the third contact via and electrically coupled to the third contact via.
In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a first metal line and a second metal line in a first dielectric layer, an etch stop layer disposed on the first dielectric layer and in direct contact with the first metal line and the second metal line, a first conductive layer disposed on the etch stop layer and directly over the first metal line, a second conductive layer disposed on the etch stop layer and directly over the second metal line, wherein a top surface of the second conductive layer is coplanar with a top surface of the first conductive layer, a third conductive layer disposed over the first conductive layer and vertically overlapped with both the first conductive layer and the second conductive layer, a fourth conductive layer disposed over the third conductive layer and vertically overlapped with the second conductive layer, a first conductive feature electrically coupled to the first metal line and extending through the third conductive layer, the first conductive layer, and the etch stop layer, and a second conductive feature electrically coupled to the second metal line and extending through the fourth conductive layer, the second conductive layer, and the etch stop layer.
In some embodiments, the semiconductor structure may include an insulator layer disposed vertically between the second conductive layer and the third conductive layer, and wherein the insulator layer comprises a high-k dielectric material. In some embodiments, a portion of the second conductive layer may be disposed directly over the second metal line and a portion of the second conductive layer may be disposed directly over the first dielectric layer. In some embodiments, the semiconductor structure may include a third metal line in the first dielectric layer and spaced apart from the second metal line along a first direction, a third conductive feature electrically coupled to the third metal line without penetrating the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer. In some embodiments, the third metal line may extend lengthwise along a second direction perpendicular to the first direction and has a first length, and the first length may be greater than a length of the second metal line along the second direction. In some embodiments, the semiconductor structure may include a fifth conductive layer disposed over the fourth conductive layer, and a sixth conductive layer disposed over the fifth conductive layer. The first conductive feature may extend through the fifth conductive layer, and the second conductive feature may extend through the sixth conductive layer. In some embodiments, the etch stop layer may include silicon carbide or aluminum nitride.
In yet another exemplary aspect, the present disclosure is directed to a method. The method includes providing a workpiece that includes a first dielectric layer, a first lower contact feature, a second lower contact feature, and a third lower contact feature in the first dielectric layer. The method also includes depositing an etch stop layer directly on the first dielectric layer, forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate directly on the etch stop layer, forming a second dielectric layer over the metal-insulator-metal capacitor, forming a first contact via penetrating multiple layers of the metal-insulator-metal capacitor to electrically couple to the first lower contact feature, and forming a second contact via penetrating multiple layers of the metal-insulator-metal capacitor to electrically couple to the second lower contact feature.
In some embodiments, the forming of the metal-insulator-metal capacitor may include depositing a first conductive layer directly on the etch stop layer, patterning the first conductive layer to form a conductive feature directly over the first lower contact feature and a bottom plate directly over the second lower contact feature, depositing a first insulator layer over the workpiece, forming a middle plate over the first insulator layer, the middle plate being vertically overlapped with the first lower contact feature, depositing a second insulator layer over the workpiece, and forming a top plate over the second insulator layer, the top plate being vertically overlapped with the second lower contact feature. In some embodiments, the forming of the first contact via and the second contact via may include performing a first etching process to form a first via opening extending through both the middle plate and the conductive feature and stop on the etch stop layer, and a second via opening extending through both the top plate and the bottom plate and stop on the etch stop layer, performing a second etching process to extend the first via opening and the second via opening, thereby exposing the first lower contact feature and the second lower contact feature, forming the first contact via in the extended first via opening, and forming the second contact via in the extended second via opening. In some embodiments, the workpiece may include a third lower contact feature formed in the first dielectric layer and spaced apart from the second lower contact feature along a first direction, the top plate is not vertically overlapped with the third lower contact feature. In some embodiments, the method may include, after the forming of the top plate, performing an etching process to remove portions of the second insulator layer and the first insulator layer directly over the third lower contact feature, and forming a third second contact via penetrating the second dielectric layer and in direct contact with the third lower contact feature.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
