The present disclosure relates generally to patterning methods.
Nanoscale features (about 100 nm or smaller) are suitable for use in a variety of structures, for example, molecular electronic devices. Various processes and tools (e.g., photolithography, electron-beam lithography, etc.) have been developed for achieving nanoscale features. However, the resolution of these tools (photolithography and electron-beam lithography tools) is, in some instances, limited by the optical diffraction and electron scattering effects. Such limitations may make it difficult to achieve nanoscale features with sizes beyond their resolution limit (e.g., from about 50 to about 100 nm for the current state-of-the-art photolithography tools, or from about 10 to about 30 nm for the current state-of-the-art electron beam lithography tools) or with high aspect ratio.
Objects, features and advantages of the present disclosure will become apparent by reference to the following detailed description and drawings, in which like reference numerals correspond to similar, though not necessarily identical components. For the sake of brevity, reference numerals having a previously described function may not necessarily be described in connection with subsequent drawings in which they appear.
Embodiments of the patterning methods disclosed herein advantageously form nanoscale features or structures having a high-resolution pattern and a high aspect ratio. Throughout embodiments of the method, a height of the structure remains substantially unchanged, while a width of the structure is altered.
Referring now to
In an embodiment, the substrate 12 is a silicon-on-insulator (SOI) substrate. The pre-purchased or pre-formed SOI substrate includes the substrate 12 (e.g., a silicon wafer), the insulator layer 14 (e.g., silicon dioxide), and the silicon layer 16.
In another embodiment, the insulator layer 14 is established on the substrate 12, and then the silicon layer 16 is established on the insulator layer 14. The layer 14, 16 may be established using any suitable technique. Non-limiting examples of such techniques include thermal growth, evaporation, sputtering, epitaxial growth, low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or any other suitable chemical or physical vapor deposition techniques.
In the embodiments disclosed herein, silicon dioxide is a suitable material for the insulator layer 14. It is believed that other suitable materials, such as nitrides and oxynitrides, may be used as the insulator layer 14. Generally, the height H of the insulator layer 14 remains substantially unchanged throughout the patterning process; as such, the insulator layer 14 is selected or established to have the desirable height H.
Referring now to
The mask 18 may be formed of any suitable masking material, including, but not limited to metals (e.g., nickel, chromium, or the like, or combinations thereof), dielectrics, polymers, resist materials, or combinations thereof. Establishing the mask 18 may be accomplished by lithography, lift-off processes, printing (e.g., inkjet or contact printing techniques), radiation beam “writing” processes, scanning probe “writing” processes, or the like, or combinations thereof.
As depicted, the patterned insulator layer 14 forms the nanoscale feature(s) 20, each of which has an initial width WI. As previously described, the initial width WI is the width W of the mask 18. The initial formation of the nanoscale feature(s) 20 leaves at least a portion of the insulator layer 14 directly contacting the silicon layer 16, while other portions are exposed.
After the mask pattern is transferred to the layer 14, 16, the insulator layer 14 (i.e., nanoscale feature(s) 20) is exposed to a wet-etching process. A non-limiting example of such a process is a hydrofluoric (HF) wet-etch. This process substantially etches or trims away exposed areas of the insulator layer 14, thereby leaving a height of the layer/features 14, 20 substantially intact. As such, the initial width WI of the nanoscale feature(s) 20 decreases to a desirable final width WF. It is to be understood that the decrease in width may be controlled, at least in part, by the concentration of the diluted HF and/or by the amount of time the insulator layer 14 is exposed to the wet-etching process. Generally, if the nanoscale feature(s) 20 is/are exposed to a relatively short wet-etch, less of the initial width WI will be reduced than if the nanoscale feature(s) 20 is are exposed to a longer wet-etch. Etching may be accomplished for several seconds to several minutes. The etch time may be calculated by the following equation:
[(initial width−desired final width)/2]/(etch rate)=etch time (1)
As a non-limiting example, the etch rate of thermally grown silicon dioxide in 1:50 diluted HF is about 5 nm/min. In order to reduce an initial width WI of about 50 nm to a final width WF of about 20 nm, the etch time is calculated using equation (1), [(50−20)nm/2]/(5 nm/min)=3 minutes. In another non-limiting example, the initial width WI of the nanoscale feature(s) 20 is about 100 nm, and the final width WF (after wet-etching) of the nanoscale feature(s) 20 is about 10 nm.
As depicted in
After the mask 18 and silicon layer 16 are removed, this embodiment of the method includes removing the protective layer 22, as shown in
In another embodiment of the method, after the wet-etching process (as shown in
As previously described,
While several embodiments have been described in detail, it will be apparent to those skilled in the art that the disclosed embodiments may be modified. Therefore, the foregoing description is to be considered exemplary rather than limiting.