Phase-change random access memory device

Abstract

A phase-change random access memory device is provided. The phase-change random access memory device includes a plurality of memory blocks, a main word line, a plurality of local word lines and a plurality of section word line drivers connected between the main word line and each of the plurality of local word lines and adapted to adjusting voltage levels of the plurality of local word lines in response of voltages applied to the main word line and block information. The plurality of section word line drivers include at least one first section word line driver and at least one second section word line driver. The first section word line drivers include pull-down devices while not including pull-up devices.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the disclosed methods and systems will become more apparent by describing in detail disclosed embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram of a conventional phase-change random access memory device;

FIG. 2 is a block diagram of a phase-change random access memory device according to an embodiment of the disclosed methods and systems;

FIG. 3 is a circuit diagram of a phase-change random access memory device illustrating a first memory sector shown in FIG. 2;

FIG. 4 is a detailed circuit diagram of section word line drivers and SWD1 and memory blocks;

FIG. 5A is a diagram illustrating a layout area of the phase-change random access memory device according to an embodiment of the disclosed methods and systems,

FIG. 5B is a diagram illustrating a layout area of a conventional phase-change random access memory device;

FIG. 6 is a circuit diagram of a phase-change random access memory device according to another embodiment of the disclosed methods and systems; and

FIG. 7 is a circuit diagram of a phase-change random access memory device according to still another embodiment of the disclosed methods and systems.

Claims

1. A phase-change random access memory device, comprising: a plurality of memory blocks with each memory block including a plurality of phase-change memory cells;a main word line;a plurality of local word lines arranged corresponding to the plurality of memory blocks, respectively; anda plurality of section word line drivers with each section each word line driver connected between the main word line and a respective local word line and adapted to adjust a voltage level of its respective local word lines in response to a voltage applied to the main word line and block information, wherein the plurality of section word line drivers include at least one first section word line driver and at least one second section word line driver,wherein the at least one first section word line driver includes a plurality of pull-down devices pulling-down the voltage levels of the plurality of local word lines in response to voltages applied to the main word line and block information while not including a pull-up device, andwherein the at least one second section word line driver includes pull-up devices pulling-up voltage levels of the plurality of local word lines in response of voltages applied to the main word line and pull-down devices pulling-down voltage levels of the plurality of local word lines in response of voltages applied to the main word line and block information.

2. The phase-change random access memory device of claim 1, wherein the block information designates a memory block corresponding to a local word line connected with each of the plurality of section word line drivers.

3. The phase-change random access memory device of claim 1, wherein each of the pull-down devices includes first and second NMOS transistors connected in series between each of the plurality of local word lines and a ground voltage, wherein the first NMOS transistor is gated in response to the voltages applied to the main word line and the second NMOS transistor is gated in response to the block information.

4. The phase-change random access memory device of claim 1, wherein each of the pull-up devices includes PMOS transistors connected between a power supply voltage and a respective local word lines;wherein each of the pull-down devices includes first and second NMOS transistors connected in series between a respective local word lines and a ground voltage;wherein the PMOS transistors and the first NMOS transistors are gated in response to the voltages applied to the main word line, and the second NMOS transistor is gated in response to the block information.

5. The phase-change random access memory device of claim 1, wherein the plurality of section word line drivers include first and second section word line drivers that are alternately arranged.

6. The phase-change random access memory device of claim 1, wherein the plurality of section word line drivers include a couple of spaced-apart second section word line drivers arranged at opposite sections, and first section word line drivers arranged at the remaining sections.

7. The phase-change random access memory device of claim 1, wherein the plurality of section word line drivers comprise a second section word line driver arranged at a central section, and first section word line drivers arranged at the remaining sections.

8. The phase-change random access memory device of claim 1, wherein the phase-change memory cell includes a variable resistor containing a phase change material having at least two resistance values based on a current profile passing through the phase-change memory cell, and an access element controlling the current profile.

9. The phase-change random access memory device of claim 8, wherein the access element includes a diode connected in series with the variable resistor.

10. The phase-change random access memory device of claim 8, wherein the phase-change material is made of germanium (Ge), antimony (Sb) and tellurium (Te).

11. A phase-change random access memory device comprising: a main word line;a plurality of local word lines coupled to the main word linea plurality of memory blocks arranged in common with the main word line and a respective local word line of the plurality of local word lines; anda plurality of section word line drivers arranged between each of the plurality of memory blocks,wherein first and second section word line drivers are arranged at opposite sides of the at least one memory block,wherein the at least one first section word line driver includes pull-down devices pulling-down the voltage levels of the plurality of local word lines in response to a voltage applied to the main word line and block information while not including a pull-up device, andwherein the at least one second section word line driver includes pull-up devices pulling-up voltage levels of the plurality of local word lines in response to a voltage applied to the main word line and pull-down devices pulling-down voltage levels of the plurality of local word lines in response to a voltages applied to the main word line and block information.

12. The phase-change random access memory device of claim 11, wherein the block information designates a memory block of the at least one memory block.

13. The phase-change random access memory device of claim 11, wherein each of the pull-down devices of the at least one first section word line driver includes first and second NMOS transistors connected in series between each of the plurality of local word lines and a ground voltage, the first NMOS transistor being gated in response to the voltages applied to the main word line, and the second NMOS transistor being gated in response to the block information.

14. The phase-change random access memory device of claim 11, wherein each of the pull-up devices of the at least one second section word line driver includes PMOS transistors connected between a power supply voltage and a respective local word line, and the pull-down devices include first and second NMOS transistors connected in series between a respective local word line and a ground voltage, the PMOS transistors and the first NMOS transistor are gated in response to the voltages applied to the main word line, and the second NMOS transistor is gated in response to the block information.

15. A phase-change random access memory device comprising: a plurality of memory blocks each including a plurality of phase-change memory cells;a main word line;a plurality of local word lines arranged corresponding to a respective memory block; anda plurality of section word line drivers each connected between the main word line and a respective local word line, wherein each section word line driver adjust a voltage levels of a respective local word lines in response to a voltages applied to the main word line and block information.

16. The phase-change random access memory device of claim 15, wherein the block information designates a memory block corresponding to a local word line connected with each of the plurality of section word line drivers.

17. The phase-change random access memory device of claim 15, wherein the plurality of section word line drivers includes at least one first section word line driver and at least one second section word line driver, wherein each first section word line driver includes pull-down devices pulling-down the voltage levels of the plurality of local word lines in response to a voltage applied to the main word line and block information while not including a pull-up device, andwherein the at least one second section word line driver includes pull-up devices pulling-up voltage levels of the plurality of local word lines in response to a voltage applied to the main word line and pull-down devices pulling-down voltage levels of the plurality of local word lines in response to a voltage applied to the main word line and block information

18. The phase-change random access memory device of claim 17, wherein each of the pull-down devices includes first and second NMOS transistors connected in series between a respective local word line and a ground voltage, the first NMOS transistor being gated in response to the voltage applied to the main word line and the second NMOS transistor being gated in response to the block information.

19. The phase-change random access memory device of claim 17, wherein each of the pull-up devices includes PMOS transistors connected between a power supply voltage and a respective local word line, and the pull-down devices include first and second NMOS transistors connected in series between a respective local word line and a ground voltage, the PMOS transistors and the first NMOS transistors are gated in response to the voltage applied to the main word line, and the second NMOS transistor is gated in response to the block information.