PHASE-CHANGE RANDOM ACCESS MEMORY

Abstract

A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention can be understood in more detail from the following descriptions taken in conjunction with the attached drawings in which:

FIG. 1 is a block diagram representing a phase-change random access memory according to an exemplary embodiment of the present invention;

FIG. 2 is a block diagram of the phase-change random access memory according to an exemplary embodiment of the present invention;

FIGS. 3 and 4 are conceptual diagrams illustrating input/output repair operations of the phase-change random access memory according to an exemplary embodiment of the present invention;

FIG. 5 is a block diagram of a column address fuse box used in the system shown in FIG. 2;

FIG. 6 is a circuit diagram illustrating a master fuse unit and an input/output information fuse unit used in the system shown in FIG. 5

FIG. 7 is a circuit diagram illustrating a column address fuse used in the system shown in FIG. 5;

FIG. 8 is a block diagram of a control fuse box used in the system shown in FIG. 2;

FIG. 9 is a circuit diagram illustrating an input/output decoder used in the system shown in FIG. 2;

FIG. 10 is a circuit diagram illustrating a path selector circuit used in the system shown in FIG. 2; and

FIG. 11 is a schematic block diagram representing a phase-change random access memory according to an exemplary embodiment of the present invention.

Claims

1. A phase-change random access memory comprising: a memory block including a plurality of memory columns corresponding to a same column address and using different input/output paths;a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; andan input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using the redundancy memory columns in response to an input/output repair mode control signal.

2. The phase-change random access memory of claim 1, wherein the number of memory columns simultaneously repaired using the redundancy memory columns is one of 1, 2, 4, 8, and 16.

3. The phase-change random access memory of claim 1, wherein the input/output repair mode control signal is determined depending on whether at least one control fuse is cut.

4. A phase-change random access memory comprising: a memory block including a plurality of memory columns corresponding to a same column address and using different input/output paths;a redundancy memory block including a plurality of redundancy memory columns using different input/output paths;a plurality of column address fuse boxes corresponding to the plurality of redundancy memory columns, each of the plurality of column address fuse boxes receiving a column address, for determining whether the plurality of memory columns include at least one repaired memory column, and providing a designation signal for designating the at least one repaired memory column among the plurality of memory columns;a control fuse box providing an input/output repair mode control signal for designating input/output repair modes;an input/output decoder receiving and decoding the designation signal and the input/output repair mode control signal and providing a plurality of path selection signals; anda plurality of path selection circuits receiving the plurality of path selection signals and disabling input/output paths of the at least one repaired memory column and enabling redundancy input/output paths of the at least one redundancy memory column to replace the at least one repaired memory column.

5. The phase-change random access memory of claim 4, wherein the input/output repair modes includes ×1, ×2, ×4, ×8 and ×16 modes.

6. The phase-change random access memory of claim 4, wherein each of the plurality of column address fuse boxes comprises: a column address fuse unit including at least one column address fuse, storing a column address of the repaired memory column depending on whether the at least one control fuse is cut, receiving an external column address and determining whether the external column address is identical with the repaired column address stored therein; andan input/output information fuse unit including at least one input/output information fuse and providing a designation signal for designating repaired memory columns among the plurality of memory columns depending on whether the at least one input/output information fuse is cut.

7. The phase-change random access memory of claim 6, wherein each of the plurality of column address fuse boxes further comprises a master fuse unit including a master fuse and providing a master signal depending on whether the master fuse is cut, and wherein the column address fuse unit is enabled by the master signal.

8. The phase-change random access memory of claim 6, wherein the control fuse box comprises at least one control fuse and provides an input/output repair mode control signal depending on whether the at least one control fuse is cut.

9. The phase-change random access memory of claim 4, wherein the plurality of path selection circuits comprises a first path logic circuit enabling/disabling input/output paths of the repaired memory columns and a second path logic circuit enabling/disabling input/output paths of the redundancy memory columns to replace the repaired memory columns.

10. The phase-change random access memory of claim 4, wherein each of the memory columns and redundancy memory columns comprises a plurality of phase-change memory cells, each of the plurality of phase-change memory cells comprises a variable resistor containing a phase change material having at least two resistance values in response to current passing through the phase-change random access memory device cell, and an access element controlling the pass-through current.

11. The phase-change random access memory of claim 10, wherein the access element comprises a diode connected in series to a variable resistor.

12. The phase-change random access memory of claim 10, wherein the phase-change material is made of germanium (Ge), antimony (Sb), and tellurium (Te).

13. A phase-change random access memory comprising: a memory block including a plurality of memory subblocks and a plurality of memory columns corresponding to a same column address, each of the plurality of memory columns is arranged in each of the plurality of memory subblocks;a plurality of sense amplifiers and/or write drivers arranged corresponding respectively to the plurality of memory subblocks;a redundancy memory block including a plurality of redundancy memory columns;a plurality of repair sense amplifiers and/or write drivers arranged corresponding respectively to the plurality of redundancy memory columns;a plurality of column address fuse boxes corresponding respectively to the plurality of redundancy memory columns, each of the plurality of column address fuse boxes receiving a column address, for determining whether the plurality of memory columns includes at least one repaired memory column, and providing a designation signal for designating the at least one repaired memory column among the plurality of memory columns;a control fuse box providing an input/output repair mode control signal for designating input/output repair modes;an input/output decoder receiving and decoding the designation signal and the input/output repair mode control signal and providing a plurality of path selection signals; anda plurality of path selection circuits connected to the plurality of sense amplifiers and/or write drivers through a plurality of data lines, respectively, at least one of the plurality of path selection circuits connected to each of the plurality of repair sense amplifiers and/or write drivers through a plurality of redundancy data lines, and the plurality of path selection circuits selectively inputting/outputting data through the plurality of data lines or through the plurality of redundancy data lines.

14. The phase-change random access memory of claim 13, wherein the input/output repair modes include ×1, ×2, ×4, ×8, and ×16 modes.

15. The phase-change random access memory of claim 13, wherein each of the plurality of column address fuse boxes comprises: a column address fuse unit including at least one column address fuse, storing a column address of the repaired memory column depending on whether the at least one control fuse is cut, and receiving an external column address and determining whether the external column address is identical with the repaired column address stored therein; andan input/output information fuse unit including at least one input/output information fuse and providing a designation signal for designating repaired memory columns among the plurality of memory columns depending on whether the at least one input/output information fuse is cut.

16. The phase-change random access memory of claim 15, wherein each of the plurality of column address fuse boxes comprises a master fuse unit including a master fuse and providing a master signal depending on whether the master fuse is cut, and wherein the column address fuse unit is enabled by the master signal.

17. The phase-change random access memory of claim 13, wherein the control fuse box comprises at least one control fuse and provides an input/output repair mode control signal depending on whether the at least one control fuse is cut.

18. The phase-change random access memory of claim 13, wherein the plurality of redundancy data lines are mutually connected through a path logic circuit turned on in response to the input/output repair mode control signal.

19. A phase-change random access memory comprising: a plurality of memory blocks, each of the plurality of memory blocks including a plurality of memory columns corresponding to a same column address and using different input/output paths;a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; anda plurality of input/output repair control circuits arranged corresponding respectively to the plurality of memory blocks, each of the plurality of input/output repair control circuits repairing at least one of the plurality of memory columns according to input/output repair modes using at least one of the plurality of redundancy memory columns, and at least two of the plurality of input/output repair control circuits having different input/output repair modes.

20. The phase-change random access memory of claim 19, wherein the input/output repair modes include ×1, ×2, ×4, ×8, and ×16 modes.

21. The phase-change random access memory of claim 19, wherein the input/output repair modes depend on whether the at least one control fuse is cut.