PHASE DIFFERENCE DETECTOR, PHASE DIFFERENCE DETECTION PROGRAM, AND PLASMA PROCESSING SYSTEM USING THE PHASE DIFFERENCE DETECTOR

Abstract

A phase difference detector detects the phase difference between two AC signals at a high speed and with high accuracy. A phase difference computation unit computes the phase difference φr(=φ2−φ1) between two detected voltages v1 (phase angle: φ1) and v2 (phase angle: φ2). The phase difference computation unit uses a sine wave vs and a cosine wave vc generated separately and having the same frequency as the fundamental frequency of the voltages v1 and v2, to perform computation of v2s=v2×vs, v2c=v2×vc, v1s=v1×vs, v1c=v1×vc, and then extracts DC components I2=(−A2/2)·sin(φ2), R2=(A2/2)·cos(φ2), I1=(−A1/2)·sin(φ1), R1=(A1/2)·cos(φ1) at low-pass filters. The phase difference computation unit computes R3=R1×R2+I1×I2 at a complex multiplying unit to obtain R3=(A1·A2/4)·cos(φr), computes I3=R2×I1−R1×I2 to obtain I3=(A1·A2/4)·sin(φr), and computes φr=tan−1(I3/R3) at the arctangent calculation unit, thereby obtaining the phase difference φr.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a phase difference detector for computing the phase difference between two alternating current signals (AC signals) having the same frequency. The invention also relates to a program for detecting such a phase difference, and to a plasma processing apparatus utilizing such a phase difference detector.

2. Description of the Related Art

Conventionally, a digital computation technique has been known for determining the phase difference between two AC signals of the same frequency. For instance, Japanese Patent No. 3808973 discloses the following method for computing the phase difference between two AC signals: s₁=A₁·cos(ω·t) and s₂=A₂·cos(ω+t+φ), where ω=2π·f, f represents frequency, and φ represents a phase difference from the signal s₁.

(1) A sine (or sinusoidal) wave s₃=cos((ω+ω_o)·t), ω_o=2·π·f_o, having a frequency of (f+f_o)[Hz] (f_o<<f) is generated by using a direct digital synthesizer. Then, the sine wave is multiplied by each of the AC signals s₁ and s₂, whereby the following signals s_a and s_b are obtained.

$\begin{array}{c}{s}_a=s_1\times s_3\\ =A_1·\cos \left(\omega ·t\right)·\cos \left(\left(\omega +w_o\right)·t\right)\\ =\left(A_1/2\right)·\left[\cos \left(\left(2\omega +{\omega }_o\right)·t\right)+\cos \left({\omega }_o·t\right)\right]\end{array}$ $\begin{array}{c}{s}_b=s_2\times s_3\\ =A_2·\cos \left(\omega +t+\phi \right)·\cos \left(\left(\omega +{\omega }_o\right)·t\right)\\ =\left(A_2/2\right)·\left[\cos \left(\left(2\omega +{\omega }_o+\phi \right)·t\right)+\cos \left({\omega }_o·t+\phi \right)\right].\end{array}$

(2) Filtering is performed with respect to the signals s_a and s_b to remove frequency components higher than f_o, thereby extracting low frequency signals s_a(A₁/2)·cos(ω·t) and s_bo=(A₂/2)·cos(ω·t+φ) having the frequency f_o.

(3) The two low frequency signals s_ao and s_bo are transformed into rectangular waves, and by using the reference clock of a direct digital synthesizer, the period T(=1/f_o) and the deviation time t of the rise timings of the two low frequency signals s_ao, s_bo are obtained. By computing 360×(t/T)[°] or 2π×(t/T)[rad], the phase difference φ is obtained. In the above technique for computing phase difference disclosed in U.S. Pat. No. 3,808,973, after detected values of two AC signal s₁ and s₂ having a phase difference φ are converted into low frequency signal s_ao and s_bo, the period T and the deviation time t of the rise timings of the two low frequency signals s_ao and s_bo are measured by using a clock of a reference clock, and then the measured values are used to obtain the phase difference φ.

When the frequency of the reference clock is f_CLK, the period τ of the reference clock is τ=1/f_CLK, and the period T of the low frequency signals s_ao, s_bo is T=1/f_o. Thus, the resolving power N for measuring the period T is N=T/τ=f_CLK/f_o[times/period]. When the resolving power N is converted into a resolving power B in terms of angle, B=360/N=360×f_o/f_CLK[°] or B=2π×f_o/f_CLK[rad]. In this way, since the phase difference φ is computed by using the period T and the phase deviation time t of the low frequency signals s_ao, s_bo in the conventional phase difference computation method, the accuracy of the computation results depends on the resolving power B.

Specifically, when the ratio of the frequencies R_f=f_o/f_CLK is increased, the resolving power B increases, which results in lower detection accuracy. When the ratio Rf is decreased, the resolving power B decreases, which results in higher detection accuracy. Thus, to improve the detection accuracy, it may be considered to set the value of the frequency f_CLK of the reference clock high or to set the value of the frequency f_o low. However, since the speed of a device such as a direct digital synthesizer that uses a reference clock for operation or a counter for measuring the period T or the phase deviation time t cannot be increased beyond a certain limit, the frequency f_CLK cannot be set to a high value as desired.

On the other hand, since the phase difference φ is detected at the period T=1/f_o, setting the frequency f_o low leads to long detection intervals. Thus, in the case where the phase difference φ changes largely when detection is not being performed, the reliability of the detected value is low.

In this way, in the conventional phase difference detection method, the resolving power B depends on the ratio R_f=f_o/f_CLK and the detection period (1/f_o) is a trade-off for the resolving power B (detection accuracy), so that it is difficult to set optimum values for the frequency f_o and the frequency f_CLK of the reference clock.

SUMMARY OF THE INVENTION

The present invention has been conceived in view of the foregoing situation. It is therefore an object of the present invention to provide a phase difference detector and a phase difference detection program that are capable of detecting phase difference between two AC signals at a high-speed and with high accuracy. Another object of the present invention is to provide a plasma processing system that uses such a phase difference detector and a phase difference detection program.

To solve the above-described problem, the present invention takes the following measures.

According to a first aspect of the present invention, there is provided a phase difference detector for detecting a phase difference between a first AC signal and a second AC signal having a same frequency as a fundamental frequency of the first AC signal. The phase difference detector includes a sine wave generator that generates a sine wave signal having the same frequency as the fundamental frequency, a cosine wave generator that generates a cosine wave signal having the same frequency as the fundamental frequency, a first signal multiplier that multiplies the first AC signal and the sine wave signal, a second signal multiplier that multiplies the first AC signal and the cosine wave signal, a third signal multiplier that multiplies the second AC signal and the sine wave signal, a fourth signal multiplier that multiplies the second AC signal and the cosine wave signal, a DC component extraction unit that extracts four DC components by removing an AC component from a result of multiplication in each of the first through the fourth signal multipliers, a trigonometric function computation unit that obtains a sine value and a cosine value of the phase difference by a computation using the four DC components, and a phase difference computation unit that uses the cosine value and the sine value computed by the trigonometric function computation unit to compute arctangent of a ratio of the sine value to the cosine value to obtain the phase difference.

Preferably, when the first AC signal is A₁·cos(2π·f₀·t+φ₁)+h₁(t) (where h₁(t) is sum of harmonic components) and the second AC signal is A₂·cos(2π·f₀·t+φ₂)+h₂(t) (where h₂(t) is sum of harmonic components) the sine wave signal generated by the sine wave generator and the cosine wave signal generated by the cosine wave generator are expressed as sin(2π·f₀·t) and cos(2π·f₀·t) respectively, the four DC components extracted by the DC component extraction unit are expressed as R₁=(A₁/2)·cos(φ₁), I₁=(−A₁/2)·sin(φ₁) R₂=(A₂/2)·cos(φ₂) and I₂=(−A₂/2)·sin(φ₂), and the trigonometric function computation unit computes R₁×R₂+I₁×I₂ to obtain a cosine value expressed as (A₁·A₂/4)·cos(φ_r) (where φ_r=φ₂−φ₁) and computes R₂×I₁−R₁×I₂ to obtain a sine value expressed as (A₁·A₂/4)·sin(φ_r).

Preferably, the sine wave generator and the cosine wave generator are provided by a direct digital synthesizer including a first clock generator that generates a first reference clock, a first frequency retaining unit that retains a value of a fundamental frequency of the first AC signal, a first adder that adds the value of a fundamental frequency retained in the first frequency retaining unit and a result of addition and outputs a result every time a clock pulse of the first reference clock is inputted, and a first waveform storing unit that stores a table of wave height values of predetermined sine waves or cosine waves and outputs a wave height value corresponding to the result of addition every time the result of addition is outputted from the first adder.

According to a second aspect of the present invention, there is provided a computer readable storage medium comprising a phase difference detection program encoded and stored in a computer readable format, where the program is configured to cause a computer to function as a phase difference detector for detecting a phase difference between a first AC signal and a second AC signal having a same frequency as a fundamental frequency of the first AC signal. Specifically, the program causes the computer to function as: a sine wave generator that generates a sine wave signal having the same frequency as the fundamental frequency; a cosine wave generator that generates a cosine wave signal having the same frequency as the fundamental frequency; a first signal multiplier that multiplies the first AC signal and the sine wave signal; a second signal multiplier that multiplies the first AC signal and the cosine wave signal; a third signal multiplier that multiplies the second AC signal and the sine wave signal; a fourth signal multiplier that multiplies the second AC signal and the cosine wave signal; a DC component extraction unit that extracts four DC components by removing an AC component from a result of multiplication in each of the first through the fourth signal multipliers; a trigonometric function computation unit that obtains a sine value and a cosine value of the phase difference by a computation using the four DC components; and a phase difference computation unit that uses the cosine value and the sine value computed by the trigonometric function computation unit to compute arctangent of a ratio of the sine value to the cosine value to obtain the phase difference.

According to a third aspect of the present invention, there is provided a plasma processing system for plasma-processing an object by supplying two high-frequency voltages having a same frequency and a phase difference to a pair of electrodes of a plasma chamber. The system includes a phase difference detector as set forth above, an AC voltage detector that detects AC voltages at respective input ends of the paired electrodes and outputs to the phase difference detector one of voltages detected as the first AC signal and the other one of the voltages detected as the second AC signal, an input unit for inputting control values of the frequency and the phase difference, a computation unit that computes difference between the control value of the phase difference inputted by the input unit and a phase difference detected by the phase difference detector, a first high-frequency instruction signal generator that generates, based on the control value of the frequency, a first high-frequency instruction signal having the frequency and a zero phase angle, a second high-frequency instruction signal generator that generates, based on the control value of the frequency and the difference between phase differences computed by the computation unit, a second high-frequency instruction signal having the frequency and a phase angle of the difference between the phase differences, a first high-frequency generator for outputting, based on the first high-frequency instruction signal, a high-frequency voltage having the frequency of the control value and a zero phase angle to one of the paired electrodes, and a second high-frequency generator for outputting, based on the second high-frequency instruction signal, a high-frequency voltage having the frequency of the control value and a phase angle of the difference between phase differences to the other one of the paired electrodes.

Preferably, the first high-frequency instruction signal generator is provided by a direct digital synthesizer including a second clock generator that generates a second reference clock, a second frequency retaining unit that retains a control value of a frequency inputted by the input unit, a second adder that adds the control value of the frequency retained in the second frequency retaining unit and a result of addition and outputs a result every time a clock pulse of the second reference clock is inputted, a second waveform storing unit that stores a table of wave height values of predetermined sine waves or cosine waves and outputs a wave height value corresponding to the result of addition every time the result of addition is outputted from the second adder, and a first signal converter that converts a wave height value outputted from the second waveform storing unit into an analog signal. Preferably, the second high-frequency instruction signal generator is provided by a direct digital synthesizer including a third frequency retaining unit that retains a control value of a frequency inputted by the input unit, a phase difference retaining unit that retains difference between the phase differences computed by the computation unit, a third adder that adds the control value of the frequency retained in the third frequency retaining unit and a result of addition and outputs a result every time a clock pulse of the second reference clock is inputted, a fourth adder that adds the difference between the phase differences retained in the phase difference retaining unit and a result of addition and outputs a result every time a clock pulse of the second reference clock is inputted, a third waveform storing unit that stores a table of wave height values of predetermined sine waves or cosine waves and outputs a wave height value corresponding to the result of addition every time the result of addition is outputted from the fourth adder, and a second signal converter that converts a wave height value outputted from the third waveform storing unit into an analog signal.

According to the phase difference detector of the present invention, a sine wave signal and a cosine wave signal having the same frequency as the fundamental frequency of the first and the second AC signals are generated. Four products are obtained by multiplying the first AC signal and the sine wave signal, the first AC signal and the cosine wave signal, the second AC signal and the sine wave signal, the second AC signal and the sine wave signal. After four DC components are extracted by removing an AC component from each of the products, the four DC components are subjected to predetermined computation processing, whereby a cosine value and a sine value of the phase difference are obtained. Then, arctangent of a ratio of the sine value to the cosine value is computed, whereby the phase difference is obtained.

For instance, when the first AC signal v₁ is v₁=A₁ cos(2π·f₀·t+φ₁)+h₁(t) (where h₁(t) is the sum of harmonic components) and the second AC signal v₂ is V₂=A₂·cos(2π·f₀·t+φ₂)+h₂(t) (where h₂(t) is the sum of harmonic components), the sine wave signal is expressed as sin(2π·f₀·t), whereas the cosine wave signal is expressed as and cos(2π·f₀·t). Thus, when the computations v_1c=v₁×v_c, v_1s=v₁×v_s, v_2c=v₂×v_c, v_2s=v₂×v_s, are performed and AC components are removed from the computation results v_1c, v_1s, v_2c, and v_2s, the DC component of v_1c R₁=(A₁/2)·cos(φ₁) the DC component of v_1s I₁=(−A₁/2)·sin(φ₁), the DC component of v_2c R₂=(A₂/2)·cos(φ₂) and the DC component of v_2s I₂=(−A₂/2)·sin(φ₂) are obtained.

Then, the cosine value R₃ expressed as (A₁·A₂/4)·cos(φ_r)(φ_r=φ₂−φ₁) is obtained by the computation of R₃=R₁×R₂+I₁×I₂, and the sine value I₃ expressed as (A₁·A₂/4)·sin(φ_r) is obtained by the computation of I₃=I₁×R₂×R₁×I₂. By further computing tan⁻¹ (I₃/R₃), the phase difference φ_r is obtained.

Unlike the conventional phase difference computation method, the process of computing the phase difference φr(=φ₂−φ₁) in the phase difference detector according to the present invention does not include parameters of the period (1/f_o) and the resolving power B (detection accuracy). Thus, the problem that the period (1/f_o) becomes a trade-off for the resolving power B (detection accuracy) is avoided. Thus, the phase difference φ is detected at a high speed and with high accuracy.

In the plasma processing system of the present invention, the actual phase difference between two high frequency voltages applied to a pair of electrodes is detected, and the detection result is fed back so that the phase difference between the high frequency voltages is controlled to a control value. According to this arrangement, the actual phase difference is detected at a high speed and with high accuracy by the phase difference detector of the present invention, so that the actual phase difference between the two high frequency voltages applied to the paired electrodes is stably controlled to a control value. This allows stable control of plasma processing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the structure of a plasma processing system that uses a phase difference detector according to the present invention;

FIG. 2 is a block diagram showing the computing function of a phase difference control unit;

FIG. 3 is a block diagram of a first signal generating unit;

FIG. 4 is a block diagram of a second signal generating unit; and

FIG. 5 is a block diagram showing the internal structure of a phase difference computation unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention are described below with reference to accompanying drawings.

FIG. 1 shows the structure of a plasma processing system that uses a phase difference detector according to the present invention.

The plasma processing system 1 is a system for performing processing such as plasma etching by supplying a high frequency electric power to a processing object such as a semiconductor wafer or a liquid crystal substrate. The plasma processing system 1 is made up of two high-frequency power source unit 2 and 3, two impedance matching apparatuses 4 and 5, two AC voltmeters 6 and 7, a phase difference control unit 8, a plasma chamber 9 as a load, and an input device 10.

The plasma processing system 1 performs plasma processing of a processing object by supplying high frequency voltages having a predetermined phase difference φ to a pair of electrodes 91 and 92 in the plasma chamber 9. The high-frequency power source unit 2 and the impedance matching apparatus 4 constitute a first high-frequency supply unit for supplying a first high-frequency voltage of a frequency f₀ to the first electrode 91. The high-frequency power source unit 3 and the impedance matching apparatus 5 constitute a second high-frequency supply unit for supplying, to the second electrode 92, a second high-frequency voltage of a frequency f₀ which has a shift of a phase difference φ relative to the first high-frequency voltage.

The impedance matching apparatus 4 matches the output impedance of the high-frequency power source unit 4 with the impedance of the plasma chamber 9 (i.e., the load impedance looking from the connection end of the electrode 91 toward the plasma chamber 9 side). Though not illustrated, each of the impedance matching apparatuses 4 and 5 is provided with a mechanism for automatically adjusting a variable reactance element for impedance matching while monitoring the reflection coefficient at the end connected with the high-frequency power source unit 2 or 3. During the plasma processing, the impedance matching apparatus 4, 5 performs automatic matching operation to make the reflection coefficient at the end connected with the high-frequency power source unit 2, 3 as small as possible. Thus, each of the high frequency voltages outputted from the high-frequency power source unit 2, 3 is supplied to the first electrode 91 and the second electrode 92 of the plasma chamber 9, with the power loss reduced as much as possible.

The AC voltmeters 6, 7 and the phase difference control unit 8 use the measured values v₁ and v₂ of the high frequency voltages supplied to the first and the second electrodes 91, 92, and the frequency f₀ and phase difference φ set in the phase difference control unit 8 by external input, to generate a first high-frequency instruction signal S₁ for the high-frequency power source unit 2 and a second high-frequency instruction signal S₂ for the high-frequency power source unit 3 and feed back the high-frequency instruction signals S₁ and S₂ to the high-frequency power source unit 2 and the high-frequency power source unit 3, respectively.

The high-frequency power source unit 2 generates a high frequency voltage v_c1 having an amplitude A₁ based on the first high-frequency instruction signal S₁=cos(2π·f₀·t) inputted from the phase difference control unit 8, and supplies the voltage to the first electrode 91 of the plasma chamber 9 via the impedance matching apparatus 4. Similarly, based on the second high-frequency instruction signal S₂=cos(2π·f₀·t+φ′) (φ′: a value determined such that the difference Δφ between the control value φ and the actual phase difference φ_r gradually approaches 0) inputted from the phase difference control unit 8, the high-frequency power source unit 3 generates a high frequency voltage v_C2 having an amplitude A₂ and supplies the voltage to the second electrode 92 of the plasma chamber 9 via the impedance matching apparatus 4.

By the feedback control using the first and the second high-frequency instruction signals S₁ and S₂ by the AC voltmeters 6, 7 and the phase difference control unit 8, the high frequency voltage supplied to the first electrode 91 of the plasma processing system 1 and the high frequency voltage supplied to the second electrode 92 of the plasma processing system 1 are controlled to respective control values (target values) v₁ and v₂ determined by external input.

Thus, even when a high frequency voltage v_C1 is outputted from the high-frequency power source unit 2, a phase angle φ₁ is generated by the transmission path including the impedance matching apparatus 4 between the high-frequency power source unit 2 and the first electrode 91. Thus, when the loss of amplitude is not taken into consideration, a high frequency voltage v₁=A₁·cos(2π·f₀·t+φ₁) is supplied to the first electrode 91. Similarly, even when a high frequency voltage v_C2 is outputted from the high-frequency power source unit 3, a phase angle φ₂ is generated by the transmission path including the impedance matching apparatus 4 between the high-frequency power source unit 3 and the second electrode 92. Thus, when the loss of amplitude is not taken into consideration, the high frequency voltage v₂=A₂·cos(2π·f₀·t+φ₂) is supplied to the second electrode 92.

The phase difference (actual phase difference) φ_r between the high frequency voltage v₁ and the high frequency voltage v₂ is φ_r=(φ₂−φ₁). The phase difference control unit 8 uses the measured values v₁ and v₂ of the high frequency voltages obtained by the AC voltmeters 6, 7 and a sine wave and a cosine wave generated in it, to compute the difference Δφ=φ−φ_r between the actual phase difference φ_r and the phase difference control value φ. Using the value computed in this way, the phase difference control unit 8 generates a first high-frequency instruction signal S₁ and a second high-frequency instruction signal S₂ and inputs the first high-frequency instruction signal S₁ and the second high-frequency instruction signal S₂ into the first high-frequency power source unit 2 and the second high-frequency power source unit 3, respectively.

The phase difference control unit 8 is made up of a microcomputer including a CPU (central processing unit), a ROM (read only memory) and a RAM (random access memory). The computation of the difference Δφ between phase differences and the generation of the first and the second high-frequency instruction signals S₁ and S₂ are performed by execution of a predetermined program by the microcomputer. The phase difference control unit 8 can be provided by a FPGA (Field Programmable Gate Array).

The phase difference control unit 8 computes the actual phase difference φ_r by a phase difference computation method according to the present invention. Of the phase difference control unit 8, the portion that computes the phase difference φ_r corresponds to the phase difference detector according to the present invention.

The method for computing the actual phase difference φ_r according to the present invention is described below.

The high frequency voltage v₁(t)=A₁·cos(2π·f₀·t+φ₁)+h₁(t) (where h₁(t) represents the sum of harmonic components) detected by the AC voltmeter 6 and the high frequency voltage v₂(t)=A₂·cos(2π·f₀·t+φ₂)+h₂(t) (where h₂(t) represents the sum of harmonic components) detected by the AC voltmeter 7 are subjected to analog-to-digital conversion, whereby discrete-time signals are obtained which are expressed as:

v ₁ [k]=A ₁·cos(2π·f₀·k+φ₁)+h₁[k]

v ₂ [k]=A ₂·cos(2π·f₀·k+φ₂)+h₂[k].

By direct digital synthesizers (DDS), a cosine wave v_c[k]=cos(2π·f₀·k) and a sine wave v_s[k]=sin(2π·f₀·k) of a fundamental wave component of v₁[k] and v₂[k] are generated, and discrete-time signals v_1c[k], v_2c[k], v_1s[k] and v_2s[k] are computed by the computations below:

v _1c [k]=v ₁ [k]×v _c [k]  (1)

v _2c [k]=v ₂ [k]×v _c [k]  (2)

v _1s [k]=v ₁ [k]×v _s [k]  (3)

v _2s [k]=v ₂ [k]×v _s [k]  (4)

Applying the addition theorem of trigonometric functions to the above formulae (1)-(4) gives the following:

v _1c [k]=(A₁/2)·(cos(φ₁)+cos(4π·f₀·k+φ₁))+h₁[k]·cos(2π·f₀·k)  (5)

v _2c [k]=(A₂/2)·(cos(φ₁)+cos(4π·f₀·k+φ₂))+h₂[k]·cos(2π·f₀·k)  (6)

v _1s [k]=(A₁/2)·(−sin(φ₁)+sin(4π·f₀·k+φ₁))+h₁[k]·sin(2π·f₀·k)  (7)

v _2s [k]=(A₂/2)·(−sin(φ₂)+sin(4π·f₀·k+φ₂))+h₂[k]·sin(2π·f₀·k)  (8).

As will be understood from the above formulae (5)-(8), the discrete-time signals v_1c[k], v_2c[k], v_1s[k], v_2s[k] are composite waves of the DC component and the AC components. Thus, subjecting the discrete-time signals v_1c[k] v_2c[k] v_1s[k] and v_2s[k] to filtering for removing AC components (filtering by a low-pass filter) provides four discrete-time signals, which are a sine wave and a cosine wave having a phase angle φ₁, and a sine wave and a cosine wave having a phase angle φ₂. Each of these discrete-time signals has a value that does not relate to the discrete-time (sampling number k).

When a sine wave and a cosine wave having a phase angle φ₁ are R₁=(A₁/2)·cos(φ₁), I₁=(−A₁/2)·sin(φ₁) and a sine wave and a cosine wave having a phase angle φ₂ are R₂=(A₂/2)·cos(φ₂) I₂=(−A₂/2)·sin(φ₂),

$\begin{array}{cc}\begin{array}{c}{R}_3=R_1\times R_2+I_1\times I_2\\ =\left(A_1·A_2/4\right)\left[\cos \left({\phi }_1\right)·\cos \left({\phi }_2\right)+\sin \left({\phi }_1\right)·\sin \left({\phi }_2\right)\right]\\ =\left(A_1·A_2/4\right)·\cos \left({\phi }_2-{\phi }_1\right)=\left(A_1·A_2/4\right)·\cos \left({\phi }_r\right)\end{array}& \left(9\right)\\ \begin{array}{c}{I}_3=R_2\times I_1-R_1\times I_2\\ =\left(A_1·A_2/4\right)\left[-\sin \left({\phi }_1\right)·\cos \left({\phi }_2\right)+\cos \left({\phi }_1\right)·\sin \left({\phi }_2\right)\right]\\ \left(A_1·A_2/4\right)·\sin \left({\phi }_2-{\phi }_1\right)=\left(A_1·A_2/4\right)·\sin \left({\phi }_r\right)\end{array}& \left(10\right)\end{array}$

Since I₃/R₃=tan(φ_r), the phase difference φ_r is obtained by the formula

φ_r=tan⁻¹(I₃/R₃)  (11)

The structure of the phase difference control unit 8 is described below.

FIG. 2 is a block diagram showing the computation function of the phase difference control unit 8.

The phase difference control unit 8 includes a first signal generating unit 81 for generating a first high-frequency instruction signal S₁, a second signal generating unit 82 for generating a second high-frequency instruction signal S₂, a third signal generating unit 83 for generating a cosine wave signal v_c having an output frequency f₀ of the high-frequency power source units 2, 3 which is inputted as a control value from the input device 10, a fourth signal generating unit 84 for generating a sine wave signal v_s having the output frequency f₀, a phase difference computation unit 85 for computing the phase difference φ_r between the high frequency voltage v₁ and the high frequency voltage v₂ detected by the AC voltmeters 6 and 7, an adder 86 for computing the difference Δφ between the phase difference φ inputted as a control value from the input device 10 and the phase difference φ_r computed by the phase difference computation unit 85, and a clock 87 for generating a reference clock.

The phase difference control unit 8 is provided with the input device 10 and a non-illustrated display unit. By using the input device 10 and the display unit, the user can set the frequency f₀ (control value) of the high frequency voltages outputted from the high-frequency power source units 2 and 3 and the phase difference φ (control value) between the output voltage v_c1 from the high-frequency power source unit 2 and the output voltage v_c2 from the high-frequency power source unit 3. For instance, the frequencies often used in plasma processing systems, such as 2.0[MHz] or 13.56[MHz], may be set in the phase difference control unit 8 as the frequency f₀. The frequency f₀ inputted from the input device 10 is inputted into the first through the fourth signal generating units 81-84, and the phase difference φ inputted from the input device 10 is inputted into the adder 86.

The first signal generating unit 81 may be provided by a direct digital synthesizer (DDS) as shown in FIG. 3 as a block diagram.

The DDS is a signal generator including, as its basic structural elements, a look-up table for storing waveform data obtained by sampling wave height values of basic waveforms (such as a sine wave, a triangular wave or a rectangular wave) of one period by predetermined bits, a phase accumulator for generating the phase of a desired frequency at an arbitrary time, and a digital-to-analog converter. The DDS reads out a wave height value corresponding to the phase generated by the phase accumulator from the look-up table to generate the wave height value data of a desired frequency, and subjects the wave height value data to digital-to-analog conversion to generate a signal of a desired frequency.

The first signal generating unit 81 shown in FIG. 3 is basically made up of an adder 811, a frequency setting register 812, a look-up table (LUT) 813 and a digital-to-analog converter 814. The look-up table 813 stores wave height value data of cosine waves by predetermined bits. The digital value of a frequency f_o inputted by the input device 10 is set in the frequency setting register 812.

Every time a clock pulse of a reference clock is inputted from the clock 87 (at the rise time or fall time of a reference clock), the adder 811 adds the value of the frequency f_o set in the frequency setting register 812 and the result of the preceding addition by the adder 811 and outputs the result of addition to the look-up table 813 as address data. Thus, the clock 87, the adder 811 and the frequency setting register 812 function as a phase accumulator.

Every time address data is inputted from the adder 811, the look-up table 813 reads out the wave height value data corresponding to the address data and outputs the wave height value data to the digital-to-analog converter 814. The digital-to-analog converter 814 converts the wave height value data into an analog signal. The analog signal outputted from the digital-to-analog converter 814 is caused to pass through a low-pass filter and an amplifier (not shown) where unnecessary frequency components are removed and the amplitude level is adjusted, and then outputted as a first high-frequency instruction signal S₁. The first high-frequency instruction signal S₁ is expressed as S₁=cos(2π·f₀·t) (amplitude is normalized to 1).

The second signal generating unit 82 may be provided by a direct digital synthesizer (DDS) as shown in FIG. 4 as a block diagram. The DDS shown in this figure includes, as its basic structural elements, adders 821 and 826, a frequency setting register 822, a look-up table (LUT) 823, a digital-to-analog converter 824 and a phase difference setting register 825. The adder 821, the frequency setting register 822, the look-up table 823 and the digital-to-analog converter 824 correspond to the adder 811, the frequency setting register 812, the look-up table 813 and the digital-to-analog converter 814, respectively, of the first signal generating unit 81 and have the same functions as these. Similarly to the frequency setting register 812, the digital value of the frequency f_o inputted by the input device 10 is set in the frequency setting register 822. The look-up table 823 stores the same wave height value data as the look-up table 813.

Thus, the difference of the DSS of the second signal generating unit 82 shown in FIG. 4 from the DDS of the first signal generating unit 81 shown in FIG. 3 is that it additionally includes a phase difference setting register 825 and an adder 826. The difference between phase differences Δφ=φ−φ_r computed by the adder 86 shown in FIG. 2 is set in the phase difference setting register 825. The adder 826 adds the difference Δφ between phase differences, which is set in the phase difference setting register 825, to the result of addition by the adder 822, and outputs the result of addition to the look-up table 823 as address data. Thus, in the second signal generating unit 82, the adders 821 and 826, the frequency setting register 822 and the phase difference setting register 825 function as a phase accumulator.

In the second signal generating unit 82, every time a clock pulse of a reference clock is inputted from the clock 87, the adder 821 adds the value of the frequency f_o set in the frequency setting register 822 and the result of the preceding addition by the adder 821. Further, to the result of this addition by the adder 822, the adder 826 adds the difference 4 between phase differences which is set in the phase difference setting register 825. The adder 826 outputs the result of addition to the look-up table 823 as address data.

The result of the addition by the adder 826 is the sum of the result of addition by the adder 821 and the difference Δφ between phase differences. Thus, the phase of the wave height value data outputted from the look-up table 823 in accordance with the result of the addition by the adder 826 as the address data is delayed by Δφ from the phase of the wave height value data outputted from the look-up table 813 of the first signal generating unit 81. Thus, the second high-frequency instruction signal S₂, which is generated by subjecting the analog signal outputted from the digital-to-analog converter 824 to removal of unnecessary frequency components by a low-pass filter (not shown) and amplitude level adjustment by an amplifier (not shown), is expressed as S₂=cos(2π·f₀·t+Δφ) (amplitude is normalized to 1).

The third signal generating unit 83 is provided by a DDS having a similar structure to the first signal generating unit 81 shown in FIG. 3. The third signal generating unit 83 operates similarly to the first signal generating unit 81 to generate a cosine wave signal v_c. Since the cosine wave signal v_c generated by the third signal generating unit 83 is inputted into the phase difference computation unit 85 and used for the above-described digital computation of the formulae (1) and (2), the DDS of the third signal generating unit 83 does not include a digital-to-analog converter. Thus, in the third signal generating unit 83, the wave height value data outputted from the look-up table is outputted as the cosine wave signal v_c. The cosine wave signal v_c is expressed as v_c[k]=cos(2π·f₀·k) (amplitude is normalized to 1).

The fourth signal generating unit 84 is provided by a DDS having a similar structure to the third signal generating unit 83. The fourth signal generating unit 84 operates similarly to the third signal generating unit 83 to generate a sine wave signal v_s. Since the fourth signal generating unit 84 generates a sine wave signal v_s, wave height value data of sine waves (wave height value data whose phase is delayed by 90° from the cosine waves stored in the look-up table 813) is stored in the look-up table, which is the difference from the third signal generating unit 83. The sine wave signal v_s outputted from the fourth signal generating unit 84 is expressed as v_s[k]=sin(2π·f₀·k) (amplitude is normalized to 1).

The fourth signal generating unit 84 may be provided by a DDS having a similar structure to the second signal generating unit 82. In this case, the same cosine wave height value data as those stored in the look-up table 813 is stored in the look-up table, and appropriate phase difference data for a 90° phase delay is set in the phase difference setting register 825. With this arrangement, the phase data outputted from the adder 821 is delayed by 90° by the phase difference setting register 825 and the adder 826, so that the phase read out from the look-up table 823 is delayed by 90°. Thus, the wave height value of the cosine wave read out from the look-up table 824 substantially becomes the wave height value of a sine wave.

FIG. 5 is a block diagram showing the internal structure of the phase difference computation unit 85 shown in FIG. 2.

The phase difference computation unit 85 includes two analog-to-digital converters 851a and 851b, four multipliers 852a, 852b, 852c and 852d, four low-pass filters 853a, 853b, 853c and 853d, a sign inversion unit 854, a complex multiplying unit 855 and arctangent calculation unit 856. Though not illustrated, a reference clock outputted from a clock that is common to the clocks 811 and 821 is inputted into the phase difference computation unit 85 as well. Based on the reference clock, the phase difference computation unit 85 performs the processing for computing the difference 4c1) between phase differences in synchronism with the wave height value data generation operation by the first through the fourth signal generating units 81-84.

The analog-to-digital converter 851a converts the voltage v₁(t)=A₁·cos(2π·f₀·t+φ₁)+h₁(t) detected by the AC voltmeter 6 into a digital signal detection voltage [k]=A₁·cos(2π·f₀·k+φ₁)+h₁[k]. The analog-to-digital converter 851b converts the voltage v₂(t)=A₂·cos(2π·f₀·t+φ₂)+h₂(t) detected by the AC voltmeter 7 into a digital signal detection voltage v₂[k]=A₂·cos(2π·f₀·k+φ₂)+h₂[k].

The multiplier 852a multiplies the cosine wave signal v_s[k] generated by the fourth signal generating unit 84 with a detection voltage v₂[k] of the AC voltmeter 7 outputted from the analog-to-digital converter 851b to obtain v_2s[k] of the formula (8). The multiplier 852b multiplies the sine wave signal v_c[k] generated by the third signal generating unit 83 with a detection voltage v₂[k] of the AC voltmeter 7 outputted from the analog-to-digital converter 851b to obtain v_2c[k] of the formula (6). The multiplier 852c multiplies the cosine wave signal v_s[k] generated by the fourth signal generating unit 84 with a detection voltage v₁[k] of the AC voltmeter 6 outputted from the analog-to-digital converter 851a to obtain v_1s[k] of the formula (7). The multiplier 852d multiplies the sine wave signal v_c[k] generated by the third signal generating unit 83 with a detection voltage v₁[k] of the AC voltmeter 6 outputted from the analog-to-digital converter 851a to obtain v_1c[k] of the formula (5).

The low-pass filter 853a removes an AC component from the signal v_2s[k] outputted from the multiplier 852a to extract a sine wave I₂=(−A₂/2)·sin(φ₂). The low-pass filter 853b removes an AC component from the signal v_2c[k] outputted from the multiplier 852b to extract a cosine wave R₂=(A₂/2)·cos(φ₂). The cosine wave R₂ outputted from the low-pass filter 853b is inputted as it is into the complex multiplying unit 855. The sine wave I₂ outputted from the low-pass filter 853a is inputted into the complex multiplying unit 855 after its sign is inverted to −I₂ by the sign inversion unit 854.

The low-pass filter 853c removes an AC component from the signal v_1s[k] outputted from the multiplier 852c to extract a sine wave I₁=(−A₁/2)·sin(φ₁). The low-pass filter 853d removes an AC component from the signal v_1c[k] outputted from the multiplier 852b to extract a cosine wave R₁=(A₁/2)·cos(φ₁). The sine wave I₁ and the cosine wave R₁ outputted from the low-pass filters 853c and 853d are inputted into the complex multiplying unit 855.

The complex multiplying unit 855 performs multiplication of complex numbers. That is, when two complex numbers α and β are α=R₁+j·I₁ and β=R₂−j·I₂, α×β=(R₁×R₂+I₁×I₂)+j·(R₂×I₁−R₁×I₂). Thus, the complex multiplying unit 855 performs computation of real part (R₁×R₂+I₁×I₂) and imaginary part (R₂×I₁−R₁×I₂) of α×β. As described above, the real part (R₁×R₂+I₁×I₂) of α×β is the computation of the formula (9), whereas the imaginary part (R₂×I₁−R₁×I₂) of α×β is the computation of the formula (10). Thus, the complex multiplying unit 855 computes R₃ of the formula (9) and I₃ of the formula (10) and inputs the results into the arctangent calculation unit 856.

In the arctangent calculation unit 856, the arithmetic expression of the arctangent tan⁻¹ (I₃/R₃) with the argument (I₃/R₃) is set. The arctangent calculation unit 856 calculates the arctangent by substituting the real part R₃ and the imaginary part I₃ inputted from the complex multiplying unit 855 for the argument of tan⁻¹(I₃/R₃), thereby calculating the phase difference φ_r of the formula (11). The phase difference φ_r calculated by the arctangent calculation unit 856 is inputted into the adder 86. In the adder 86, the difference Δφ=φ−φ_r, i.e., the difference from the phase difference control value φ inputted from the input device 10, is computed. As shown in FIGS. 2 and 4, this computation result is inputted into the phase difference setting register 825 of the second signal computation unit 82.

In the plasma processing system 1 of this embodiment, in starting the system, the phase difference control unit 8 outputs a first high-frequency instruction signal S₁=cos(2π·f₀·t) to the high-frequency power source unit 2 and outputs a second high-frequency instruction signal S₂−cos(2π·f₀·t+Δφ) to the high-frequency power source unit 3.

The high-frequency power source unit 2 outputs a high frequency voltage v_C1 of an amplitude A₁ based on the first high-frequency instruction signal S₁, whereas the high-frequency power source unit 3 outputs a high frequency voltage v_C2 of an amplitude A₂ based on the second high-frequency instruction signal S₂. The high frequency voltage v_c1 outputted from the high-frequency power source unit 2 is supplied to the first electrode 91 of the plasma chamber 9 via the impedance matching apparatus 4. In this process, the phase changes in the impedance matching apparatus 4 or the transmission path between the high-frequency power source unit 2 and the first electrode 91, so that a high frequency voltage v₁=A₁·cos(2π·f₀·t+φ₁) is supplied to the first electrode 91. Similarly, a high frequency voltage v₂=A₂·cos(2π·f₀·t+φ₂) is supplied to the second electrode 92.

The high frequency voltage v₁ supplied to the first electrode 91 and the high frequency voltage v₂ supplied to the second electrode 92 are detected by the AC voltmeters 6 and 7, respectively, and inputted into the phase difference control unit 8. The phase difference control unit 8 uses the detected values of the high frequency voltages v₁, v₂ and the frequency f₀ and phase difference φ set by the input device 10 to perform computation of the above-described formulae (1)-(4). Then, filtering is performed to remove AC components from these computation results to extract DC components only. By conducting computations of the formulae (9)-(11) by using the extracted values, the phase difference φ_r between the high frequency voltage v₁ and the high frequency voltage v₂ is computed.

The phase difference control unit 8 further computes the difference Δφ between the phase value control value φ set from the input device 10 and the actual phase difference and feeds back the difference Δφ to the second signal generating unit 82 for generating a second high-frequency instruction signal S₂. Thus, the second high-frequency instruction signal S₂=cos(2π·f₀·t+Δφ) in which deviation from the control value φ is corrected is generated. The correction processing of the second high-frequency instruction signal S₂ by the phase difference control unit 8 is performed in the period of the reference clock generated by the reference clocks 811, 821. Thus, the phase difference (actual phase difference) φ_r between the first high frequency voltage v₁ supplied to the first electrode 91 and the second high frequency voltage v₂ supplied to the second electrode 92 is stably controlled to the control value φ by the phase difference control unit 8.

As described above, in this embodiment, R₃ corresponding to the real part and I₃ corresponding to the imaginary part of multiplication of two complex numbers α and β are obtained by the formulae (9) and (10), and the phase difference φ_r is obtained by calculating the arctangent shown as the formula (11) by using the values R₃ and I₃. Thus, unlike the conventional phase difference detection method, the problem that the detection period (1/f_o) becomes a trade-off for the resolving power B (detection accuracy) is avoided.

Thus, the phase difference φ_r is detected at a high speed and with high accuracy, and the phase difference between the first high frequency voltage v₁ supplied to the first electrode 91 and the second high frequency voltage v₂ supplied to the second electrode 92 is stably controlled to the control value φ. This assures that stable control of plasma generation between the first electrode 91 and the second electrode 92 is performed at a high speed and with high accuracy.

Although explanation is given in the foregoing embodiment as to the case where the phase difference detector according to the present invention is applied to a phase difference control unit of a plasma processing system in which two high frequency voltages V₁ and V₂ are supplied to the plasma chamber with the same frequency f₀ and a predetermined phase difference φ, the phase difference detector according to the present invention is applicable to systems other than a plasma processing system.

Claims

1. A phase difference detector for detecting a phase difference between a first AC signal and a second AC signal having a same frequency as a fundamental frequency of the first AC signal, the detector comprising: a sine wave generator that generates a sine wave signal having the same frequency as the fundamental frequency;a cosine wave generator that generates a cosine wave signal having the same frequency as the fundamental frequency;a first signal multiplier that multiplies the first AC signal and the sine wave signal;a second signal multiplier that multiplies the first AC signal and the cosine wave signal;a third signal multiplier that multiplies the second AC signal and the sine wave signal;a fourth signal multiplier that multiplies the second AC signal and the cosine wave signal;a DC component extraction unit that extracts four DC components by removing an AC component from a result of multiplication in each of the first through the fourth signal multipliers;a trigonometric function computation unit that obtains a sine value and a cosine value of the phase difference by a computation using the four DC components; anda phase difference computation unit that uses the cosine value and the sine value computed by the trigonometric function computation unit to compute arctangent of a ratio of the sine value to the cosine value to obtain the phase difference.

2. The phase difference detector according to claim 1, wherein: when the first AC signal is A1·cos(2π·f0·t+φ1)+h1(t) (where h1(t) is sum of harmonic components) and the second AC signal is A2·cos(2π·f0·t+φ2)+h2(t) (where h2(t) is sum of harmonic components),the sine wave signal generated by the sine wave generator and the cosine wave signal generated by the cosine wave generator are expressed as sin(2π·f0·t) and cos(2π·f0·t) respectively,the four DC components extracted by the DC component extraction unit are expressed as R1=(A1/2)·cos(φ1) I1=(−A1/2)·sin(φ1), R2=(A2/2)·cos(φ2) and I2=(−A2/2)·sin(φ2) andthe trigonometric function computation unit computes R1×R2+I1×I2 to obtain a cosine value expressed as (A1·A2/4)·cos(φr) (where φr=φ2−φ1) and computes R2×I1−R1×I2 to obtain a sine value expressed as (A1·A2/4)·sin(φr).

3. The phase difference detector according to claim 1, wherein the sine wave generator and the cosine wave generator are provided by a direct digital synthesizer comprising: a first clock generator that generates a first reference clock;a first frequency retaining unit that retains a value of a fundamental frequency of the first AC signal;a first adder that adds the value of a fundamental frequency retained in the first frequency retaining unit and a result of addition and outputs a result every time a clock pulse of the first reference clock is inputted; anda first waveform storing unit that stores a table of wave height values of predetermined sine waves or cosine waves and outputs a wave height value corresponding to the result of addition every time the result of addition is outputted from the first adder.

4. A computer readable storage medium comprising a phase difference detection program encoded and stored in a computer readable format, the program configured to cause a computer to function as a phase difference detector for detecting a phase difference between a first AC signal and a second AC signal having a same frequency as a fundamental frequency of the first AC signal, the program causing the computer to function as: a sine wave generator that generates a sine wave signal having the same frequency as the fundamental frequency;a cosine wave generator that generates a cosine wave signal having the same frequency as the fundamental frequency;a first signal multiplier that multiplies the first AC signal and the sine wave signal;a second signal multiplier that multiplies the first AC signal and the cosine wave signal;a third signal multiplier that multiplies the second AC signal and the sine wave signal;a fourth signal multiplier that multiplies the second AC signal and the cosine wave signal;a DC component extraction unit that extracts four DC components by removing an AC component from a result of multiplication in each of the first through the fourth signal multipliers;a trigonometric function computation unit that obtains a sine value and a cosine value of the phase difference by a computation using the four DC components; anda phase difference computation unit that uses the cosine value and the sine value computed by the trigonometric function computation unit to compute arctangent of a ratio of the sine value to the cosine value to obtain the phase difference.

5. A plasma processing system for plasma-processing an object by supplying two high-frequency voltages having a same frequency and a phase difference to a pair of electrodes of a plasma chamber, the system comprising: a phase difference detector as set forth in claim 1;an AC voltage detector that detects AC voltages at respective input ends of the paired electrodes and outputs to the phase difference detector one of voltages detected as the first AC signal and the other one of the voltages detected as the second AC signal;an input unit for inputting control values of the frequency and the phase difference;a computation unit that computes difference between the control value of the phase difference inputted by the input unit and a phase difference detected by the phase difference detector;a first high-frequency instruction signal generator that generates, based on the control value of the frequency, a first high-frequency instruction signal having the frequency and a zero phase angle;a second high-frequency instruction signal generator that generates, based on the control value of the frequency and the difference between phase differences computed by the computation unit, a second high-frequency instruction signal having the frequency and a phase angle of the difference between the phase differences;a first high-frequency generator for outputting, based on the first high-frequency instruction signal, a high-frequency voltage having the frequency of the control value and a zero phase angle to one of the paired electrodes; anda second high-frequency generator for outputting, based on the second high-frequency instruction signal, a high-frequency voltage having the frequency of the control value and a phase angle of the difference between phase differences to the other one of the paired electrodes.

6. The plasma processing system according to claim 5, wherein: the first high-frequency instruction signal generator is provided by a direct digital synthesizer comprising: a second clock generator that generates a second reference clock,a second frequency retaining unit that retains a control value of a frequency inputted by the input unit,a second adder that adds the control value of the frequency retained in the second frequency retaining unit and a result of addition and outputs a result every time a clock pulse of the second reference clock is inputted,a second waveform storing unit that stores a table of wave height values of predetermined sine waves or cosine waves and outputs a wave height value corresponding to the result of addition every time the result of addition is outputted from the second adder, anda first signal converter that converts a wave height value outputted from the second waveform storing unit into an analog signal,the second high-frequency instruction signal generator is provided by a direct digital synthesizer comprising:a third frequency retaining unit that retains a control value of a frequency inputted by the input unit,a phase difference retaining unit that retains difference between the phase differences computed by the computation unit;a third adder that adds the control value of the frequency retained in the third frequency retaining unit and a result of addition and outputs a result every time a clock pulse of the second reference clock is inputted,a fourth adder that adds the difference between the phase differences retained in the phase difference retaining unit and a result of addition and outputs a result every time a clock pulse of the second reference clock is inputted,a third waveform storing unit that stores a table of wave height, values of predetermined sine waves or cosine waves and outputs a wave height value corresponding to the result of addition every time the result of addition is outputted from the fourth adder, anda second signal converter that converts a wave height value outputted from the third waveform storing unit into an analog signal.