The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with integrated, light focusing elements and methods of manufacture.
A photodiode is a semiconductor device that converts light into an electrical current. Photodiodes may contain optical filters, built-in lenses, and may have large or small surface areas depending on the specific application. Photodiodes can be used in many different optical applications. For example, germanium (Ge) photodiodes can be used for state of the art LIDAR applications due to their higher absorption compared to silicon (Si). In this way, smaller pixel size and active area can be realized. In such implementations, signal to noise (S/N) ratio is reduced by inefficient coupling to the absorber and cross-talk is increased with a smaller pitch.
A microlens can be used to focus light into the photodiode material. The microlens, though, is separated from the absorber by a non-absorbing optical path (e.g., polymer microlens in back end of the line (BEOL) stack). This can result in loss or degradation of the light, in addition to requiring extra fabricating steps which add to the overall cost of the structure.
In an aspect of the disclosure, a structure comprises: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.
In an aspect of the disclosure, a structure comprises: a trench photodiode extending into a well region of a semiconductor substrate and comprising a domed structure at its upper end; a doped material on the domed structure extending to a side of the trench photodiode; a first contact in electrical contact with the doped material; and a second contact in electrical contact with the well region of the semiconductor substrate.
In an aspect of the disclosure, a method comprises: forming a trench photodiode in a trench structure, the trench photodiode comprising an integrated domed structure; forming a doped material on the integrated domed structure and extending to a side of the trench photodiode, the doped material having a concave underside surface; and forming a contact in electrical contact to the doped material on the side of the trench photodiode.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with integrated, light focusing elements and methods of manufacture. More specifically, the present disclosure is directed to deep trench photodiodes with an aligned light focusing elements. In embodiments, the deep trench photodiode is a deep trench Ge photodiode and the light focusing element is aligned with the deep trench photodiode. The light focusing element includes a domed structure fully integrated with and using the same material as the deep trench photodiode. Advantageously, the integrated focusing element enables small active area pixel arrays with improved signal to noise (S/N) ratio and isolation.
In embodiments, the photodiode is a trench photodiode with a domed structure (e.g., convex) fully integrated and aligned with the photodiode, itself. The domed structure is covered by a doped polysilicon material and an optional dielectric material, e.g., SiN, resulting in a concave layered structure over the domed structure. The combination of the domed structure and concave material(s) result in a focusing element aligned to the trench photodiode or pixel element. That is, the focusing element comprises a combination of polysilicon material, dielectric material, and the domed structure, with the dielectric and polysilicon materials having a concave, underside surface and the domed material having a convex, upper surface.
In embodiments, the trench photodiode and domed structure comprise Ge based material. Also, the photodiode is provided in a doped well region formed in bulk Si material. The polysilicon material can be doped with an opposite polarity from the doped well region of the bulk Si material; although other doping arrangements are also contemplated herein as described below. The poly silicon material extends to a side of the photodiode for contact formation to the photodiode. In this way, the contact will not be directly over the photodiode and, hence, does not block light from entering into the photodiode. In alternative implementations, though, the contact can be directly on the domed structure. In further embodiments, the domed structure can be surrounded by shallow trench isolation material, over the doped well region. An array of focusing elements can also be provided.
The photodiode structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the photodiode structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the photodiode structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
The shallow trench isolation structures 14 can be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over the semiconductor substrate 12 is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to form one or more trenches in the semiconductor substrate 12 through the openings of the resist. Following the resist removal by a conventional oxygen ashing process or other known stripants, insulator material, e.g., SiO2, can be deposited in the trenches by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual insulator material on the surface of the semiconductor substrate 12 can be removed by conventional chemical mechanical polishing (CMP) processes.
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To perform the ion implantation process, a patterned implantation mask is used to define selected areas exposed for the implantations. The implantation mask may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. the implantation masks has a thickness and stopping power sufficient to block masked areas against receiving a dose of the implanted ions. The implantation mask used to select the exposed area for forming the well region 16 is stripped after implantation.
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In embodiments, the epitaxial growth process can be modulated to include a domed structure 24 of the epitaxial semiconductor material 22. In embodiments, the domed structure 24 is convex and fully integrated and aligned with the trench photodiodes, e.g., epitaxial semiconductor material 22, as shown by the dashed lines. The alignment may be a result of growing the domed structure 24 and the epitaxial semiconductor material 22 of the trench photodiodes within the same deep trench, e.g., both of which extend to the same sidewalls of the deep trench as shown by the dashed lines. As the domed structure 24 is epitaxially grown with the material from the epitaxial semiconductor material 22, the domed structure aligns itself with the sidewalls of the trench and becomes fully integrated with the epitaxial semiconductor material 22 in the deep trench.
Similar to the epitaxial semiconductor material 22, from a top down view, the domed structure 24 can take on the shape of the deep trenches 20, e.g., circular, square, rectangular, oval, diamond, etc. The epitaxial semiconductor material 22 and integrated domed structure 24 can be Ge material; although other highly light absorbing material compounds are also contemplated herein. For example, other materials include, but are not limited to, SiGe, SiGeSn or GeSn. In further embodiments, the epitaxial semiconductor material 22 and integrated domed structure 24 can be doped with boron, in an in-situ process (or, in further embodiments, any p- or n-type dopant).
The domed structure 24 will be used to form a fully integrated, focusing element that is aligned with the photodiode material 22. And, by growing the domed structure 24 of the epitaxial semiconductor material directly on the photodiode material 22, the domed structure 24 will self-align to the photodiode material 22, hence being a fully integrated, self-aligned focusing element. The domed structure 24 can be optimized through the epitaxial growth process by modulating the pressure, relationship of growth time to pixel dimensions and/or temperature parameters. For example, pressures in the range of 1 μT to 760 T and temperatures in the range of 100° C. to 900° C. This pressure and temperature range contemplates a full range of UHVCVD, RP-CVD, and molecular-beam epitaxy (MBE) growth processes, as is known in the art. In further embodiments, the epitaxial growth process can result in the domed structure 24 being at, below or above a surface of the shallow trench isolation structures 14. Alternatively, the domed structure 24 can be provide by a crystallographic etch process after the epitaxial growth process.
The polysilicon material 26 can be deposited by a CVD process or plasma vapor deposition (PVD) process (both of which can include in-situ doping) to a thickness of about 50 nm to 2 microns, although other dimensions are contemplated herein. The deposition of the polysilicon material 26 over the domed structure 24 results in a concave underside surface 26a, directly over and in contact with the domed structure 24.
Following the deposition process, the polysilicon material 26 is subjected to a patterning process through a conventional lithography and etching process with a selective chemistry. The patterning process leaves polysilicon material 26 extending on a side of the photodiode material 22. The polysilicon material 26 extending to the side of the photodiode material 22 may have a planar surface used for contact formation to the photodiode material 22. In this way, a contact can be on the side of the photodiode and not interfere or block light entering into the photodiode.
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For example, after deposition of dielectric materials 30, 32, 34, 36, a trench is formed in these materials by lithography and etching processes. The dielectric materials 30, 32, 34, 36 can be any anti-reflective materials such as a combination of SiO2 and SiN3 in various sequences and orders used in BEOL stacks as should be known to this of skill in the art. The first dielectric material 30, e.g., SiO2, can also have a concave underside surface, with a top planar surface. The remaining layers 32, 34, 36 may have planar surfaces. A conductive material, e.g., aluminum or tungsten, can be deposited within the trenches to form the contacts 38. Any excess conductive material can be removed by a CMP process.
The photodiode with focusing structures can be utilized in system on chip (SoC) technology. It should be understood by those of skill in the art that SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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