Patent Application
20080014511
The accompanying figures are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the figures:
Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.
In the specification, the dimensions of layers and regions are exaggerated for clarity of illustration. It will also be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Also, though terms like a first, a second, and a third are used to describe various regions and layers in various embodiments of the present invention, the regions and the layers are not limited to these terms. These terms are used only to tell one region or layer from another region or layer. Therefore, a layer referred to as a first layer in one embodiment can be referred to as a second layer in another embodiment. An embodiment described and exemplified herein includes a complementary embodiment thereof.
Referring to
In the current embodiment of the present invention, the photomask includes prototype patterns for forming a semiconductor device, and the photoresist pattern, the upper pattern, and the vernier overlay mark are formed using the prototype patterns by photolithography or patterning. Here, the photoresist pattern includes a photoresist overlay pattern defining the vernier overlay mark.
In the current embodiment of the present invention, an overlay accuracy between the photoresist pattern and the lower pattern is measured by comparing the positions of the photoresist overlay pattern and the main overlay mark in operation S30. As described above, the overlay accuracy is measured based on a region having a proper line width in consideration of various process conditions. The photomask of the current embodiment includes an overlay pattern, and the overlay pattern includes regions that have different widths and are sequentially connected to one another. Therefore, the photomask is not required to have excessively many overlay patterns, and thus the problem with the related art does not occur in the current embodiment of the present invention. The photomask of the present invention will be described later in more detail with reference to
In operation S35, it is determined whether a measured overlay accuracy value OL1 before etching is less than an allowable accuracy value OL0. If the measured overlay value OL1 before etching is not less than the allowable accuracy value OL0, the photoresist pattern is removed in operation S60. Then, a re-work operation is performed to form a photoresist pattern again. On the other hand, if the measure overlay value OL1 before etching is less than the allowable accuracy value OL0, the upper layer is patterned in operation S40 as described above.
In operation S45, the position of the vernier overlay mark formed in operation S40 is compared with the position of the main overlay mark to measure an overlay accuracy value OL2 between the lower pattern and the upper pattern formed in operation S40. Like in operation S30 where the overlay accuracy OL1 is measured, a region having a proper line width is selected based on experience or theory for precise measurement in operation S70. In the current embodiment of the present invention, since the main overlay mark or the vernier overlay mark includes regions having various line widths, a desired line width may be easily selected from the line widths of the regions of the main overlay mark or the vernier overlay mark (this will be described later in more detail with reference to
Meanwhile, the lower pattern and the main overlay mark are formed by patterning using the same photomask as that used for forming the photoresist pattern in operation S25. Thus, the main overlay mark has the same shape-related characteristics as the overlay mark of the photomask that will be described with reference to
Referring to
The chip regions 110 and the scribe lane region 130 are regions where prototype patterns are formed. Patterns corresponding to the prototype patterns will be formed in a wafer through an exposure process (that is, the prototype patterns will be transferred to a wafer through an exposure process). Prototype patterns for semiconductor chips are formed in the chip regions 110. The photomask 100 may includes a plurality of chip regions as shown in
In a final sawing process, the chip regions 110 are separated based on the scribe lane region 130. For this, the scribe lane region 130 is formed among the chip regions 110 and the shading region 120. The scribe lane region 130 may include at least one overlay mark 131, at least one test pattern region 132, and at least one monitoring pattern region 133. As explained above, the overlay mark 131 is used to measure an overlay accuracy between lower and upper patterns that are formed using different photomasks. In the test pattern region 132, test patterns may be disposed for indirectly evaluating electrical characteristics of a semiconductor chip. In the monitoring pattern region 133, monitoring patterns may be disposed to monitor a semiconductor manufacturing process.
The shading region 120 is formed around the chip regions 110 and the scribe lane region 130 for blocking light during an exposure process. In the current embodiment of the present invention, at least on alignment mark 125 is formed in the shading region 120. The alignment mark 125 may be used to align the photomask 100 with an exposing stage or a wafer (formed with a lower pattern). In another embodiment of the present invention, the alignment mark 125 may be formed in the scribe lane region 130.
In the following description, exemplary structures of the overlay mark 131 will be illustrated with reference to
Referring to
In the current embodiment, the sub-overlay mark 200 has a stepped shape, and the unit regions a, b, c, d, and e of the sub-overlay mark 200 increase in width as it goes from one end P1 to the other end P2 (|Wi+1−Wi|>0). Approximately, each of the unit regions a, b, c, d, and e has a rectangular shape. That is, although the unit regions a, b, c, d, and e are different in width, the width of a given unit region is constant. Owing to this local constancy of width, overlay accuracy may be easily measured. In other words, when the width of the sub-overlay mark 200 varies linearly, it may be difficult to select a portion of the sub-overlay mark 200 having a desired width. However, in the current embodiment of the present invention, the width of the sub-overlay mark 200 varies in a step-by-step manner, such that a portion of the sub-overlay mark 200 having a desired width can be easily selected. For example, a desired width may be selected from the unit regions a, b, c, d, and e by counting the order of the unit regions a, b, c, d, and e.
Each of the widths W1, W2, W3, W4, and W5 of the unit regions a, b, c, d, and e of the sub-overlay mark 200 may range from 0.1 μm to 100 μm, and a width difference (Wi+1−Wi) may range from 0.1μ to 1 μm. In a well-known scale-down exposure method, a photoresist pattern formed on a wafer may be smaller than a prototype pattern of a photomask. That is, the size of an overlay mark formed on a wafer may be determined by the product of the size of the sub-overlay mark 200 and the magnification of an exposure apparatus. In an embodiment of the present invention, the sub-overlay mark 200 may include ten unit regions each having a width in the range from 0.3 μm to 3 μm. In this case, a width difference of the unit regions may be 0.3 μm (i.e., Wi+1−Wi=0.3 μm where i=1, 2, through to 10).
In the present invention, the overlay mark 131 may have a closed-line shape with a plurality of sides. Here, at least one of the sides of the overlay mark 131 includes a sub-overlay mark 200 like that illustrated in
In other embodiments of the present invention, the overlay mark 131 may have a rectangular close-line shape with eight sub-overlay marks 200 as shown in
In other embodiments of the present invention, the overlay mark 131 may include branches running outward from a center point P3. For example, the overlay mark 131 may include four branches running outward from the center point P3. In this case, as shown in
In other embodiments of the present invention, the overlay mark 131 may include a plurality of parallel sub-overlay marks as shown in
As described above, according to the present invention, the overlay mark of the photomask includes at least one sub-overlay mask, and the sub-overlay mask includes a plurality of unit regions having different widths. Therefore, when the photomask of the present invention is used in a process of manufacturing a semiconductor device, overlay accuracy may be easily measured in spite of various process conditions without increasing the number of overlay marks.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-65990 | Jul 2006 | KR | national |
