Patent Application
20200072889
Modern automobiles include various electronic control units (ECUs) that implement, for example, engine control, power train control, airbag systems, antilock brake systems, cruise control, electric power steering, audio systems, window control systems, door control systems, mirror adjustment systems, and battery and recharging systems for hybrid/electric cars. The ECUs communicate with each other in an automobile via in-vehicle network (IVN) technologies such as Ethernet, Controller Area Network (CAN), and FlexRay.
Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations at a network node in a communications network is disclosed. In an embodiment, the method involves identifying a fault status at the network node, embedding an indication of the fault status into a bit stream at the physical layer of the network node, and transmitting the bit stream from the network node.
In an embodiment, embedding an indication of the fault status into a bit stream at the physical layer includes embedding an operations, administration, and management (OAM) word into the bit stream to communicate the indication of the fault status.
In an embodiment, the OAM word is embedded into the bit stream at a physical coding sublayer transmitter (PCS-TX) of the network node.
In an embodiment, identifying a fault status at the network node includes detecting a low voltage condition at the physical layer.
In an embodiment, identifying a fault status at the network node includes detection an open/short circuit condition at the physical layer.
In an embodiment, identifying a fault status at the network node includes performing a loop test at the network node.
In an embodiment, identifying a fault status at the network node includes reading a register at the physical layer that indicates a status of a microcontroller.
In an embodiment, identifying a fault status at the network node includes evaluating data bits at the physical layer to determine a status of a microcontroller.
In an embodiment, determining a fault status of the microcontroller of the network node includes reading a register bit at the physical layer of the network node.
In an embodiment, determining a fault status of the microcontroller of the network node includes reading a register bit at the physical layer that is set by a layer higher than the physical layer.
In an embodiment, the method further involves receiving the bit stream at a receiver of the second network node, extracting the indication of the fault status from the bit stream, configuring the second network node using the indication of the fault status, and operating the second network node as configured using the indication of the fault status.
An embodiment of a physical layer (PHY) device for a communications network is disclosed. The device includes a transmitter configured to transmit a bit stream from the PHY device, a receiver configured to receive a bit stream at the PHY device, and fault status logic configured to identifying a fault status at a first network node, and provide an indication of the identified fault status to the transmitter.
In an embodiment, the transmitter is configured to embed an operations, administration, and management (OAM) word into a bit stream before transmission of the bit stream, the OAM word including the indication of the fault status provided by the fault status logic.
In an embodiment, the PHY device further includes a low voltage detector configured to detect a low voltage condition in the PHY device and to provide an indication of the low voltage condition to the fault status logic.
In an embodiment, the PHY device further includes an open/short circuit detection circuit configured to detect an open/short circuit condition in the PHY device and to provide an indication of the open/short circuit condition to the fault status logic.
In an embodiment, the PHY device further includes a loopback testing circuit and wherein the fault status logic includes a register for storing a result of a loopback test that is performed using the loopback testing circuit.
In an embodiment, the fault status logic includes a register for storing a result of a loopback test that is performed using the transmitter and the receiver of the PHY device.
In an embodiment, the fault status logic includes a register for storing a microcontroller status, wherein the register can be set to indicate a fault status of the microcontroller.
In an embodiment, the fault status logic includes a microcontroller evaluation circuit configured to evaluate a fault status of a microcontroller.
Other aspects in accordance with the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention.
Throughout the description, similar reference numbers may be used to identify similar elements.
It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.
Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.
Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases “in one embodiment”, “in an embodiment”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
In some embodiments, the microcontrollers 108 are connected to at least one device (not shown) such as a sensor, an actuator, or some other control device and are programmed to determine the meaning of received messages and to generate appropriate outgoing messages. In some embodiments, at least one of the microcontrollers includes a host (not shown), which may include, for example, a software application that is stored in memory of the microcontroller and executed by processing circuits of the microcontroller. The microcontrollers, also referred to as host processors, hosts, or digital signal processors (DSPs), are known in the field. In an embodiment, the microcontrollers 108 implement data link layer (i.e., Layer 2) operations as is known in the field, which in an Ethernet-based network may include Logical Link Control (LLC) sublayer operations and/or media access control (MAC) sublayer operations. For example, in a receive operation, a microcontroller stores received serial bits from a corresponding transceiver 110. In a transmit operation, the microcontroller may transmit a message as serial bits in a data frame format to the corresponding transceiver. The microcontrollers may be implemented as, for example, digital signal processors (DSPs) and/or central processing units (CPUs).
The transceivers 110 are located between the microcontrollers 108 and the communications medium 106 and implement physical layer operations. For example, in receive operations, the receivers 114 convert analog signals from the communications medium to digital signals that a corresponding microcontroller can interpret. In an embodiment, the receivers 114 include a DSP to process incoming signals. The transceiver also can protect the microcontroller from extreme electrical conditions on the communications medium, e.g., electrical surges. In transmit operations, the transmitters 112 convert digital bits received from the microcontroller into analog signals that are sent on the communications medium. The transceivers may be any suitable type of transceivers. In some embodiments, the transceivers are Ethernet transceivers. For example, the transceivers may be Institute of Electrical and Electronics Engineers (IEEE) 802.3 compatible Ethernet transceivers. The transceivers may be implemented in suitable analog circuits and/or digital circuits.
In the communications network 100 depicted in
At the physical layer, encoding, such as Forward Error Correction (FEC) encoding, has been used to improve the quality of point-to-point communications across an Ethernet link, for example, to improve the Bit Error Rate (BER) or to meet a minimum BER requirement. At the physical layer, the receivers typically include a decoder, e.g., digital decoder that is implemented in a DSP. The decoder includes processing blocks (e.g., processing blocks of the DSP) for bit decoding and for error detection and correction. DSP processing blocks for bit decoding include, for example, an equalizer block, an echo cancellation block, an automatic gain control (AGC) block, a clock data recovery (CDR) block, and/or a baseline wander (BLW) block. DSP processing blocks for error detection and error correction include, for example, a syndrome calculation block, an error location block, and an error correction block.
In automotive in-vehicle networks, various faults may occur that may inhibit communications between ECUs. Faults may occur within an ECU, including faults that occur at the physical layer (e.g., in the PHY device or PHY chip) and faults that occur at higher layers (e.g., in a microcontroller) and/or faults may occur in the connectors that connect ECUs to the communications medium and faults may occur on the communications medium itself. Faults that may occur at the physical layer (e.g., within a PHY device or PHY chip) include, for example, low voltage faults and open/short circuit faults in the electronics of the physical layer circuits. Faults that may occur at higher layers include failure of the microcontroller that supports higher layer operations. Faults that may occur in the connectors and communications medium include, for example, damaged or broken connectors and/or damaged or broken communications wires.
In accordance with an embodiment of the invention, a technique for performing physical layer operations at a network node in a communications network involves identifying a fault status at the network node, embedding an indication of the fault status into a bit stream at the physical layer of the network node, and transmitting the bit stream from the network node. Identifying a fault status and embedding the fault status into a bit stream at the physical layer of the network node enables a physical layer device to share its fault status with another physical layer device in the communications network. Since the fault status of a physical layer device is shared with another physical layer device, a physical layer device may be able to take some action based on the shared knowledge of the fault status. For example, a node may chose to operate in a fail safe mode (e.g., a low data rate mode) or a node may notify other nodes in the network of the fault status. In an embodiment, embedding an indication of the fault status into a bit stream at the physical layer involves embedding an operations, administration, and management (OAM) word into the bit stream to communicate the indication of the fault status. For example, in an Ethernet network, the OAM word is embedded into the frame at a physical coding sublayer transmitter (PCS-TX) of the first network node. Some types of faults for which it is desirable to be able to share a fault status with other nodes in a network include, for example, a low voltage condition at the physical layer, an open/short circuit condition at the physical layer, a faulty microcontroller, or problems with a connector or cable that supports communications between nodes. For example, with respect to a low voltage condition, a fault status may be low voltage condition=YES or low voltage condition=NO. In another embodiment, a fault status may be simply an indication of “low voltage condition.” In an embodiment, a fault status is shared at the physical layer as a fault code, which is generated by the control logic, then encoded into a few OAM bits, and then decoded back to a fault code that can be understood by the control logic. Examples of techniques for identifying such faults are described in more detail below.
As described above, the technique for performing physical layer operations in a communications network involves utilizing an OAM word in an FEC frame.
In operation (described from transmission to reception), a bitstream is received at node A 302 (e.g., at a PHY chip) via the XGMII 383 and passed to the NB/NB+1 encoder 384 for NB/NB+1 bit encoding. The NB/NB+1 encoded bits are then combined with OAM bits and parity bits at the multiplexer to form FEC frames. In an embodiment, OAM bits that indicate a fault status (e.g., a low voltage condition or an open/short circuit condition) are received from the fault status logic 387 as indicated in
In an embodiment, the nodes may not implement FEC on the bit streams that are communicated across the physical link.
In operation (described from transmission to reception), a bit stream is received at node A 302 (e.g., at a PHY chip) via the XGMII 383 and passed to the NB/NB+1 encoder 384 for NB/NB+1 bit encoding. The NB/NB+1 encoded bits are then combined with OAM bits to form the bit stream that will be transmitted across the physical link. In an embodiment, OAM bits that indicate a fault status (e.g., a low voltage condition or an open/short circuit condition) are received from the fault status logic 387 as indicated in
With reference to node A, 402, the PHY chip 495 includes a transceiver 410 that includes a physical coding sublayer transmitter (PCS-TX) 451, a physical medium attachment transmitter (PMA-TX) 489, a physical coding sublayer receiver (PCS-RX) 453, a physical medium attachment receiver (PMA-RX) 490, fault status logic 487, a MII 483 (e.g., XGMII), and an MDIO 455. In the embodiment of
In the embodiment of
In an embodiment, the encode OAM module 434 of the fault status logic 487 is configured to encode information received from the control logic 432 into OAM bits. For example, the encode OAM module is configured to encode an indication of a fault status into an OAM word according to OAM encoding rules. For example, an indication that a low voltage condition exists at the PHY device may be encoded into an 8-bit OAM word.
In an embodiment, the OAM-TX module 436 of the fault status logic 487 is configured to buffer the encoded OAM bits (e.g., as an OAM word) before the encoded OAM bits are embedded into the payload field of an FEC frame. For example, an OAM word is embedded into a stream of data that makes up the payload of an FEC frame. In an embodiment, the OAM-TX module includes a buffer for temporarily storing the OAM bits before the OAM bits are embedded into the payload field of an FEC frame.
In an embodiment, the OAM-RX module 438 of the fault status logic 487 is configured to buffer encoded OAM bits (e.g., as an encoded OAM word) that have been extracted from the payload field of an FEC frame. For example, an OAM word is extracted from a stream of data that makes up the payload. In an embodiment, the OAM-RX module includes a buffer for temporarily storing the extracted encoded OAM word.
In an embodiment, the decode OAM module 440 of the fault status logic 487 is configured to decode the encoded OAM word that is extracted from the payload field of the FEC frame and to pass the decoded information to the control logic 432. For example, the decode OAM module is configured to decode the OAM word to information that is understood by the control logic. For example, an 8-bit OAM word is decoded into information, which is understood by the control logic, to notify the receiving network node that a fault was identified at the transmitting network node. In an embodiment, the encode OAM module and the decode OAM module encode and decode according to a complementary set of encoding and decoding rules.
In an embodiment, the control logic 432 of each node controls the operation of the fault status logic 487. For example, the control logic enables a node to share its fault status information with other nodes in the network. In an example, the two nodes are able to share fault status information so that the nodes can take a desired action.
In an embodiment, the voltage detection circuit 452 is a circuit in the PHY chip 495 that is able to detect a voltage condition, e.g., a low voltage condition or a high voltage condition in the PHY chip. Voltage detection circuits, including high voltage detection circuits and low voltage detection circuits are known in the field. In an embodiment, the voltage detection circuit provides an output to the fault status logic. In one embodiment, the output of the voltage detection circuit indicates that the voltage is below a desired voltage, e.g., a low voltage condition. An example implementation of a voltage detection circuit is described with reference to
In an embodiment, the open/short circuit detection circuit 454 is a circuit in the PHY chip 495 that is able to detect an open circuit or short circuit condition in the PHY chip. Open circuit or short circuit detection circuits are known in the field. In an embodiment, the open/short circuit detection circuit provides an output to the fault status logic. In one embodiment, the output of the open/short circuit detection circuit indicates that an open or short circuit exists in the PHY chip. For example, the output of the open/short circuit detection circuit indicates that an undesirable open or short circuit exists in the PHY chip. In an embodiment, the open/short circuit detection circuit may be configured to detect an open/short circuit by measuring transmission line parameters such as the line impedance, the reflected signal strength, and/or the transmitted signal strength. An example implementation of a voltage detection circuit is described with reference to
In an embodiment, the microcontroller fault module 450 is a circuit and/or logic in the PHY chip 495 that provides an indication that a microcontroller is faulty. In an embodiment, the microcontroller fault module may be a register that gets set by a higher layer in the network node when a fault condition in the microcontroller is identified. In another embodiment, the microcontroller fault module includes logic circuits to determine, at the physical layer, that there is some fault associated with the microcontroller. For example, the faulty microcontroller may be configured to evaluate the bits of data that are provided to the transceiver through the (XG)MII 483 and/or evaluate the bits of data that are decoded on the communications link 406 to identify a fault associated with the microcontroller. In one embodiment, the output of the microcontroller fault module indicates that the microcontroller of the network node has some fault condition. An example implementation of the microcontroller fault module is described with reference to
In an embodiment, the loopback testing circuit 456 is a circuit in the PHY chip 495 that provides circuitry to enable loopback testing of the circuit at the PHY layer. For example, the loopback testing circuitry may include splitters, combiners, demultiplexers, and/or multiplexers that enable signals to be looped back within the PHY chip. Loopback testing circuitry for PHY chip is known in the field. In an embodiment, loopback testing is controlled at a higher layer than the physical layer. For example, loopback testing is controlled at layer 2 or at the application layer. In an embodiment, the results of loopback testing is provided to the register 430 of the fault status logic 487 from a higher layer through the MDIO 455. Loopback testing of the physical layer components may involve internal loopback testing, external loopback testing, and/or remote loopback testing. Techniques for implementing loopback testing of physical layer components such as internal loopback testing, external loopback testing, and/or remote loopback testing are known in the field. Example implementations of loopback testing are described with reference to
In an example of a transmission operation, the control logic 432 of the fault status logic 487 identifies information about fault status. For example, the control logic obtains information about a fault status from at least one of the register 430, the microcontroller fault module 450, the voltage detection circuit 452, the open/short circuit detection circuit 454, or the loopback testing circuit 456. The control logic is configured to evaluate the information to determine if information about a fault status should be shared with another node. The desired fault status information that is determined by the control logic can be provided to the encode OAM module 434, wherein the desired fault status information is encoded into OAM bits, e.g., of an OAM word. The OAM bits are then provided to the OAM-TX module 436, which may include buffering memory and/or logic to provide the OAM bits (e.g., as an OAM word) to the transceiver 410 for insertion into an FEC frame. The FEC frames, including at least one FEC frame with the encoded OAM bits, are transmitted on the link 406 as analog signals by the PMA-TX 489. In an example, with respect to a low voltage condition, a fault status may be low voltage condition=YES or low voltage condition=NO. In other embodiment, a fault status may be simple an indication of “low voltage condition.” In an embodiment, a fault status is shared as fault code, which is generated by the control logic, then encoded into a few OAM bits, and then decoded back to a fault code that can be understood by the control logic. The control logic can also set a value in the register to indicate a fault status. The value can be read by a higher layer through the MDIO 455.
In an example of a receive operation, the PMA-RX 490 of node A 402 receives electrical signals on the link 406, decodes the signals into symbols, and provides the symbols to the PCS-RX 453. The PCS-RX maps the symbols to a bit stream and demultiplexes the OAM bits and the payload bits as described with reference to
In an embodiment, a network node may implement loopback testing to determine if there is a fault at the network node and/or to determine if there is a fault in the physical medium (e.g., the twisted pair wire and or connectors that connect the wire to the node) that connects the network node to another network node. For example, internal loopback testing and external loopback testing are known techniques for testing physical layer components of a PHY device/PHY chip and remote loopback testing is a known technique for testing the physical medium (e.g., the twisted pair wire and or connectors that connect the wire to the node) that connects the network node to another network node.
If at decision point 912, the status of register values for the local and remote receivers (1c_rx_sts and rm_rx_sts) are 1c_rx_sts=0 and rm_rx_sts=0, and a remote loopback test is OK (rm_loopback_test=!OK) and internal and external loopback tests are OK (Internal & External_Loopback_test!=OK), then at block 914, the channel is not ok, the local and remote PHYs are OK, and OAM bits are encoded accordingly to indicate a fault status.
If at decision point 916, the status of register values for the local and remote receivers (1c_rx_sts and rm_rx_sts) are 1c_rx_sts=1 and rm_rx_sts=0, and a remote loopback test is OK (rm_loopback_test=OK) and internal and external loopback tests are OK (Internal & External_Loopback_test=OK), then at block 918, the channel is ok, the local receiver and remote transmitter are ok, either the local transmitter or remote receiver is not ok, the register, 1c_rx_sts is set to “0,” and OAM bits are encoded accordingly to indicate a fault status.
If at decision point 920, the status of register values for the local and remote receivers (1c_rx_sts and rm_rx_sts) are 1c_rx_sts=0 and rm_rx_sts=1, and a remote loopback test is OK (rm_loopback_test=OK) and internal and external loopback tests are OK (Internal & External_Loopback_test=OK), then at block 922, the channel is ok, the remote receiver and local transmitter are ok, either the local receiver or remote receiver is not ok, the register, rm_rx_sts is set to “0,” and OAM bits are encoded accordingly to indicate a fault status.
As described above, the desired error management mode can be determined at, for example, node A and provided to node B. An example of providing error management mode information is now described with reference to
With reference to
With reference to
The above-described operations of the fault status logic can be implemented in hardware, firmware, software, or a combination thereof. In an embodiment, the error management logic is implemented in a PHY chip with hardware logic circuits. In another embodiment, the PHY chip may include an instruction processor and the error management logic can be implemented through computer readable instructions that are executed by the instruction processor.
In an embodiment, OAM bits are used by a receiving node to learn the status of the physical layer (e.g., the PHY chip) of a transmitting node and/or to communicate certain defined/agreed actions. The OAM bits can be used to communicate between two PHY chips to agree on the timing to start a new configuration.
In an embodiment, the elements of the physical layer as described above are integrated into an IC device, referred to as a PHY device. In an embodiment, the elements of the physical layer as described above can be integrated into an IC device that includes other functionality, such as microprocessor functionality. For example, the components of a traditional PHY chip can be integrated onto a System-on-Chip (SoC).
In an embodiment, the OAM bits are used to pass information from a local PHY chip to a remote PHY chip. As shown in
Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.
It should also be noted that at least some of the operations for the methods described herein may be implemented using software instructions stored on a computer useable storage medium for execution by a computer. As an example, an embodiment of a computer program product includes a computer useable storage medium to store a computer readable program.
The computer-useable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of non-transitory computer-useable and computer-readable storage media include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), and a digital video disk (DVD).
Alternatively, embodiments of the invention may be implemented entirely in hardware or in an implementation containing both hardware and software elements. In embodiments which use software, the software may include but is not limited to firmware, resident software, microcode, etc.
Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.
