Patent Grant
6978390
This invention relates in general to integrated circuits, and more particularly to a pipelined data processor with power management control.
Increasingly, electronic circuit manufacturers need to reduce the power consumption of their boards. The conservation of power is particularly important in portable electronic devices, such as laptop or notebook computers, where the product is specifically designed for use in situations where power outlets are not available. Since laptop and notebook computers must operate using internal batteries or rechargeable battery packs for extended periods of time, the conservation of battery power becomes a primary concern.
In a laptop or notebook computer, the largest consumer of power is the display. The proportion of power consumed by the display will vary depending on the technology used. Thus, laptop and notebook computer manufacturers have disabled the power to the display during periods of inactivity. Decoupling the display from the power supply can be accomplished with fairly simple circuitry.
The next largest consumer of power on a laptop or notebook computer is the CPU motherboard microprocessor. Heretofore, computer manufacturers have used one or two techniques for reducing power consumption of the microprocessor during periods of inactivity. One technique reduces the speed of the system clock to a fraction of the normal operating frequency during periods of inactivity. Since the power consumption of the microprocessor is proportional to the frequency, reducing the frequency of the system clock also reduces the power consumption of the microprocessor. In an Intel 80386DX microprocessor (manufactured by Intel Corporation of Santa Clara, Calif.), reducing the operating frequency from 33 MHz to 4 MHz reduces the typical operating current of the microprocessor from 400 to approximately 100 milliamps. Nevertheless, an operating current of 100 milliamps still poses a large power drain on the battery.
A second technique for reducing power turns off the system clock during periods of inactivity. Turning off the system clock affects all circuitry on the motherboard, consequently, the circuitry which disables the system clock must also save all pertinent information in the microprocessor and associated board logic and restore the data upon resumption of activity, such that the state of the computer after resumption of the system clock will be identical to the state of the computer prior to disabling the system clock. As a result, this technique for consuming power is both costly because of the complicated circuitry and slow because of the need to store and restore the state of the computer.
Therefore, a need has arisen in the industry to provide a method and apparatus for conserving power in an electronic device which significantly reduces the power drain of the microprocessor without the need for complicated external circuitry.
In accordance with the presently claimed invention, a pipelined data processor with instruction-initiated power management control is provided in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to an instruction executed by the pipeline subcircuitry by selectively disabling a clock signal to the pipeline subcircuitry.
In accordance with one embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes a plurality of interface electrodes, a plurality of subcircuits, control circuitry and clock circuitry. The plurality of interface electrodes conveys at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The plurality of subcircuits is coupled to at least a portion of the plurality of interface electrodes and includes pipeline subcircuitry responsive to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline subcircuitry is responsive to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline subcircuitry is coupled to the first pipeline subcircuitry portion and responsive to the active first clock signal by executing the one or more decoded instructions. The control circuitry is coupled to the plurality of subcircuits and responsive to the one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals with the second selected assertion and de-assertion states following reception of the power management instruction. The clock circuitry is coupled to the control circuitry and the plurality of subcircuits, and responsive to the one or more clock control signals by providing at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes interface means, subcircuit means, controller means and clock source means. The interface means is for conveying at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The subcircuit means includes pipeline means for responding to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline means is for responding to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline means is for responding to the active first clock signal by executing the one or more decoded instructions. The controller means is for responding to the one or more local control signals by generating one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals with the second selected assertion and de-assertion states following reception of the power management instruction. The clock source means is for responding to the one or more clock control signals by generating at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes a plurality of interface electrodes, a plurality of subcircuits, control circuitry and clock circuitry. The plurality of interface electrodes conveys at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The plurality of subcircuits coupled to at least a portion of the plurality of interface electrodes and includes pipeline subcircuitry responsive to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline subcircuitry is responsive to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline subcircuitry is coupled to the first pipeline subcircuitry portion and responsive to the active first clock signal by executing the one or more decoded instructions. The control circuitry is coupled to the plurality of subcircuits and responsive to the one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals. The clock circuitry is coupled to the control circuitry and the plurality of subcircuits, and responsive to the one or more clock control signals by providing at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and following reception of the power management instruction.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes interface means, subcircuit means, controller means and clock source means. The interface means is for conveying at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The subcircuit means includes pipeline means for responding to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline means is for responding to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline means is for responding to the active first clock signal by executing the one or more decoded instructions. The controller means is for responding to the one or more local control signals by generating one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals. The clock source means is for responding to the one or more clock control signals by generating at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and following reception of the power management instruction.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes a plurality of interface electrodes, a plurality of subcircuits, control circuitry and clock circuitry. The plurality of interface electrodes conveys at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The plurality of subcircuits is coupled to at least a portion of the plurality of interface electrodes and includes pipeline subcircuitry responsive to a first clock signal having an active state with a plurality of successive cycles and an inactive state with substantially zero cycles by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline subcircuitry is responsive to at least a first one of the plurality of first clock signal cycles by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline subcircuitry is coupled to the first pipeline subcircuitry portion and responsive to at least a second one subsequent to the first one of the plurality of first clock signal cycles by executing the one or more decoded instructions. The control circuitry is coupled to the plurality of subcircuits and responsive to the one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals with the second selected assertion and de-assertion states following reception of the power management instruction. The clock circuitry is coupled to the control circuitry and the plurality of subcircuits, and responsive to the one or more clock control signals by providing at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes interface means, subcircuit means, controller means and clock source means. The interface means is for conveying at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The subcircuit means includes pipeline means for responding to a first clock signal having an active state with a plurality of successive cycles and an inactive state with substantially zero cycles by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline means is for responding to at least a first one of the plurality of first clock signal cycles by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline means is for responding to at least a second one subsequent to the first one of the plurality of first clock signal cycles by executing the one or more decoded instructions. The controller means is for responding to the one or more local control signals by generating one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals with the second selected assertion and de-assertion states following reception of the power management instruction. The clock source means is for responding to the one or more clock control signals by generating at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes a plurality of interface electrodes, a plurality of subcircuits, control circuitry and clock circuitry. The plurality of interface electrodes conveys at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The plurality of subcircuits is coupled to at least a potion of the plurality of interface electrodes and includes pipeline subcircuitry responsive to a first clock signal having an active state with a plurality of successive cycles and an inactive state with substantially zero cycles by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline subcircuitry is responsive to at least a first one of the plurality of first clock signal cycles by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline subcircuitry is coupled to the first pipeline subcircuitry portion and responsive to at least a second one subsequent to the first one of the plurality of first clock signal cycles by executing the one or more decoded instructions. The control circuitry is coupled to the plurality of subcircuits and responsive to the one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals. The clock circuitry is coupled to the control circuitry and the plurality of subcircuits, and responsive to the one or more clock control signals by providing at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and following reception of the power management instruction.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes interface means, subcircuit means, controller means and clock source means. The interface means is for conveying at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The subcircuit means includes pipeline means for responding to a first clock signal having an active state with a plurality of successive cycles and an inactive state with substantially zero cycles by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline means is for responding to at least a first one of the plurality of first clock signal cycles by performing at least one or more respective portions of one or more Processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline means is for responding to at least a second one subsequent to the first one of the plurality of first clock signal cycles by executing the one or more decoded instructions. The controller means is for responding to the one or more local control signals by generating one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals. The clock source means is for responding to the one or more clock control signals by generating at least the first clock signal with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and following reception of the power management instruction.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes a plurality of interface electrodes, a plurality of subcircuits, control circuitry and clock circuitry. The plurality of interface electrodes conveys at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The plurality of subcircuits is coupled to at least a portion of the plurality of interface electrodes and includes pipeline subcircuitry responsive to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline subcircuitry is responsive to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline subcircuitry is coupled to the first pipeline subcircuitry portion and responsive to the active first clock signal by executing the one or more decoded instructions. The control circuitry is coupled to the plurality of subcircuits and responsive to the first clock signal, a second clock signal and the one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals with the second selected assertion and de-assertion states following reception of the power management instruction. The clock circuitry is coupled to the control circuitry and the plurality of subcircuits, and responsive to the one or more clock control signals by providing the first and second clock signals with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and the second clock signal having active and inactive states substantially independent of the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes interface means, subcircuit means, controller means and clock source means. The interface means is for conveying at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The subcircuit means includes pipeline means for responding to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline means is for responding to the active first clock signal by performing at least one or more respective portions of one or more Processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline means is for responding to the active first clock signal by executing the one or more decoded instructions. The controller means is for responding to the first clock signal, a second clock signal and the one or more local control signals by generating one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals with the second selected assertion and de-assertion states following reception of the power management instruction. The clock source means is for responding to the one or more clock control signals by generating the first and second clock signals with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and the second clock signal having active and inactive states substantially independent of the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes a plurality of interface electrodes, a plurality of subcircuits, control circuitry and clock circuitry. The plurality of interface electrodes conveys at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The plurality of subcircuits is coupled to at least a portion of the plurality of interface electrodes and includes pipeline subcircuitry responsive to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline subcircuitry is responsive to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline subcircuitry is coupled to the first pipeline subcircuitry portion and responsive to the active first clock signal by executing the one or more decoded instructions. The control circuitry is coupled to the plurality of subcircuits and responsive to the first clock signal, a second clock signal and the one or more local control signals by providing one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals. The clock circuitry is coupled to the control circuitry and the plurality of subcircuits, and responsive to the one or more clock control signals by providing the first and second clock signals with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and following reception of the power management instruction, and with the second clock signal having active and inactive states substantially independent of the one or more second selected assertion and de-assertion states of the one or more clock control signals.
In accordance with another embodiment of the presently claimed invention, an apparatus including integrated processor circuitry includes interface means, subcircuit means, controller means and clock source means. The interface means is for conveying at least a plurality of incoming instructions, including a power management instruction, from at least one signal source. The subcircuit means includes pipeline means for responding to a first clock signal having active and inactive states by selectively operating on one or more of the plurality of incoming instructions for data processing. A first portion of the pipeline means is for responding to the active first clock signal by performing at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of the one or more of the plurality of incoming instructions to provide one or more decoded instructions and to provide one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to the power management instruction, and a second portion of the pipeline means is for responding to the active first clock signal by executing the one or more decoded instructions. The controller means is for responding to the first clock signal, a second clock signal and the one or more local control signals by generating one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to the one or more first selected assertion and de-assertion states of the one or more local control signals. The clock source means is for responding to the one or more clock control signals by generating the first and second clock signals with the first clock signal inactive state corresponding to the one or more second selected assertion and de-assertion states of the one or more clock control signals and following reception of the power management instruction, and with the second clock signal having active and inactive states substantially independent of the one or more second selected assertion and de-assertion states of the one or more clock control signals.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
a–b illustrate circuitry for enabling and disabling pins providing power management control signals; and
The preferred embodiment of the present invention and its advantages are best understood by referring to
The computer system 10 shown in
Clock module 84 receives an external clock signal (CLK2) and generates CLKA (connected to the bus controller 40) and CLKB (coupled to the memory circuitry 38 and the core circuitry 36). CLKA and CLKB are both clock signals of one-half the frequency of CLK2. Clock module 84 receives control signals from bus controller 40.
In operation, instructions are received by the microprocessor 12 from external memory under control of the memory management unit 66. For enhanced performance, an instruction/data cache 70 caches instruction and data received through the bus controller 40. Instructions are stored in the instruction queue and are subsequently translated by the decode circuitry 46 into microcode. The sequencer points to the next address in the microcode ROM 48 under control of the decoder 46 and the execution unit 52. The execution unit 52 processes information under control of the microcode ROM 48.
In the preferred embodiment, the microprocessor 12 has a static design, i.e., retention of data in the internal memories and registers of the microprocessor 12 is not dependent upon the clock signal. As described in greater detail hereinbelow, the clock module 84, under control of the bus controller 40, can disable clocks to the subcircuits of the core circuitry 36 and the memory circuitry 38 while continuing to generate clock signals to the bus controller 40. Thus, during periods of inactivity, a large portion of the circuitry of the microprocessor may be suspended, thereby greatly reducing the power consumed by the microprocessor 12.
In operation, an external circuit (typically the BIOS 16 in conjunction with the logic 18) detects conditions where microprocessor operations could be suspended. Upon detection of such a situation, the external circuit asserts the SUSP pin (for example, by driving the SUSP pin with a logical low voltage). In response to the assertion of the SUSP signal, the bus controller 40, in conjunction with the exception processor 86, asserts the F—IDLE control signal to the clock module 84. In response to the assertion of the F—IDLE signal, the clock module 84 disables the CLKB clock signals (by holding the disabled clock signal at a logical high or logical low voltage), while continuing to generating the CLKA clock signals. Since the design of the microprocessor is static, the memories do not require refreshing, and therefore suspending the clock will not result in a loss of data within the microprocessor 12. The SUSPACK signal is asserted to notify external circuitry that the microprocessor 12 is in the suspended state. To resume operation of the microprocessor 12, the SUSP signal is de-asserted (i.e., by applying a logical low voltage to the SUSP pin).
By suspending the clocks to the core circuitry 36 and memory circuitry 38, a significant reduction in the power consumed by the microprocessor 12 is realized. The bus controller 40 remains active to observe and control I/O signals between the microprocessor 12 and the external circuitry.
Most microprocessors, including the 80386, do not use all available pins on the chip package. Thus, the SUSP and SUSPACK signals may be communicated to and from the microprocessor 12 using unused pins, thereby maintaining compatibility with a pre-existing technology. Nonetheless, in the preferred embodiment, the pins for the SUSP and SUSPACK signals may be selectively enabled or disabled. In the preferred embodiment, the SUSP and SUSPACK pins are initially disabled, and the BIOS 16 must be configured to enable the pins in its start-up routine. To effect enabling or disabling of the SUSP and SUSPACK pins, a control bit is provided which may be written to or read from via preselected I/O ports. The preferred embodiment of this aspect is shown in greater detail in connection with
In
In
This aspect of the preferred embodiment ensures pin-compatibility with an existing pin structure.
In the present invention, however, the HALT instruction has essentially the same consequence as asserting the SUSP pin. Thus, the BIOS 16 can issue a HALT instruction to the microprocessor 12, thereby disabling CLKB. Again, disabling CLKB will result in a significant reduction of power consumed by the microprocessor 12.
The HALT instruction allows the BIOS 16 to place the microprocessor 12 in a suspended state without any additional hardware connections to the microprocessor.
The present invention provides significant advantages over the prior art. By suspending the clocks to the core circuitry and memory circuitry, a current consumption of less than 10 milliamps has been demonstrated. Since most BIOS programs support power conservation measures, the additional coding for supporting the SUSP and SUSPACK signals is relatively simple. Alternatively, the chipset logic 18 can be modified to support the SUSP and SUSPACK signals. Further, since the SUSPACK, in the preferred embodiment, is not asserted until after coprocessor operations are completed, the BIOS does not have to provide additional circuitry or codes for monitoring the coprocessor. Further, the power saving circuitry may be provided on the microprocessor chip without sacrificing pin-compatibility. Additionally, by using the enhanced HALT command, the microprocessor may be operated in a suspended state without any hardware interaction, other than asserting an interrupt to bring the microprocessor 12 out of a suspended state.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
This is a division of application Ser. No. 10/216,615, filed on Aug. 9, 2002, now U.S. Pat. No. 6,721,894, which is a division of application Ser. No. 09/779,150, filed on Feb. 8, 2001, now U.S. Pat. No. 6,694,443 B1, which is a division of application Ser. No. 09/570,155, filed on May 12, 2000, now U.S. Pat. No. 6,343,363, which is a continuation of application Ser. No. 08/777,772, filed on Dec. 9, 1996, now U.S. Pat. No. 6,088,807, which is a division of application Ser. No. 08/310,895, filed Sep. 22, 1994, now U.S. Pat. No. 5,630,143, which is a continuation of application Ser. No. 07/858,579, Mar. 27, 1992, abandoned.
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| Number | Date | Country | |
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| 20040230852 A1 | Nov 2004 | US |
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| Parent | 10216615 | Aug 2002 | US |
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| Parent | 09779150 | Feb 2001 | US |
| Child | 10216615 | US | |
| Parent | 09570155 | May 2000 | US |
| Child | 09779150 | US | |
| Parent | 08310895 | Sep 1994 | US |
| Child | 08777772 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 08777772 | Dec 1996 | US |
| Child | 09570155 | US | |
| Parent | 07858579 | Mar 1992 | US |
| Child | 08310895 | US |
