Patent Application
20150179436
Related fields include thin-film microwave devices with superconducting components.
At temperatures<100 mK, amorphous silicon (a-Si) is a dielectric. Its low cost and ease of fabrication make it attractive as an interlayer dielectric (ILD) for superconducting interconnects and components for planar microwave devices, but its loss tangent (˜108) is much larger than that of single-crystal Si (˜107) at microwave frequencies (e.g., 3-300 GHz). The loss tangent is believed to be caused by defects occurring during deposition.
ILD films are typically tenths of microns thick (e.g., 300-500 nm). At this thickness, many surface treatments are ineffective to remove defects from the bulk of the film. This is also an inconvenient thickness to form by the precisely controlled methods of atomic layer deposition (ALD); because each ALD cycle creates a monolayer on the order of 0.1 nm thick, a layer hundreds of nm thick would take too long to be cost-effective.
Hydrogenation has been observed to improve a-Si loss tangent in some cases. However, only hydrogen (H) that is strongly bonded to Si helps to reduce loss. H that is trapped in interstices of the a-Si, or that is weakly attracted to dangling bond sites of two neighboring Si atoms, can form a two-level system (TLS) that increases noise and loss. For example, early studies of Josephson-junction-based qubits for quantum computing attributed loss and decoherence primarily to extraneous TLS effects from defects in dielectrics.
Therefore, a need exists for methods to reduce the microwave-frequency loss tangent of a-Si films by reducing or eliminating defects in the bulk of micron-scale films as well as on the surface. Preferably, this method should avoid or minimize the creation of additional TLS.
The following summary presents some concepts in a simplified form as an introduction to the detailed description that follows. It does not necessarily identify key or critical elements and is not intended to reflect a scope of invention.
In some embodiments, a hydrogenated a-Si layer is deposited by chemical vapor deposition (CVD). During or after the formation of the layer, ions are injected into the CVD chamber where the layer is/was deposited. In some embodiments, the ions and the plasma-generating energy are selected to avoid damaging the layer surface (e.g., argon (Ar) ions from a ˜300 W plasma source). The ions transfer energy to the layer as they contact the layer surface. The added energy dislodges interstitial or weakly-bonded H atoms, but does not disturb strongly-bonded H atoms.
As the ions continue to transfer energy to the layer, the dislodged H atoms move through the a-Si. Some of the mobile H atoms may encounter available strong-bonding sites and be trapped. Other mobile H atoms may encounter each other, recombine into H2, and outgas into the chamber ambient. The result is a denser Si film with fewer defects. In some embodiments, the ion treatment is done in-situ after the a-Si layer is formed. In some embodiments, the deposition may be paused periodically (e.g., every after every 3-6 nm of a-Si thickness) to ion-treat the completed part of the layer.
In some embodiments, the layer is annealed at 500-650 C for 5-60 min. Like the ion treatment, the annealing increases mobility of weakly-bonded or interstitial H. In addition, the annealing drives out H2 and may at least partially crystallize the a-Si, further reducing defects.
The accompanying drawings may illustrate examples of concepts, embodiments, or results. They do not define or limit the scope of invention. They are not drawn to any absolute or relative scale. In some cases, identical or similar reference numbers may be used for identical or similar features in multiple drawings.
A detailed description of one or more example embodiments is provided below. To avoid unnecessarily obscuring the description, some technical material known in the related fields is not described in detail. Semiconductor fabrication generally requires many other processes before and after those described; this description omits steps that are irrelevant to, or that may be performed independently of, the described processes.
Unless the text or context clearly dictates otherwise: (1) By default, singular articles “a,” “an,” and “the” (or the absence of an article) may encompass plural variations; for example, “a layer” may mean “one or more layers.” (2) “Or” in a list of multiple items means that any, all, or any combination of less than all the items in the list may be used in the invention. (3) Where a range of values is provided, each intervening value is encompassed within the invention. (4) “About” or “approximately” contemplates up to 10% variation. “Substantially” contemplates up to 5% variation.
“Substrate,” as used herein, may mean any workpiece on which formation or treatment of material layers is desired. Substrates may include, without limitation, silicon, germanium, silica, sapphire, zinc oxide, SiC, AlN, GaN, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride and aluminum nitride, and combinations (or alloys) thereof. The term “substrate” or “wafer” may be used interchangeably herein. Semiconductor wafer shapes and sizes can vary and include commonly used round wafers of 50 mm, 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm in diameter.
As used herein, a material (e.g. a dielectric material or an electrode material) will be considered to be “crystalline” if it exhibits greater than or equal to 25% crystallinity as measured by a technique such as x-ray diffraction (XRD), and “amorphous” otherwise. “Interlayer dielectric,” “intermetallization dielectric,” “bulk insulator,” and “fill dielectric” are used interchangeably herein for an insulating dielectric layer that fills spaces between conducting interconnects (e.g., wiring layers, vias) or between the devices connected by the interconnects. Material descriptions such as “conductor,” “superconductor,” “semiconductor,” “dielectric,” and “insulator” may vary with temperature for a given material, and shall be used herein to describe the characteristics of the materials at the intended operating temperature of the device in which the materials are used. For example, “forming a superconducting layer” shall mean “forming a layer of a material expected to exhibit superconductivity at the intended operating temperature of the device being fabricated.”
Ion treatment 603 may include Ar ions from a 100-350 W plasma at 100-1000 sccm flow rate. Ion treatment 603 may be performed in the same chamber as hydrogenated a-Si deposition 602. Optionally, a chamber purge 605 may follow ion treatment 603 to exhaust the H gas, excess ions, and other gases from the chamber. This purge and other purges described herein may optionally use an inert purge gas, such as Ar. Ion treatment 603 may be performed after deposition completion 604; e.g., after deposition of a 100-500 nm thick ILD layer. In some embodiments, repeated ion treatments 603 may be alternated with repeated partial depositions 602; for example, the deposition may pause after each 3-5 nm of thickness, the partial layer may be ion-treated 603, then the deposition 602 may continue. Optionally, an anneal 606 (e.g., 500-650 C for 5-60 min at 20-60 Torr) may follow the post-completion ion treatment 603. Anneal 606 may be performed in the same chamber as hydrogenated a-Si deposition 602. Anneal 606 may or may not partially crystallize the layer. In some embodiments, an additional chamber purge 615 may be performed after anneal 606 and before next process 699.
On completion 714 of the interconnect structure, one or more component layers may be added. Component formation 720 may include, for example, formation of superconducting Josephson junctions. The components may be formed over exposed (or otherwise accessible) connections to the underlying interconnect structure formed in steps 701-714. Optionally, one or more wirings and vias may be formed in the component layer. ILD formation 712 over the component layer may include a variation of the process of
Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the description and drawings. The examples are illustrative, not restrictive. There are many alternative ways of implementing the invention. Various aspects or components of the described embodiments may be used singly or in any combination. The scope is limited only by the claims, which encompass numerous alternatives, modifications, and equivalents.
