Patent Application
20060145355
The present invention relates to the fabrication of substrates such as semiconductor wafers, and more specifically, to filling plugs such as vias or contacts in a dual damascene process.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.13 micron and even 90 nm feature sizes.
Metallization of integrated circuits can employ a process known as damascene, in which a substrate is inlaid with metal. Damascene and a related process known as dual damascene (both referred to henceforth as “damascene”) have become widely used in integrated circuit manufacturing for devices with geometries of 0.1 micron or less. Generally, the damascene process involves creating interconnect schemes by forming plug openings and/or cutting trenches in a dielectric, and then filling those openings and/or trenches with metal. Any excess metal is then removed. Damascene methods often use tungsten or copper as the bulk filling interconnect metal because of its low resistance. A copper interconnect is frequently surrounded with a metal barrier.
It is desired that fabrication processes, such as dual damascene processes, be performed with as few steps as possible. Reducing and/or eliminating steps not only speeds up the overall process time, but also may reduce fabrication costs and reduced the amount of defects due to the reduced handling of the wafers.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The present disclosure provides a new method for filling plug openings on a semiconductor substrate, such as can be used in a dual damascene process. The present disclosure also provides a unique plug-filling material for fabricating integrated circuits. It is understood, however, that the specific examples provided in the present disclosure are meant to teach the broader inventive concept, and one of ordinary skill in the art can easily apply the teachings of the present disclosure to other processes, devices and material. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
Referring now to
Referring also to
According to step 12, one or more via plug openings 106 are created in the insulator layer 104 by a plasma etch or another fabrication method known to those skilled in the art. In some embodiments, the via plug openings 106 can be lined with a metal barrier such as Ti, TiN, Ta, TaN, or other appropriate material.
Referring now to
At step 16, the integrated circuit 100 is subjected to a bake process for curing the plug-filler material. Baking is a well-known conventional process and depends on various parameters that may change from one design to the next. The integrated circuit is then sent directly to a metal trench/photolithography process, not requiring any intermediate etch removal of excessive plug-filler material form the top surface of layer 108.
Referring now to
At step 20, a bottom-side antireflective coating (BARC) can be applied, if desired. For example, some 0.13 micron processes may not use BARC, while some 90nm process may require BARC. At step 20, if BARC is applied, a second RRC process can be used to rinse the surface of the integrated circuit 100.
Referring to
Plug-Filler Material
In the present embodiments, the cross-linking action of the plug filler material for layer 108 is modified so that it is more soluble to an otherwise-conventional RRC solvent. In the present embodiment, the plug-filler material includes a cross-linking material and an additive. The plug-filler material can be selected for various properties beyond the scope of the present disclosure.
Table 1 below describes five different additives for the plug material. This list is not intended to be exhaustive, but is intended to provide several different examples. Novolac, which is graphically illustrated in
To illustrate by example, different percentages of each of the above-listed additives were combined with cross-linking material to form the plug-filler material, and the results are provided in Table 2, below. The columns A-K represent different experiments, with the column K representing a baseline where no additives are provided. The row “Sample No.” refers to the with the cross-linking material. The row “Thickness” identifies the thickness, in Angstroms, of the plug-filler material after step 16 of method 10 (
Column K of Table 2 represents a baseline procedure in which no additive (e.g., no PHS or Novolac) is used in the plug-filler material. As a result, a layer 108 of about 887.1 Angstroms in thickness, with a range of 8.9 Angstroms is formed at steps 14 and 16 of the method 10 (
Referring now to column A of Table 2, a mixture of 50% conductive material and 50% Novolac (Mw of 3000) produced a layer 108 (
Referring now to column F of Table 2, a mixture of 75% conductive material and 25% Novolac (Mw of 3000) produced a layer 108 (
With the given experimental results of Table 2 and the present example range of about 500-800 Angstroms thickness for the layer, it can be seen that columns A, C, G, I, and J represent acceptable mixtures of cross-linking material and additive. It can also be seen that a desired thickness, concentration, or viscosity can be further “fine tuned” by changing the mixture concentrations of the additive or other parameters. Furthermore, the above-described experimental results were created using conventional RRC solvent, and in other embodiments, this solvent can be modified to further facilitate obtaining a desired thickness.
In summary, the present embodiment provides a novel dual damascene semiconductor device including a substrate and an insulator above the substrate including a plurality of openings filled with a plug-filler material. The plug-filler material includes a cross-linking material and an additive, the additive selected and provided in a concentration by which a significant portion of the plug-filler material can be removed during a reduced resist coating (RRC) process. The thickness of the plug-filling material can be measured by using optical critical dimension (OCD) measurement to check the thickness before RRC and after RRC without destroying the wafer.
In another embodiment, a method is provided for manufacturing a dual damascene structure on a semiconductor substrate. The method includes forming an insulator above the substrate and patterning the insulator to include a plurality of plug openings. Plug-filler material fills one or more of the plug openings and extends above the insulator. A portion of the plug-filler material extending above the insulator can then be removed by using a solvent.
In another embodiment, a plug-filling material for use in a dual damascene structure on a semiconductor substrate is provided. The plug-filling material includes at least fifty percent concentration of cross-linking material and at least twenty five percent concentration of an additive. The additive reduces a cross-linking property of the plug-filling material so that a substantial portion of the plug-filling material can be removed, after baking, by using an RRC solvent.
The foregoing has outlined features of several embodiments according to aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
