Claims
- 1. A method of manufacturing a polishing pad for planarization of a microelectronic-device substrate assembly, comprising:forming a plurality of contour surfaces over a first surface of a backing member to project away from the first surface by depositing a plurality of pattern elements over the first surface of the backing member, each pattern element having a portion projecting away from the first surface of the backing member, and the portions of the pattern elements projecting away from the backing member defining the contour surfaces, wherein the plurality of pattern elements are deposited on the first surface by coating the first surface with a liquid containing the pattern elements by drawing the backing member through a bath including the liquid and the pattern elements and evaporating the liquid to leave the pattern elements directly on the first surface of the backing member; and covering the contour surfaces with a cover layer of hard material that conforms to the contour surfaces to form nodules from the portions of the hard cover layer over the contour surfaces, the nodules projecting away from the first surface of the backing member.
- 2. The method of claim 1 wherein depositing the cover layer comprises chemical vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 3. The method of claim 2 wherein depositing the cover layer comprises plasma vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 4. A method of manufacturing a polishing pad for planarization of a microelectronic-device substrate assembly, comprising:constructing an intermediate layer directly on a first surface of a backing member; forming a plurality of contour surfaces on the intermediate layer to project away from the intermediate layer by depositing a plurality of pattern elements over the intermediate layer, each pattern element having a portion projecting away from the intermediate layer, and the portions of the pattern elements projecting away from the intermediate layer defining the contour surfaces, wherein the plurality of pattern elements are deposited on the intermediate layer by coating the intermediate layer with a liquid containing the pattern elements by drawing the backing member and the intermediate layer through a bath including the liquid and the pattern elements, and evaporating the liquid to leave the pattern elements directly on the intermediate layer; and covering the contour surfaces with a cover layer of hard material that conforms to the contour surfaces to form nodules from the portions of the hard cover layer over the contour surfaces, the nodules projecting away from the intermediate layer.
- 5. The method of claim 4 wherein depositing the cover layer comprises chemical vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 6. The method of claim 5 wherein depositing the cover layer comprises plasma vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 7. A method of manufacturing a polishing pad for planarization of a microelectronic-device substrate assembly, comprising:distributing a plurality of pattern elements over a first surface of a backing member, the pattern elements defining a plurality of contour surfaces projecting away from the first surface of the backing member by coating the first surface with a liquid containing the pattern elements by drawing the backing member through a bath including the liquid and the pattern elements and evaporating the liquid to leave the pattern elements directly on the first surface of the backing member; and forming a layer of a hard material at least on the pattern elements to conform to the contour surfaces, the portions of the cover layer over the contour surfaces projecting away from the first surface of the backing member to define abrasive nodules.
- 8. The method of claim 7 wherein depositing the cover layer comprises chemical vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 9. The method of claim 8 wherein depositing the cover layer comprises plasma vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 10. A method of manufacturing a polishing pad for planarization of a microelectronic-device substrate assembly, comprising:constructing an intermediate layer directly on a first surface of a backing member; distributing a plurality of pattern elements over the intermediate layer, the pattern elements being distributed directly on the intermediate layer by coating the intermediate layer with a liquid containing the pattern elements by drawing the backing member and the intermediate layer through a bath including the liquid and the pattern elements and evaporating the liquid to leave the pattern elements directly on the intermediate layer to define a plurality of contour surfaces projecting away from the intermediate layer; and forming a layer of a hard material at least on the pattern elements to conform to the contour surfaces, the portions of the cover layer over the contour surfaces projecting away from the first surface of the backing member to define abrasive nodules.
- 11. The method of claim 10 wherein forming the layer of hard material comprises chemical vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
- 12. The method of claim 11 wherein forming the layer of hard material comprises plasma vapor deposition of either silicon nitride, ceria, silica, alumina, zirconia, titanium or titanium nitride.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of U.S. patent application Ser. No. 09/201,576 filed Nov. 30, 1998, now U.S. Pat. No. 6,206,759, issued Mar. 27, 2001.
US Referenced Citations (7)