Claims
- 1. A polishing pad for planarizing a surface of a semiconductor device or a precursor thereto, said pad being characterized by; a polishing layer for planarizing said surface, said layer having a KEL of about 100-1,000 (1/Pa at 40° C.).
- 2. A polishing pad according to claim 1, wherein the polishing layer further has an E′ ratio at 30° C.-90° C. of about 1-4.6.
- 3. A polishing pad according to claim 1, wherein the polishing layer further has a hardness of about 40-70 Shore D.
- 4. A polishing pad according to claim 1, wherein the polishing layer further has a tensile Modulus of about 100-2,000 MPa at 40° C.
- 5. A polishing pad according to claim 1, wherein each linear dimension of said pad changes by less than about 1% when said pad is immersed in deionized water for 24 hours at an ambient temperature of about 25° C.
- 6. A polishing pad according to claim 1, wherein the hardness of said pad decreases by less than about 30% when said pad is immersed in deionized water for 24 hours at an ambient temperature of about 25° C.
- 7. A polishing pad according to claim 1, wherein the polishing layer has a surface roughness of from about one to about nine micron Ra.
- 8. A process for polishing a metal damascene structure of a semiconductor wafer comprising:biasing the wafer toward an interface between the wafer and a polishing layer of a polishing pad; flowing a polishing fluid into the interface; and providing relative motion of the wafer and the polishing pad under pressure so that the moving pressurized contact of the polishing fluid against the wafer results in planar removal along a surface of said wafer; said polishing layer having a KEL of about 100-1,000 (1/Pa at 40° C.).
- 9. A process according to claim 8, further comprising, attracting a complexing agent of the polishing fluid to the metal, and protecting a surface of the metal until disrupted by the polishing pad, said movement occurring at a distance between the polishing pad and the metal being less than the average dimension of nano-asperities of less than, 500 Angstroms along a polishing surface of the polishing layer.
- 10. A process according to claim 8, further comprising: changing each linear dimension of said pad by less than about 1%, and decreasing the hardness of said pad by less than about 30%, by said pad being in deionized water for 24 hours at an ambient temperature of about 25° C.
Parent Case Info
This application is a continuation of U.S. application Ser. No. 09/631,784 filed Aug. 3, 2000, U.S. Pat. No. 6,454,634 which claims benefit of U.S. Provisional Application Serial No. 60/207,936 filed May 27, 2000.
US Referenced Citations (18)
Non-Patent Literature Citations (1)
Entry |
Murarka, S. P., Steigerwald, J., Gutmann, R. J., “Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing”, MRS Bulletin, Jun. 1993, pp. 46-51. |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/207938 |
May 2000 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/631784 |
Aug 2000 |
US |
Child |
10/193429 |
|
US |