Claims
- 1. A capacitor structure, integrated with a polysilicon gate in a silicon integrated circuit, comprising:a phosphorus-doped polysilicon gate that consists of a first layer of polysilicon, that was formed at a temperature between about 600 and 650° C., on which lies a second layer of phosphorus-doped polysilicon that was formed at a temperature between about 520 and 580° C., the second polysilicon layer having a thickness between about 2,000 and 3,800 Angstroms; said first and second polysilicon layers having been formed at the same deposition rate; a dielectric layer on the second polysilicon layer, wherein the second polysilicon layer having a roughness value that is between about 60 and 80 Angstroms at an interface to said dielectric layer; and a conductive layer on said dielectric layer.
- 2. The structure of claim 1 wherein the first polysilicon layer has a thickness between about 2,000 and 3,800 Angstroms.
Parent Case Info
This is a division of patent application Ser. No. 09/049,212, filing date Mar. 27,1998, now U.S. Pat. No. 5,874,333 Polysilicon Layer Having Improved Roughness After POCl3 Doping, assigned to the same assignee as the present invention.
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