In many electronic devices, integrated circuit (IC) chips and/or semiconductor dies are connected to larger circuit boards such as motherboards and/or other types of printed circuit boards (PCBs) via a package substrate. Some package substrates include a glass substrate (e.g., a glass core) having one or more openings extending between first and second sides of the glass substrate. Conductive material may be provided in the openings to electrically couple devices (e.g., the IC chips and/or semiconductor dies) to each other and/or to a PCB.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
While the example IC package 100 of
As shown in the illustrated example, each of the dies 108, 110 is electrically and mechanically coupled to the package substrate 112 via corresponding arrays of interconnects 116. In
As shown in
As used herein, the bridge bumps 120 are bumps on the dies 108, 110 through which electrical signals pass between different ones of the dies 108, 110 within the IC package 100. Thus, as shown in the illustrated example, the bridge bumps 120 of the first die 108 are electrically coupled to the bridge bumps 120 of the second die 110 via an interconnect bridge 128 (e.g., a silicon-based interconnect bridge, an interconnect die, an embedded interconnect bridge (EMIB)) embedded in the package substrate 112. As represented in
In some examples, an underfill material 130 is disposed between the dies 108, 110 and the package substrate 112 around and/or between the first level interconnects 116 (e.g., around and/or between the core bumps 118 and/or the bridge bumps 120). In the illustrated example, only the first die 108 is associated with the underfill material 130. However, in other examples, both dies 108, 110 are associated with the underfill material 130. In other examples, the underfill material 130 is omitted. In some examples, the mold compound used for the package lid 114 is used as an underfill material that surrounds the first level interconnects 116.
In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and/or inductors disposed on the package mounting surface 106 of the package substrate 112 and/or the die mounting surface 124 of the package substrate 112.
In
In some examples, the glass core 132 is an amorphous solid glass layer. In some examples, the glass core 132 is a layer of glass that does not include an organic adhesive or an organic material. In some examples, the glass core 132 is a solid layer of glass having a rectangular shape in plan view. In some examples, the glass core 132, as a glass substrate, includes at least one glass layer and does not include epoxy and does not include glass fibers (e.g., does not include an epoxy-based prepreg layer with glass cloth). In some examples, the core 132 corresponds to a single piece of glass that extends the full height/thickness of the core. In other examples, the glass core 132 can be silicon, a dielectric material and/or any other material(s).
In some examples, the glass core 132 has a rectangular shape that is substantially coextensive, in plan view, with the layers above and/or below the core. In some examples, the glass core 132 has a thickness in a range of about 50 micrometers (μm) to about 1.4 millimeters (mm). In some examples, the glass core 132 can be a multi-layer glass substrate (e.g., a coreless substrate), where a glass layer has a thickness in a range of about 25 μm to about 50 μm. In some examples, the glass core 132 can have dimensions of about 10 mm on a side to about 250 mm on a side (e.g., 10 mm by 10 mm to 250 mm by 250 mm). In some examples, the glass core 132 corresponds to a rectangular prism volume with sections (e.g., vias) removed and filled with other materials (e.g., metal). Among other things, glass cores are advantageous over epoxy-based cores because glass is stiffer and, therefore, provides for greater mechanical support or strength for the package substrate. Thus, the glass core 132 is an example means for strengthening the package substrate.
The first and second build-up regions 134, 136 are represented in
Using glass as a starting core material (e.g., the glass core 132 of
While glass cores provide a number of benefits and advantages, they also present certain challenges. For instance, differences in the coefficients of thermal expansion (CTEs) between copper and glass results in copper expanding and contracting more than the glass. As a result, the copper in a TGV that extends through a glass core (such as the glass core 132) can expand and contract relative to the glass core during thermal cycles (e.g., during a TGV annealing process and/or subsequent fabrication processes) thereby inducing stress in the glass. Such stress can result in reliability concerns based on a reduction in the strength of the glass core, the formation and/or propagation of cracks in the glass core, and/or other breaks or failures of the glass core. Efforts to mitigate these concerns include the deposition of a thin film liner between the glass core and the copper of a TGV to serve as a buffer that absorbs at least some of the stress induced by the expansion and contraction of the copper relative to the glass. However, many known liners are difficult to apply to the glass and often require expensive equipment for the coating process. Further, many known liners use materials that often crack and/or fail during certain types of plating processes to add copper into TGVs. Further still, many known liners are limited to specific circumstances of particular substrate designs and become less effective for different designs (based on different structures and/or different materials involved).
Examples disclosed herein involve thin film liners made of porous materials that can be applied using easier and less expensive processes than known techniques. Furthermore, in some examples, the porosity of the thin film material can be modulated and reformulated to adapt to different use cases associated with different materials and/or different structures. Furthermore, the example porous thin film materials disclosed herein and the associated methods of application are compatible with any type of TGV plating process.
In some examples, as represented in the inset image of
In some examples, the voids 504 between different portions of the bonded structural material 408 are interconnected (e.g., in communication) to define an open channel 506 (e.g., an open fluid path, a fluid channel, etc.) that extends through a thickness of the porous material 502. That is, in some examples, the porous material 502 has an open-form matrix (e.g., an open-cell porous structure). Notably, the open channel 506 may not be straight but tortuous as represented by the arrow representing the channel 506 in
As discussed above, in some examples, the structural material 408 is a polymer (e.g., a polymer solution) dissolved within a solvent (e.g., the carrier agent 410). In some such examples, the subsequent processing of the material mixture 402 results in a cross-linked polymer matrix to produce the final porous material 502 represented in
As with the powder-based approach discussed above, this non-solvent induced phase separation approach can be implemented with any suitable polymers to achieve any suitable mechanical and/or chemical properties as well as any suitable porosity and/or pore size for the porous material 502. Further, similar to what is discussed above, the nature of the non-solvent induced phase separation process results in an open-cell porous structure with continuous fluid channel(s) (e.g., the open channel 506) extending through the porous material 502.
In some examples, the material mixture 402 dispensed within the through-holes 302 (as represented in
In the illustrated example of
Significantly, the highest amounts of stress induced by the CTE mismatch between the conductive material 604 and the glass panel 202 typically occur at the ends of the TGVs 602 (e.g., adjacent the first and second surfaces 204, 206). Accordingly, in some examples, the dispensing of the material mixture 402 is controlled to achieve a suitable thickness at those regions with less concern for the thickness of the material mixture 402 (and the resulting porous material 502) at other regions (e.g., near a midpoint of the TGVs 602). In some examples, controlling the thickness of the material mixture 402 is achieved by balancing out (e.g., tuning, adjusting, optimizing, etc.) the material properties (e.g., viscosity, surface tension, etc.) with the process parameters (e.g., jetting rate, vacuum pulling from the backside, temperature, etc.).
The example process begins at block 1502 by providing a glass panel (such as the glass panel 202 shown in
At block 1508, the example process involves processing the mixture 402 to remove the carrier agent 410 and produce a porous material (e.g., the porous material 502 shown in
At block 1510, the example process involves determining whether to deposit more of the mixture 402. For instance, in the example described above in connection with
At block 1512, the example process involves determining whether to remove the porous material 502 from the outer surfaces (e.g., the first and second surfaces 204, 206) of the glass panel 202. If so (e.g., to fabricate the example glass cores 600, 1200 of
At block 1516, the example process involves depositing (e.g., plating) a conductive material (e.g., the conductive material 604 shown in
The example IC package 100 including any one of the example glass cores 600, 1200, 1300, 1400 of
The IC device 1700 may include one or more device layers 1704 disposed on and/or above the die substrate 1702. The device layer 1704 may include features of one or more transistors 1740 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1702. The device layer 1704 may include, for example, one or more source and/or drain (S/D) regions 1720, a gate 1722 to control current flow between the S/D regions 1720, and one or more S/D contacts 1724 to route electrical signals to/from the S/D regions 1720. The transistors 1740 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1740 are not limited to the type and configuration depicted in
Each transistor 1740 may include a gate 1722 including a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and/or zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and/or lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1740 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and/or any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and/or aluminum carbide), and/or any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 1740 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1702 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1702. In other examples, at least one of the metal layers that form the gate electrode may be a planar layer that is substantially parallel to the top surface of the die substrate 1702 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1702. In other examples, the gate electrode may include a combination of U-shaped structures and/or planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and/or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1720 may be formed within the die substrate 1702 adjacent to the gate 1722 of corresponding transistor(s) 1740. The S/D regions 1720 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1702 to form the S/D regions 1720. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1702 may follow the ion-implantation process. In the latter process, the die substrate 1702 may first be etched to form recesses at the locations of the S/D regions 1720. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1720. In some implementations, the S/D regions 1720 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1720 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1720.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1740) of the device layer 1704 through one or more interconnect layers disposed on the device layer 1704 (illustrated in
The interconnect structures 1728 may be arranged within the interconnect layers 1706-2010 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1728 depicted in
In some examples, the interconnect structures 1728 may include lines 1728a and/or vias 1728b filled with an electrically conductive material such as a metal. The lines 1728a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1702 upon which the device layer 1704 is formed. For example, the lines 1728a may route electrical signals in a direction in and/or out of the page from the perspective of
The interconnect layers 1706-2010 may include a dielectric material 1726 disposed between the interconnect structures 1728, as shown in
A first interconnect layer 1706 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1704. In some examples, the first interconnect layer 1706 may include lines 1728a and/or vias 1728b, as shown. The lines 1728a of the first interconnect layer 1706 may be coupled with contacts (e.g., the S/D contacts 1724) of the device layer 1704.
A second interconnect layer 1708 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1706. In some examples, the second interconnect layer 1708 may include vias 1728b to couple the lines 1728a of the second interconnect layer 1708 with the lines 1728a of the first interconnect layer 1706. Although the lines 1728a and the vias 1728b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1708) for the sake of clarity, the lines 1728a and the vias 1728b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 1710 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1708 according to similar techniques and/or configurations described in connection with the second interconnect layer 1708 or the first interconnect layer 1706. In some examples, the interconnect layers that are “higher up” in the metallization stack 1719 in the IC device 1700 (i.e., further away from the device layer 1704) may be thicker.
The IC device 1700 may include a solder resist material 1734 (e.g., polyimide or similar material) and one or more conductive contacts 1736 formed on the interconnect layers 1706-2010. In
In some examples, the circuit board 1802 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1802. In other examples, the circuit board 1802 may be a non-PCB substrate.
The IC device assembly 1800 illustrated in
The package-on-interposer structure 1836 may include an IC package 1820 coupled to an interposer 1804 by coupling components 1818. The coupling components 1818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1816. Although a single IC package 1820 is shown in
In some examples, the interposer 1804 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1804 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1804 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1804 may include metal interconnects 1808 and vias 1810, including but not limited to through-silicon vias (TSVs) 1806. The interposer 1804 may further include embedded devices 1814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1804. The package-on-interposer structure 1836 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1800 may include an IC package 1824 coupled to the first face 1840 of the circuit board 1802 by coupling components 1822. The coupling components 1822 may take the form of any of the examples discussed above with reference to the coupling components 1816, and the IC package 1824 may take the form of any of the examples discussed above with reference to the IC package 1820.
The IC device assembly 1800 illustrated in
Additionally, in various examples, the electrical device 1900 may not include one or more of the components illustrated in
The electrical device 1900 may include programmable circuitry 1902 (e.g., one or more processing devices). The programmable circuitry 1902 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1900 may include a memory 1904, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1904 may include memory that shares a die with the programmable circuitry 1902. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1900 may include a communication chip 1912 (e.g., one or more communication chips). For example, the communication chip 1912 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1912 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1912 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1912 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1912 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1912 may operate in accordance with other wireless protocols in other examples. The electrical device 1900 may include an antenna 1922 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1912 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1912 may include multiple communication chips. For instance, a first communication chip 1912 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1912 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1912 may be dedicated to wireless communications, and a second communication chip 1912 may be dedicated to wired communications.
The electrical device 1900 may include battery/power circuitry 1914. The battery/power circuitry 1914 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1900 to an energy source separate from the electrical device 1900 (e.g., AC line power).
The electrical device 1900 may include a display 1906 (or corresponding interface circuitry, as discussed above). The display 1906 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1900 may include an audio output device 1908 (or corresponding interface circuitry, as discussed above). The audio output device 1908 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1900 may include an audio input device 1918 (or corresponding interface circuitry, as discussed above). The audio input device 1918 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1900 may include GPS circuitry 1916. The GPS circuitry 1916 may be in communication with a satellite-based system and may receive a location of the electrical device 1900, as known in the art.
The electrical device 1900 may include any other output device 1910 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1910 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1900 may include any other input device 1920 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1920 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1900 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1900 may be any other electronic device that processes data.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified herein.
As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+1 second.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that include a porous material as a thin film liner between the conductive material of TGVs in a glass core and the surrounding sidewalls of the through-hole within which the conductive material is disposed. The porous nature of the material allows for deformation to absorb stress and/or strain that can arise, for example, from a CTE mismatch between the conductive material and the surrounding glass.
Further examples and combinations thereof include the following:
Example 1 includes an apparatus comprising a glass layer having a through-hole, a conductive material within the through-hole, and a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.
Example 2 includes the apparatus of example 1, wherein the at least the portion of the sidewall includes a first portion adjacent a first end of the through-hole, and the porous material is between the conductive material and at least a second portion of the sidewall adjacent a second end of the through-hole, at least a third portion of the sidewall between the at least the first portion and the at least the second portion, the porous material spaced apart from the at least the third portion.
Example 3 includes the apparatus of example 2, wherein the at least the first portion extends a first length along the through-hole, the at least the second portion extends a second length along the through-hole, and the at least the third portion extends a third length along the through-hole, the third length greater than the first length and greater than the second length.
Example 4 includes the apparatus of example 3, wherein the first and second lengths are less than 20 micrometers.
Example 5 includes the apparatus of any one of examples 1-4, wherein the porous material extends a full length along the sidewall of the through-hole from opposing first and second surfaces of the glass layer.
Example 6 includes the apparatus of example 5, wherein the porous material has a first thickness on the sidewall adjacent the first surface and a second thickness on the sidewall adjacent the second surface, the first thickness different from the second thickness.
Example 7 includes the apparatus of any one of examples 1-6, wherein the porous material is defined by a plurality of pores within a polymer matrix, and adjacent ones of the pores define an open channel through a thickness of the porous material.
Example 8 includes the apparatus of any one of examples 1-7, wherein the glass layer includes a first surface and a second surface opposite the first surface, the through-hole extends between the first and second surfaces, and the porous material extends along at least one of the first surface or the second surface.
Example 9 includes the apparatus of any one of examples 1-8, wherein the glass layer includes a first surface and a second surface opposite the first surface, the through-hole extends between the first and second surfaces, the porous material spaced apart from the first and second surfaces.
Example 10 includes the apparatus of any one of examples 1-9, wherein the porous material includes at least one of a polymer or a ceramic.
Example 11 includes the apparatus of any one of examples 1-10, wherein the porous material includes a metal.
Example 12 includes an apparatus comprising a glass core having a first surface and a second surface opposite the first surface, the glass core including an opening, the opening including a metal extending between the first and second surfaces, and a material coating an inner surface of the opening between the metal and the inner surface, the material including voids, the voids providing a porosity of at least 10%.
Example 13 includes the apparatus of example 12, wherein the material coats less than all of the inner surface of the opening.
Example 14 includes the apparatus of any one of examples 12 or 13, wherein the voids define at least one fluid channel.
Example 15 includes the apparatus of any one of examples 12-14, wherein a thickness of the material differs at different depths within the opening.
Example 16 includes the apparatus of any one of examples 12-15, wherein the material coats the first surface of the glass core.
Example 17 includes an apparatus comprising a semiconductor die, a substrate to support the semiconductor die, the substrate including a glass core, the glass core having a through-glass via (TGV) extending therethrough, the TGV including metal electrically coupled to the semiconductor die, and a porous liner at least partially surrounding an outer sidewall of the metal in the TGV.
Example 18 includes the apparatus of example 17, wherein the porous liner completely surrounds the outer sidewall of the metal along a full length of the TGV.
Example 19 includes the apparatus of any one of examples 17 or 18, wherein the porous liner at least partially surrounds opposing ends of the outer sidewall of the metal and is spaced apart from a central segment of the TGV.
Example 20 includes the apparatus of any one of examples 17-19, wherein the porous liner has a porosity of at least 25%.
Example 21 includes a method comprising providing a through-hole in a glass core, depositing a mixture onto a sidewall of the through-hole, the mixture including a material within a carrier agent, processing the glass core to remove the carrier agent and cause the material to produce a porous structure, and depositing a conductive material within the through-hole, the porous structure between the sidewall of the through-hole and the conductive material.
Example 22 includes the method of example 21, wherein the carrier agent is a liquid solvent and the depositing of the mixture is implemented by at least one of slit coating or spin coating the mixture across a surface of the glass core.
Example 23 includes the method of example 22, wherein the mixture is deposited on a first side of the glass core in a first coating process and a second side of the glass core in a second coating process, a first portion of the mixture to extend partially into the through-hole at a first end adjacent the first side of the glass core during the first coating process, a second portion of the mixture to extend partially into the through-hole at a second end adjacent the second side of the glass core during the second coating process.
Example 24 includes the method of example 23, wherein the second portion of the mixture is to remain spaced apart from the first portion of the mixture.
Example 25 includes the method of any one of examples 22-24, wherein the material is a polymer and the processing of the glass core includes applying a non-solvent liquid to facilitate removal of the carrier agent.
Example 26 includes the method of example 25, wherein the processing of the glass core includes applying heat to remove the non-solvent liquid.
Example 27 includes the method of any one of examples 21-26, wherein the material is at least one of a micro powder or a nano powder, and the carrier agent is at least one of a binder or a solvent that defines a paste with the at least one of the micro powder or the nano powder disposed therein.
Example 28 includes the method of example 27, wherein the processing of the glass core includes implementing a sintering process.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.