Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device

Abstract

A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. A similar embodiment represents grid routing technique where the signals are routed between layers N and N+1. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of the present invention pertains to circuitry to solve the problems caused by capacitive and inductive coupling in signals in an integrated circuit device. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).

2. Related Art

With their growth in commercial markets and consumer demands for smaller Integrated Circuits (ICs—which are used in numerous applications such as cellular phones, wristwatch cameras, and hand-held organizers just to name a few) increase, IC size requirement trends continue towards a small form factor and lowered power consumption. As these IC size requirements shrink, semiconductor manufacturers are forced to design circuits at a much smaller level than in the past. Previously, as the industry moved from Very Large Scale Integration (VLSI) to Ultra Large Scale Integration (ULSI), the relative capacitive and inductive coupling of the circuit itself was not realized to be as critical of an issue.

However, as the semiconductor industry designs and implements circuitry on sub-micron level technology (where spacing between circuitry lines is less than 10⁻⁶ m) and beyond, the capacitive and inductive coupling of the signal lines within the circuitry itself is realized to be a critical problem for designers. As circuit size becomes smaller and the relative distances for signal lines becomes longer, the problem of coupling and or cross talk between signal lines and ground or power lines becomes more evident. Furthermore, as the signal line to ground coupling and/or other signal lines becomes stronger, the signal to noise ratio for given signals increases proportionally. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).

One prior art approach to minimize the signal to noise ratio (or capacitive and inductive coupling), is to strengthen the signal drive level. By increasing the signal strength, the total signal to noise ratio is reduced. Unfortunately, to increase the signal strength, the device must also be supplied higher power. This solution is inconsistent with the modern trend of reducing power consumption in ICs for heat issues, portability issues and environmental issues. In addition to higher power requirement, this prior art approach does not eliminate the coupling issue.

Another prior art approach is to reduce the effective (R-L-C) impedance of the signal lines and thereby increasing the spacing between signal lines. In general, increasing the spacing between signal lines by three-fold, the coupling effect will only be reduced by fifty percent. This prior art approach is usually combined with the first prior art approach to minimize coupling and reduce signal to noise ratio. This approach is inconsistent with modern trends for circuit compactness.

Yet another prior art approach is to shield the signal lines by using either a supply voltage like VDD or ground. Utilizing this prior art approach, the shielding line (ground) would need to be wide enough (with low impedance) so that the shield itself will not begin to transfer the noise to other signal lines.

These prior art approaches that tend to compensate by increasing signal strength combined with the prior art approach of providing a shielding line adjacent to signal line are shown in FIG. 1. As shown in this depiction, 100, the signal line 110 is routed along with the shielding line 120, which is then utilized to shield the noise from a neighboring signal line. For sub-micron technologies, the lengths of these signal and shield lines can become relatively long with respect to line thickness and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate. Therefore, a need exists for reducing the capacitive and inductive signal coupling effects of routing resources of an IC device.

SUMMARY OF THE INVENTION

Accordingly, the present invention minimizes and reduces the signal coupling effects caused by. capacitive and/or inductive signal coupling effects of routing in an integrated circuit device. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

The present invention discloses a circuit composed of a power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing an integrated circuit device. The shield mesh is included in addition to the power and ground grid typically provided in an IC. The units of the shield mesh are placed such that they surround routing resources of the integrated circuit. Specifically, one embodiment of the present invention describes a method of routing a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Alternating mesh lines of VDD and VSS (or ground) are laid down and signal routing resources are placed in-between. The shield mesh can be single or multi-layered. The shield mesh is included in addition to a power grid and may be connected to the power grid.

As Very Deep Sub-Micron (VDSM) technologies continue to reduce in size (for example from 0.18 uM, 0.15 uM, 0.13 uM, 0.11 uM and beyond), the signal lines become even more susceptible to capacitive and inductive coupling and noise from other neighboring signal lines. Relatively long signal lines are routed in between fully connected power and ground shielding mesh which is typically generated by a router during the signal routing phase or during power mesh routing phase. In one embodiment, leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device.

Another embodiment of the invention describes a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment of the invention presents a multi-layer grid routing technique where signals are routed on an even grid and the power and ground lines are routed on an odd grid. A similar embodiment of the invention represents grid routing technique where the signals are routed between layers N and N+1. While another embodiment of the invention enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments of the invention also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded, thereby reducing the effective resistive or RC component of the power or grounding lines.

More specifically, an embodiment of the present invention is drawn to an integrated circuit device comprising: a) a plurality of signal lines disposed within a substrate; b) a power grid disposed on the substrate and comprising: a plurality of power lines having a first thickness; and a plurality of ground lines having the first thickness, the power grid for supplying power and ground to circuitry of the substrate; and c) a shield mesh disposed on the substrate and comprising: a plurality of power lines having a second thickness; and a plurality of ground lines having the second thickness, wherein respective signal lines of the plurality of signal lines are disposed between a respective power line of the shield mesh and a respective ground line of the shield mesh, the shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of the plurality of signal lines. Embodiments include the above and wherein the power and ground lines of the shield mesh are alternatively disposed and parallel to each other within a single metal layer of the substrate.

Other embodiments include an integrated circuit as described above generally and wherein the power and ground lines of the shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer of the substrate and wherein the power and ground lines of the shield. mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer of the substrate, the second metal layer being underneath the first metal layer and wherein the first and second directions are 90 degrees apart.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not by way of limitations in the figures accompanying drawings in which like reference numerals refers to similar elements and in which:

FIG. 1 shows a top view of a shielding line and a signal line.

FIG. 2 shows a top view of two layers indicating a grid layout according to a shield mesh of one embodiment of the present invention.

FIG. 3 shows a planar 2-D view of a shield mesh where the signal lines 1 and 2 of same thickness between VDD and VSS lines are on the same layer according to another embodiment of the present invention.

FIG. 4 shows a top view of a shield mesh comprising of two adjacent layers depicting signal lines and VDD and VSS lines on each layer and the appropriate vias between the two layers.

FIG. 5 shows a vertical cross-sectional view of a shield mesh having several layers with signal lines, VDD and VSS lines with their appropriate vias on odd/even grid tracks.

FIG. 6 shows a top view of two adjacent layers of a shield mesh indicating signals, the VDD and VSS lines in a gridless routing technique with their appropriate vias.

FIG. 7 shows a vertical cross-sectional view of a gridless routing embodiment of the shield mesh showing the signal lines with VDD and VSS lines and their appropriate vias.

FIG. 8 shows a shielding mesh within a power grid on said substrate according to one embodiment of the present invention.

FIG. 9 depicts the shielding mesh within a channel on said substrate and within a block on said substrate according to another embodiment of the present invention.

FIG. 10 shows a block diagram depicting a process from logic synthesis to placer to router to tape.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the embodiments of the invention, a shield power and ground mesh to remove both capacitive and inductive signal coupling effects of routing in ASIC chips, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to obscure aspects of the present invention unnecessarily.

The present invention describes a circuit device that comprises a plurality of signal lines of given thickness disposed within a substrate that will in addition to providing power to the circuitry of said substrate circuit, will also perform as a shielding mesh that is utilized to reduce the effects of cross-talk between nearby signal lines of said plurality of signal lines within said circuit

As shown in depiction 100 of FIG. 1, the signal line 110 is routed along with the shielding line 120, which is then utilized to shield the noise from a neighboring signal line. As discussed earlier, for sub-micron technologies, the lengths of these signal and shield lines can become relatively long (up to 100 uM) with respect to line thickness (for example: as short as 0.13 uM) and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate.

According to one embodiment of the present invention, 200, FIG. 2 depicts a single signal line, 210, which is shielded on both sides by utilizing a three dimensional shield mesh of alternating VDD and VSS lines. On another layer, e.g. metal 4, these alternating VDD and VSS lines are running perpendicular (at 90 degrees) from the previous layer, for example: metal 3, and are further connected at junctions formed by VIA3, 230, to form a three dimensional shield mesh of VDD and VSS shield lines for signal line 220. In accordance with one embodiment of the present invention it is appreciated that the shield mesh is included on an IC in addition to a power grid used to supply power and ground to the circuitry. According to another embodiment, for example in a 0.25 uM technology, the relative segment distance of the VDD and VSS lines may be reduced by as much as 0.94 uM. Reducing the segment length of VDD and VSS reduces their effective RC component and thereby reducing the coupling effects of noise.

According to another embodiment, 300, of the present invention, FIG. 3 depicts a planar, perspective view of the shield mesh where signal lines 310 and 320 of same thickness are interwoven between alternating VDD and VSS lines on the same layer and of same thickness. Therefore, FIG. 3 illustrates a single layer embodiment of the shield mesh of the present invention. According to an embodiment of shield mesh of the present invention, FIG. 3 illustrates the fact that the due to close proximity of the shielding lines coupled with the fact that these shielding lines will consist of relatively short segments, it can be derived that the effective RC impedance is reduced and thereby the signal coupling between signal lines 310 and 320 is further reduced. According to another embodiment, FIG. 3 also illustrates that the signal lines 310 and 320 are isolated with alternating VDD and VSS shield mesh of the same thickness; depending on technology used, thickness can vary from 0.25 uM to 0.13 uM and even smaller as the industry trends toward further reduction.

FIG. 4 is a top view of shield mesh embodiment 400 showing two adjacent substrate layers, 405A and 405B, depicting the signal lines (410, 420 and 430), alternating VDD and VSS lines on each layer and the appropriate vias between the two layers utilizing a grid layout. Each via provides layer connections and also reduces the segment size of the shielding mesh and thereby reduces the effective R-C resistance according to one embodiment of the present invention. It is important to note that on layer N, 405A, if the signal lines 410, 420 and 430 are on odd grid tracks, then the VDD and VSS lines will be on even grid tracks, and vice-versa. Like wise, on layer N+1, 405B, if the signal lines 440, 450 and 460 are on even tracks, then the VDD and VSS lines will alternately be on odd grid tracks and vice-versa.

Multi-layer routing assignment to signals and shields: for the vertical space, the track assignment should be done so that there would not be signal tracks directly on top of one another to avoid top bottom coupling. For example, if signals on layer N are on odd tracks, signals on layer N+2, which has the same routing direction as layer N, would be routed on even tracks. This strategy would enable the signals to be shielded by opposite power/ground both on the left/right, and on top/bottom. Thereby, further reducing the segment lengths and increasing the effective isolation between signal lines to reduce noise coupling.

FIG. 5 shows a vertical cross-sectional view of another embodiment 500 of the present invention, that depicts the three dimensional aspect of the shield grid mesh. Several layers, N through N+7, are shown with signals and alternating VDD and VSS lines and their appropriate vias on odd/even grid tracks. As seen FIG. 5, the cross-sectional cuts are taken across signal lines (510 and 520) and VDDNSS lines (530 and 540, respectively). As shown on layer N, layer N+2, layer N+4 and N+6, the VDD, signal and VSS lines are also alternatively arranged on odd, even tracks as described in FIG. 4. Therefore, the shield mesh of FIG. 5 is grid line aligned. Another embodiment of the present invention connects adjacent layers by means of vias as shown in elements 560A through 560N. According to another embodiment of the present invention, this multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects.

FIG. 6 shows another embodiment, 600, of the present invention which depicts a top view of two adjacent layers indicating the signal and alternating VDD and VSS lines in a gridless routing shield mesh with their appropriate vias. As shown, signal 640 is routed on two separate layers and is shielded by a gridless mesh, which includes adjacent VDD (620ABB) and VSS (630ABB) lines on one layer. The same 640 signal line is shielded by VDD (620B) and VSS (630A) lines on another adjacent layer that are 90 degrees alignment to the first layer. Signal line, 640, in this example is routed again on the previous layer, again 90 degrees apart, and is shielded by VDD (620ABA) and VSS (630ABA) lines. Likewise, according to another embodiment of the present invention, signal lines 610A, 610B and 610C can also be traced to have shielding on both adjacent (side-by-side) layers as well as vertical (top-to-bottom) layers. This multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects in a gridless routing technique.

According to another embodiment, 700, of the present invention, FIG. 7 shows a vertical cross-sectional view of a gridless shielding mesh showing signals and alternating VDD and VSS lines with their appropriate vias for connecting between adjacent layers. As shown in vias 710 and 720, the distance between segment size is not bound by grid width. This gridless example can again be seen in vias 730 and 740. According to another embodiment of the present invention, vias of varying sizes can be utilized in as close proximity as possible without dependency of grid size. Utilizing the close proximity of the vias, relative segment lengths of each signal, VDD or VSS shielding mesh is reduced. According to another embodiment of the present invention, the shielding mesh is utilized to provide a path for connecting an integrated circuit device to the main power grid. As shown in FIG. 7, line 740 is connected using two short segments, 710 and 720 to tap to the shielding mesh of either VDD or VSS which are in turn connected to the main power grid.

According to embodiment, 800, FIG. 8 shows an integrated circuit with a shielding mesh (820) and a power grid (810) on a substrate. The shielding mesh is utilized to reduce the capacitive and inductive effects of cross-talk while the power grid is provided to deliver power and ground to IC circuits. The lines of the power grid are much larger than the VSS and VDD lines of the shielding mesh, which are sized to be the size of the signal lines. According to this embodiment, the size difference between the shielding mesh lines and the true power grid lines may vary by factor of 2 to factor of 10. However, due to their relative small segment lengths, the shielding mesh in function, reduces the effective RC component of the lines being connected to. This in turn reduces the noise and coupling effect and therefore, the shielding mesh can be deployed on any substrate area where routing resources are used.

FIG. 9 depicts embodiment 900, which depicts a shielding mesh in the routing channel (910) between blocks on a substrate and also within a block (920) of a substrate. As described in FIG. 8, due to relative small segment lengths of the shielding mesh, the shielding mesh further reduces the effective RC component of the routing line thereby reducing the noise and coupling effects caused by cross-talk between signal lines.

FIG. 10 illustrates the flow chart of steps for the process, 1000, of an EDA tool in which the shielding mesh of the present invention may be introduced. As shown in this embodiment of the present invention, initial code is generally written using HDL, step 1010, (for example) after which logic synthesis, step 1020, is performed. Placement of a power grid is next performed as shown in block 1030. For example where substrate grid is is utilized, shielding mesh as outlined in one embodiment of the present invention can be introduced as shown at point 1040. After this point, the router, 1050, will route the designed circuit and handle the shielding mesh within its parameters. At this point, the design is put on tape (1060).

However, it is important to note that it is not necessary to introduce the shielding mesh on a substrate grid. As described earlier, another embodiment of the present invention allows for said shielding mesh to be introduced in a gridless design on a given substrate. For gridless routing, router (1050) can introduce the shielding mesh into the said substrate.

This fully connected power and ground shielding mesh can be used when it is important to remove capacitive and inductive coupling. The main sources for this mesh would be from the main power grid trunks or independent power and ground trunks dedicated for shielding where they are relatively noiseless.

The shielding mesh can also be used in standard cell or gate array routing area, routing channels or routing channels on top of hard macros, data bus routing, control bus routing, address bus routing, analog signal routing, clocks and clock bus routing, or any other signal lines.

With the addition of this fully connected power and ground shielding mesh, the automated VDSM chip routing can be much more worry-free, and almost unpredictable coupling errors can be virtually eradicated by the present invention.

Claims

1.-20. (canceled)

21. An integrated circuit device, comprising: a substrate; circuitry disposed on said substrate; a plurality of signal lines disposed on said substrate to interconnect portions of said circuitry on said substrate; a power grid disposed on said substrate, the power grid comprising: a plurality of first lines having a first thickness to supply a first voltage level to said circuitry on said substrate; and a plurality of second lines to supply a second voltage level to said circuitry on said substrate; a shield mesh disposed on said substrate, the shield mesh comprising: a plurality of third lines having a second thickness to supply a third voltage level on said substrate; and a plurality of fourth lines to supply a fourth voltage level on said substrate; wherein each of said signal lines is disposed between and adjacent to a respective one of said third lines of said shield mesh and a respective one of said fourth lines of said shield mesh within a layer on said substrate to reduce effects of electronic cross-talk between nearby ones of said signal lines; and wherein the first thickness is more than the second thickness; and, a first portion of said first lines of said power grid and a first portion of said third lines of said shield mesh are within a first layer on said substrate.

22. An integrated circuit as in claim 21, wherein said first and second voltage levels are ground and power respectively; and, said third and fourth voltage levels are VSS and VDD respectively.

23. An integrated circuit as in claim 21, wherein segment lengths of said third and fourth lines of said shield mesh are substantially smaller than segment lengths of said first and second lines of said power grid.

24. An integrated circuit as in claim 21, wherein said first portion of said first lines and said first portion of said third lines are parallel along a first direction within said first layer on said substrate; a second portion of said first lines and a second portion of said third lines are parallel along a second direction within a second layer on said substrate; and, said first direction is in an angle with said second direction.

25. An integrated circuit as in claim 24, wherein said shield mesh further comprises a plurality of vias interconnecting said first and second portions of said third lines.

26. An integrated circuit device, comprising: a substrate; circuitry disposed on said substrate; a plurality of signal lines disposed on said substrate to interconnect portions of said circuitry on said substrate; a power grid disposed on said substrate, the power grid comprising: a plurality of first lines having a first thickness to supply a first voltage level to said circuitry on said substrate; and a plurality of second lines to supply a second voltage level to said circuitry on said substrate; a shield mesh disposed on said substrate, the shield mesh comprising: a plurality of third lines having a second thickness to supply a third voltage level on said substrate; and a plurality of fourth lines to supply a fourth voltage level on said substrate; wherein each of said signal lines is disposed between and adjacent to a respective one of said third lines of said shield mesh and a respective one of said fourth lines of said shield mesh within a respective layer on said substrate to reduce effects of electronic cross-talk between nearby ones of said signal lines; and wherein, perpendicularly across layers of said substrate, each of said signal lines is vertically adjacent to at least one of a parallel one of said third lines of said shield mesh and a parallel one of said fourth lines of said shield mesh but not vertically adjacent to a parallel signal line.

27. An integrated circuit as in claim 26, wherein said first and second voltage levels are ground and power respectively; and, said third and fourth voltage levels are VSS and VDD respectively; and wherein each of said signal lines is vertically and horizontally shielded.

28. An integrated circuit as in claim 26, wherein said shield mesh further comprises: first vias interconnecting said third lines across layers of said substrate; and, second vias interconnecting said fourth lines across layers of said substrate.

29. An integrated circuit device, comprising: a substrate; circuitry disposed on said substrate; a plurality of signal lines disposed on said substrate to interconnect portions of said circuitry on said substrate; a power grid disposed on said substrate, the power grid comprising: a plurality of first lines to supply a first voltage level to said circuitry on said substrate; and a plurality of second lines to supply a second voltage level to said circuitry on said substrate; a shield mesh disposed on said substrate, the shield mesh comprising: a plurality of third lines to supply a third voltage level to said circuitry on said substrate; and a plurality of fourth lines to supply a fourth voltage level to said circuitry on said substrate; wherein each of said signal lines is disposed between and adjacent to a respective one of said third lines of said shield mesh and a respective one of said fourth lines of said shield mesh within a layer on said substrate to reduce effects of electronic cross-talk between nearby parallel ones of said signal lines; and wherein said third lines and said fourth lines are gridless.

30. An integrated circuit as in claim 29, wherein said shield mesh further comprises: first vias interconnecting said third lines across layers of said substrate in close proximity without dependency of grid size; and, second vias interconnecting said fourth lines across layers of said substrate in close proximity without dependency of grid size.

31. An integrated circuit as in claim 30, wherein said first and second vias are of varying sizes.

32. An integrated circuit as in claim 29, wherein said shield mesh has varying segment sizes that are not bound by grid width.

33. An integrated circuit as in claim 29, wherein said first lines and said second lines have a first thickness; and, said third lines, said fourth lines and said signal lines have a second thickness.

34. An integrated circuit device, comprising: a substrate; circuitry disposed on said substrate; a plurality of signal lines disposed on said substrate to interconnect portions of said circuitry on said substrate; a shield mesh disposed on said substrate, the shield mesh comprising: a plurality of first lines to supply a first reference voltage level on said substrate; and a plurality of second lines to supply a second reference voltage level on said substrate; two vias both connecting a first one of said signal lines to a second one of said signal lines, said first one and said second one of said signal lines being within a first layer and a second layer on said substrate respectively, said first one and said second one of said signal lines running in an angle; wherein each of said signal lines is disposed between and adjacent to a respective one of said first lines of said shield mesh and a respective one of said second lines of said shield mesh within a layer on said substrate to reduce effects of electronic cross-talk between nearby ones of said signal lines.

35. An integrated circuit as in claim 34, wherein said first one of said signal lines runs in a first direction in said first layer; said second one of said signal lines runs in a second direction in said second layer; and, said first and second directions are 90 degrees apart.

36. An integrated circuit as in claim 34, wherein said two vias are adjacent each other.

37. An integrated circuit as in claim 34, wherein said first lines and said second lines have a same first thickness.

38. An integrated circuit as in claim 37, wherein said first and second reference voltage levels are ground and power respectively.

39. An integrated circuit device as in claim 37, further comprising: a power grid disposed on said substrate, the power grid comprising: a plurality of third lines having a second thickness to supply a third voltage level to said circuitry on said substrate; and a plurality of fourth lines to supply a fourth voltage level to said circuitry on said substrate; wherein said second thickness is substantially larger than said first thickness.

40. An integrated circuit as in claim 39, wherein said fourth lines have said second thickness.

41. An integrated circuit as in claim 40, wherein said first and second reference voltage levels are VSS and VDD respectively; and, said third and fourth voltage levels are ground and power respectively.

42. An integrated circuit device as in claim 39, wherein said shield mesh further comprises: a plurality of first vias in close proximity interconnecting said first lines of said shield mesh across layers of said substrate; and, a plurality of second vias in close proximity interconnecting said second lines of said shield mesh across layers of said substrate.

43. A method of designing an integrated circuit (IC), said method comprising: creating a representation of a shielding mesh in at least one layer of said IC, said shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage; creating a representation of a power grid in said at least one layer of said IC, said power grid having a plurality of first reference voltage lines and a plurality of second reference voltage lines, said power grid for supplying power to circuitry in said IC, and wherein said plurality of first and second reference voltage lines have either: (a) an average line spacing which is substantially larger than an average line spacing in said shielding mesh, or (b) a thickness which is larger than lines in said shielding mesh.

44. A method as in claim 43, wherein the method is performed at least in part by an EDA tool.

45. A method as in claim 44, wherein said method uses initial code written in an HDL.

46. A method as in claim 44, further comprising: creating a representation of a plurality of signal lines routed through said shielding mesh.

47. A method of designing an integrated circuit (IC), said method comprising: creating a representation of a shielding mesh in at least a first and second layers of said IC, said shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage; creating a representation of a plurality of signal lines in said shielding mesh, wherein perpendicularly across layers of said IC, each of said signal lines is vertically adjacent to at least one of a parallel one of said first plurality of lines and a parallel one of said second plurality of lines but not vertically adjacent to a parallel signal line.

48. A method as in claim 47, wherein the method is performed at least in part by an EDA tool.

49. A method as in claim 47, wherein said method uses initial code written in an HDL.

50. A method of designing an integrated circuit (IC), said method comprising: creating a representation of a shielding mesh in at least one layer of said IC, said shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage; creating a representation of a plurality of signal lines routed through said shielding mesh, wherein said shielding mesh is gridless.

51. A method as in claim 50, wherein the method is performed at least in part by an EDA tool.

52. A method as in claim 51, wherein said method uses initial code written in an HDL.

53. An integrated circuit (IC), comprising: a shielding mesh having a first layer and a second layer, the first layer having a first conductor, the second layer having a second conductor; and two vias each connecting from the first conductor of the first layer to the second conductor of the second layer.

54. The integrated circuit of claim 53, wherein the first conductor and the second conductor are not parallel.

55. The integrated circuit of claim 53, wherein the first conductor and the second conductor are in close proximity.

56. The integrated circuit of claim 55, wherein a distance between the first conductor and the second conductor is smaller than an average spacing between parallel lines of the shielding mesh.

57. A machine readable medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method of designing an integrated circuit (IC), the method comprising: generating a representation of a shielding mesh having a first layer and a second layer, the first layer including a first conductor, the second layer including a second conductor; and generating a representation of two vias, each of the two vias connecting from the first conductor to the second conductor.

58. The medium of claim 57, wherein the first conductor and the second conductor are not parallel.

59. The medium of claim 57, wherein the first conductor and the second conductor are in close proximity.

60. A data processing system for designing an integrated circuit (IC), the system comprising: means for generating a representation of a shielding mesh having a first layer and a second layer, the first layer including a first conductor, the second layer including a second conductor; and means for generating a representation of two vias, each of the two vias connecting from the first conductor to the second conductor.

61. The system of claim 60, wherein the first conductor and the second conductor are not parallel.

62. The system of claim 61, wherein the first conductor and the second conductor are in close proximity.