Patent Application
20230307534
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0036930, filed on Mar. 24, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The present disclosure relates to a power device and a method of manufacturing the power device.
Various power conversion systems may require devices that control currents through ON/OFF switching, that is, power devices. The efficiency of power devices may determine the efficiency of power conversion systems.
It may be difficult to increase the efficiency of power devices based on silicon (Si) due to limitations in physical properties of silicon and limitations in manufacturing processes. In order to overcome the limitations, research or development is being conducted to increase conversion efficiency by applying a III-V-based compound semiconductor, such as GaN, to power devices.
Example embodiments provide a power device and a method of manufacturing the power device.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an embodiment, a power device may include a channel layer; a source electrode and a drain electrode on both sides of the channel layer, respectively; a gate electrode over the channel layer between the source electrode and the drain electrode; a first field plate above the gate electrode and extending in a direction from the gate electrode toward the drain electrode, the first field plate including a metal; and a high-k dielectric layer on a lower surface of the first field plate, a side surface of the first field plate, or both the lower surface of the first field plate and the side surface of the first field plate.
In some embodiments, the first field plate may contact the source electrode and may be integral with the source electrode.
In some embodiments, the first field plate may have a thickness of 10 nm to 10 μm.
In some embodiments, the high-k dielectric layer may have a thickness of 100 nm to 3 μm.
In some embodiments, the high-k dielectric layer may include at least one of SiON, SiN, Al2O3, HfO, and ZrO.
In some embodiments, the high-k dielectric layer may fill a space between the first field plate and the gate electrode.
In some embodiments, the power device may further include a low-k dielectric layer covering the first field plate and the high-k dielectric layer.
In some embodiments, the low-k dielectric layer may include SiO.
In some embodiments, the power device may further include a low-k dielectric layer in a space between the first field plate and the gate electrode.
In some embodiments, the low-k dielectric layer may have a thickness of 100 nm to 3 μm.
In some embodiments, a plurality of first field plates may be above the gate electrode. The first field plate may be one of the plurality of first field plates. Lengths of the plurality of first field plates may gradually increase in the direction from the gate electrode toward the drain electrode as a distance of the plurality of first plates increases from the channel layer.
In some embodiments, the plurality of first field plates may increase in thickness as a distance of the plurality of first field plates increase from the channel layer increases.
In some embodiments, a plurality of high-k dielectric layers may be on the plurality of first field plates. The high-k dielectric layer may be one of the plurality of high-k dielectric layers, and thicknesses of the plurality of high-k dielectric layers may increase as a distance of the plurality of high-k dielectric layers from the channel layer increases.
In some embodiments, a second field plate may be connected to the drain electrode and may extend in a direction from the drain electrode toward the gate electrode.
In some embodiments, the channel layer may include a GaN-based material.
In some embodiments, a barrier layer may be on the channel layer. The barrier layer may be configured to induce a 2-dimensional electron gas (2 DEG) in the channel layer.
In some embodiments, the barrier layer may include a nitride including at least one of Al, Ga, In, and B.
In some embodiments, the gate electrode may include at least one of Ni, Pt, Pd, and Au.
In some embodiments, the power device may further include an insulating layer between the channel layer and the gate electrode.
In some embodiments, the insulating layer may include at least one of SiO, SiN, SiON, AlO, and AlON.
In some embodiments, the gate electrode may include at least one of Ti, Al, Ni, Pt, Pd, and Au.
In some embodiments, the power device may further include a depletion forming layer between the channel layer and the gate electrode.
In some embodiments, the depletion forming layer may include a p-type III-V-based nitride semiconductor.
In some embodiments, the gate electrode may include at least one of Ti, Al, Ni, Pt, Pd, and Au.
According to an embodiment, a method of manufacturing a power device may include forming a gate electrode on a channel layer; forming a low-k dielectric layer on the channel layer, the low-k dielectric layer covering the gate electrode; forming a first high-k dielectric layer on an upper surface of the low-k dielectric layer; forming a metal layer on a side surface of the first high-k dielectric layer, a side surface of the low-k dielectric layer, and an upper surface of the first high-k dielectric layer; and forming a source electrode on a side of the channel layer. The forming the source electrode may include etching a portion of the metal layer and a portion of the first high-k dielectric layer, and at a same time forming a field plate on the upper surface of the first high-k dielectric layer.
In some embodiments, the low-k dielectric layer may include SiO.
In some embodiments, the first high-k dielectric layer may include at least one of SiON, SiN, Al2O3, HfO, and ZrO.
In some embodiments, in the forming the source electrode, the metal layer and the first high-k dielectric layer may be etched by a single photo process.
In some embodiments, in the forming the source electrode, the field plate may be formed above the gate electrode and may be formed to extend in a direction from the gate electrode toward a drain electrode, and the first high-k dielectric layer may be formed on a lower surface of the field plate.
In some embodiments, the method may further include forming a second high-k dielectric layer covering the field plate and the low-k dielectric layer and etching the second high-k dielectric layer such that the second high-k dielectric layer remains only on a side surface of the field plate.
In some embodiments, the second high-k dielectric layer may be formed by isotropic deposition, and the etching the second high-k dielectric layer may be performed by anisotropic etching.
According to an embodiment, a method of manufacturing a power device may include forming a gate electrode on a channel layer; forming a low-k dielectric layer on the channel layer, the low-k dielectric layer covering the gate electrode; forming a metal layer on a side surface of the low-k dielectric layer and an upper surface of the low-k dielectric layer; forming a source electrode on a side of the channel layer, the forming the source electrode including etching a portion of the metal layer and at a same time forming a field plate on the upper surface of the low-k dielectric layer; forming a high-k dielectric layer covering the field plate and the low-k dielectric layer; and etching the high-k dielectric layer such that the high-k dielectric layer remains only on a side surface of the field plate.
According to an embodiment, a method of manufacturing a power device may include forming a gate electrode on a channel layer; forming a high-k dielectric layer on the channel layer, the high-k dielectric layer covering the gate electrode; forming a metal layer on a side surface of the high-k dielectric layer and an upper surface of the high-k dielectric layer; forming a source electrode on a side of the channel layer, the forming the source electrode including etching a portion of the metal layer and a portion the high-k dielectric layer, and at a same time forming a field plate on the upper surface of the high-k dielectric layer; and forming a low-k dielectric layer covering the field plate and the high-k dielectric layer.
According to an embodiment, a power device may include a channel layer; a source electrode, a gate electrode, and a drain electrode spaced apart from each other in a first direction on the channel layer, the gate electrode between the source electrode and the drain electrode; a first metal structure on the source electrode and spaced apart from the gate electrode; and a high-k dielectric layer. The first metal structure may include a first field plate. The first field plate may extend in the first direction over the gate electrode such that a lower surface of the first field plate faces the gate electrode. A side surface of the first field plate may be over a region of the channel layer between the gate electrode and the drain electrode. The high-k dielectric layer may be on the lower surface of the first field plate, the side surface of the first field plate, or both the lower surface of the first field plate and the side surface of the first field plate.
In some embodiments, the first metal structure may include a vertical portion. The vertical portion may extend from a top surface of the source electrode in a direction perpendicular to the top surface of the source electrode. The first field plate may extend in the first direction from a sidewall of the vertical portion.
In some embodiments, the first metal structure may include a plurality of first field plates spaced apart from each other in the vertical direction along the vertical portion of the first metal structure. The plurality of first field plates may include the first field plate. The plurality of first field plates may extend different lengths in the first direction.
In some embodiments, a plurality high-k dielectric layers may be on lower surfaces of the plurality of first field plates, side surfaces of the plurality of first field plates, or both the lower surfaces of the plurality of first field plates and the side surfaces of the plurality of first field plates.
In some embodiments, a second metal structure may be on the drain electrode. The second metal structure may be spaced apart from the gate electrode and the first metal structure. The second metal structure may include a second field plate. The second field plate may extend toward to the first metal structure in a direction opposite the first direction.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.
Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and a size of each component in the drawings may be exaggerated for the sake of clear and convenient description. In addition, the following embodiments to be described are merely examples, and various modifications may be made from the embodiments.
Hereinafter, what is described as “upper portion” or “on or upper” may also include not only components directly thereon, thereunder, on the left, and on the right in contact therewith but also components thereon, thereunder, on the left, and on the right without being in contact therewith. Singular expressions include plural expressions unless the context clearly indicates otherwise. In addition, when a portion “includes” a certain component, this means that other components may be further included rather than excluding other components unless specifically stated to the contrary.
Use of a term “the” and similar reference terms may correspond to both the singular and the plural. Steps constituting a method may be performed in any suitable order unless there is a clear statement that the steps should be performed in the order described or contrary to the order and are not limited thereto.
In addition, terms such as “. . . unit”, “. . . portion”, and “module” described in the specification mean units that process at least one function or operation, which may be implemented as hardware or software, or as a combination of hardware and software.
Connection or connection members of lines between configuration elements illustrated in the drawings exemplarily represent functional connections and/or physical or circuit connections and may be represented as alternative or additional various functional connections, physical connections, or circuit connections in an actual apparatus.
Use of all examples or all example terms is merely for describing technical ideas in detail, and the scope of claims is not limited by the examples or the example terms unless limited by the claims.
The following example embodiments describe, for example, a high electron mobility transistor (HEMT) as a power device but is not limited thereto.
The HEMT includes semiconductor layers with different electrical polarization characteristics. In the HEMT, a semiconductor layer with a relatively large polarizability may induce 2-dimensional electron gas (2 DEG) in another semiconductor layer bonded thereto, and the 2 DEG may have very high electron mobility.
Referring to
The channel layer 110 may include a first semiconductor material. Here, the first semiconductor material may include a III-V-based compound semiconductor material but is not limited thereto. For example, the channel layer 110 may include a GaN-based material layer, for example, a GaN layer. In this case, the channel layer 110 may include an undoped GaN layer, or in some cases, a GaN layer doped with a certain impurity.
A buffer layer (not illustrated) may be further provided between the channel layer 110 and a substrate. The buffer layer is provided to reduce differences in lattice constants and thermal expansion coefficients between the substrate and the channel layer 110. The buffer layer may include a nitride including at least one of Al, Ga, In, and B and may have a single-layer structure or multi-layer structure. For example, the buffer layer may include at least one of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. A seed layer (not illustrated) for growth of the buffer layer may also be further provided between the substrate and the buffer layer.
The barrier layer 120 may be provided on the channel layer 110. The barrier layer 120 may induce a 2 DEG in the channel layer 110. Here, the 2 DEG may be induced in the channel layer 110 beneath an interface between the channel layer 110 and the barrier layer 120. The barrier layer 120 may include a second semiconductor material that is different from the first semiconductor material forming the channel layer 110. The second semiconductor material may be different from the first semiconductor material in at least one of polarization characteristics, an energy bandgap, and a lattice constant.
The second semiconductor material may be greater than the first semiconductor material in at least one of polarizability and an energy bandgap. The barrier layer 120 may include a nitride including at least one of, for example, Al, Ga, In, and B. In a specific example, the barrier layer 120 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, the present disclosure is not limited thereto. The barrier layer 120 may include an undoped layer, but it may also include a layer doped with a certain impurity. The barrier layer may have a single-layer structure or a multi-layer structure.
A source electrode 141 and a drain electrode 142 may be provided on both sides of the barrier layer 120. The source electrode 141 and the drain electrode 142 may be provided to extend in a y-axis direction in parallel with each other. The source electrode 141 and the drain electrode 142 may include, for example, a metal material, such as Al or Ti.
A gate electrode 130 may be provided on the barrier layer 120 between the source electrode 141 and the drain electrode 142. The gate electrode 130 may extend in the y-axis direction in parallel with the source electrode 141 and the drain electrode 142. The gate electrode 130 may include a conductive material, such as a metal material or a metal compound. For example, the gate electrode 130 may include at least one of Ni, Pt, Pd, and Au. However, the present disclosure is not limited thereto. The gate electrode 130 may have a thickness of, for example, about 100 nm to about 300 nm, but this is merely an example.
A field plate 160 is provided above the gate electrode 130. The field plate 160 may extend from above the gate electrode 130 toward the drain electrode 142 (that is, in the x-axis direction). The field plate 160 may be connected to the source electrode 141. The field plate 160 may be formed integrally with the source electrode 141. The field plate 160 may include a metal material, such as Al or Ti.
In an OFF state of an HEMT, the 2 DEG is depleted to apply a high electric field to an edge portion of a gate electrode, and thus, a breakdown voltage may reduce or a leakage current may increase. In the present embodiment, by providing the field plate 160 above the gate electrode 130, an electric field applied to an edge portion of the gate electrode 130 may disperse, and accordingly, a breakdown voltage may increase and a leakage current may reduce.
The field plate 160 may have a thickness of, for example, about 10 nm to about 10 μm. For example, when the field plate 160 is formed of metal only for the purpose of dispersion of an electric field only, the field plate 160 may have a thickness of about 10 nm to about 100 nm. For example, when the field plate 160 is formed of a metal for wiring of an integrated circuit (IC), the field plate 160 may have a thickness of about 100 nm to about 1 μm. For example, when the field plate 160 is formed of a metal for power wiring for reducing source and drain resistance, the field plate 160 may have a thickness of about 3 μm to about 10 μm. However, this is merely an example.
A high-k dielectric layer 170 may be provided on the lower surface of the field plate 160. The high-k dielectric layer 170 may include a dielectric material with a dielectric constant that is greater than a dielectric constant of silicon oxide. For example, the high-k dielectric layer 170 may include at least one of SiON, SiN, Al2O3, HfO, and ZrO. However, the present disclosure is not limited thereto.
The high-k dielectric layer 170 provided on the lower surface of the field plate 160 may disperse more effectively an electric field applied to an edge portion of the gate electrode 130, thereby further increasing a breakdown voltage thereof. The high-k dielectric layer 170 may have a thickness of, for example, about 100 nm to about 3 μm. However, the present disclosure is not limited thereto.
A low-k dielectric layer 150 may be provided between the high-k dielectric layer 170 and the barrier layer 120. The low-k dielectric layer 150 may be provided on the barrier layer 120 to cover the gate electrode 130 and the drain electrode 142.
The low-k dielectric layer 150 may include a material with a dielectric constant that is less than a dielectric constant of the high-k dielectric layer 170. For example, the low-k dielectric layer 150 may include SiO. However, this is merely an example. The low-k dielectric layer 150 may have a thickness of, for example, about 100 nm to about 3 μm but is not limited thereto.
In the power device 100 according to the present embodiment, the field plate 160 extending toward the drain electrode 142 is provided above the gate electrode 130, and thus, an electric field applied to an edge portion of the gate electrode 130 may disperse. In addition, by providing the high-k dielectric layer 170 on the lower surface of the field plate 160, the electric field applied to the edge portion of the gate electrode 130 may be dispersed more effectively. Accordingly, a breakdown voltage may increase and a leakage current may reduce, and thus, the power device 100 with improved high voltage characteristics and reliability may be implemented.
Although a metal-semiconductor (MES) gate structure in which the gate electrode 130 is directly provided on the barrier layer 120 is described above, an insulating layer may be provided between the barrier layer 120 and the gate electrode 130, or a depletion forming layer may be provided between the barrier layer 120 and the gate electrode 130 as described below.
The gate electrode 130 may include at least one of, for example, Ti, Al, Ni, Pt, Pd, and Au. However, this is merely an example. The gate electrode 130 may have a thickness of, for example, about 100 nm to about 300 nm, and the depletion forming layer 136 may have a thickness of, for example, about 50 nm to about 100 nm. However, the present disclosure is not limited thereto.
The depletion forming layer 136 may increase an energy bandgap of a portion of the barrier layer 120 thereunder, and thus, a depletion region of 2 DEG may be formed in a portion of the channel layer 110 corresponding to the depletion forming layer 136. Due to the depletion region, a power device may have normally-off characteristics in which there is no current flowing between the drain electrode 142 and the source electrode 141 when the gate voltage is 0 V.
In general, when an HEMT is in a normally-on state in which, when a gate voltage is 0 V, a current flows due to low resistance between a drain electrode and a source electrode, current and power may be consumed. In order to limit and/or prevent a current from flowing between the drain electrode and the source electrode in a normally-on HEMT, a negative voltage has to be applied to the gate electrode. However, the depletion forming layer 136 may be provided between the barrier layer 120 and the gate electrode 130 to provide a HEMT with normally-off characteristics, where there is no current flowing between the drain electrode 142 and the source electrode 141 when the gate voltage is 0 V.
Referring to
The gate electrode 130 may be formed on the barrier layer 120. The gate electrode 130 may include at least one of, for example, Ni, Pt, Pd, and Au. The gate electrode 130 may have a thickness of, for example, about 100 nm to about 300 nm. However, the present disclosure is not limited thereto. In addition, the insulating layer 135 may be further formed between the barrier layer 120 and the gate electrode 130, as illustrated in
The low-k dielectric layer 150 may be formed on the barrier layer 120 to cover the gate electrode 130. The low-k dielectric layer 150 may include a dielectric material with a dielectric constant that is less than a dielectric constant of the high-k dielectric layer 170, as described below. The low-k dielectric layer 150 may include, for example, SiO but is not limited thereto. The low-k dielectric layer 150 may be formed to have a thickness of, for example, about 100 nm to about 3 μm.
The high-k dielectric layer 170 may be formed on the low-k dielectric layer 150. The high-k dielectric layer 170 may include a dielectric material with a dielectric constant that is greater than a dielectric constant of a silicon oxide. For example, the high-k dielectric layer 170 may include at least one of SiON, SiN, Al2O3, HfO, and ZrO but is not limited thereto. The high-k dielectric layer 170 may be formed to have a thickness of, for example, about 100 nm to about 3 μm.
Referring to
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Referring to
Accordingly, the source electrode 141 forming an ohmic contact with the barrier layer 120 may be formed on one side of the low-k dielectric layer 150, and the field plate 160 may be formed on the upper surface of the high-k dielectric layer 170. That is, the high-k dielectric layer 170 may be formed on the lower surface of the field plate 160. In addition, although not illustrated in
Referring to
A high-k dielectric layer 270 may be provided in the field plate 260. The high-k dielectric layer 270 may include a first high-k dielectric layer 270a provided on the lower surface of the field plate 260 and a second high-k dielectric layer 270b provided on a side surface of the field plate 260. The high-k dielectric layer 270 may include at least one of, for example, SiON, SiN, Al2O3, HfO, and ZrO. A low-k dielectric layer 250 may be provided between the high-k dielectric layer 270 and the barrier layer 120. The low-k dielectric layer 250 may be provided on the barrier layer 120 to cover the gate electrode 130 and the drain electrode 242. The low-k dielectric layer 250 may include, for example, SiO, but this is merely an example.
In the present embodiment, the high-k dielectric layer 270 may be provided not only on the lower surface of the field plate 260 but also on the side surface of the field plate 260, and thus, an electric field applied to an edge portion of the gate electrode 130 may more effectively disperse.
The present embodiment performs the processes illustrated in
Referring to
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Referring to
Referring to
A high-k dielectric layer 370 may be provided on a side surface of the field plate 360. A low-k dielectric layer 350 may be provided between the field plate 360 and the barrier layer 120. The low-k dielectric layer 350 may be provided over the barrier layer 120 to cover the gate electrode 130 and the drain electrode 342. In the present embodiment, the high-k dielectric layer 370 may be provided on a side surface of the field plate 360, and thus, an electric field applied to an edge portion of the gate electrode 130 may effectively disperse.
Referring to
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Referring to
A high-k dielectric layer 470 may be provided on the lower surface of the field plate 460 to cover the gate electrode 130. The high-k dielectric layer 470 may fill a space between the field plate 460 and the gate electrode 130. A low-k dielectric layer 450 may be provided on the field plate 460. Specifically, the low-k dielectric layer 450 may be provided on the barrier layer 120 to cover the field plate 460, the high-k dielectric layer 470, and the drain electrode 442.
Referring to
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First to third field plates 560a, 560b, and 560c may be provided above the gate electrode 130. Here, the first to third field plates 560a, 560b, and 560c may be provided integrally with the source electrode 541. Specifically, the first to third field plates 560a, 560b, and 560c may be sequentially provided above the gate electrode 130 to be separated from each other in the z-axis direction. The first to third field plates 560a, 560b, and 560c may extend toward the drain electrode 542 in the x-axis direction.
In order to more effectively disperse an electric field applied to an edge portion of the gate electrode 130, the first to third field plates 560a, 560b, and 560c may be disposed to increase in length as a distance from the channel layer 130 in a vertical direction (z-axis direction) increases. For example, as shown in
Although
Each of high-k dielectric layers 570a, 570b, and 570c may be provided on a lower surface and a side surface of respectively each of the first to third field plates 560a, 560b, and 560c.
A low-k dielectric layer 550 may be provided between the first to third field plates 560a, 560b, and 560c and the barrier layer 120. The low-k dielectric layer 550 may cover the gate electrode 130 and the drain electrode 542 and may fill spaces between the first to third field plates 560a, 560b, and 560c.
Referring
First, second, and third high-k dielectric layers 570a′, 570b′, and 570c′ respectively provided on the first to third field plates 560a′, 560b′, and 560c′ may increase in thickness as the distance from the channel layer 110 increases. For example, in a case in which the first to third field plates 560a′, 560b′, and 560c′ are sequentially provided as a distance from the channel layer 110 increases, the first high-k dielectric layer 570a′ provided on the first field plate 560a′ may have a thickness t1, the second high-k dielectric layer 570b′ provided on the second field plate 560b′ may have a thickness t2 (>t1), and the third high-k dielectric layer 570c′ provided on the third field plate 560c′ may have a thickness t3 (>t2).
As such, the first to third field plates 560a′, 560b′, and 560c′ and the first, second, and third high-k dielectric layers 570a′, 570b′, 570c′ may increase in thickness as the distance from the channel layer 110 increases, and thus, an electric field formed at an edge portion of the gate electrode 130 may more effectively disperse.
Referring to
A plurality of first field plates 661a, 661b, and 661c may be provided above the gate electrode 130. Here, each of the first field plates 661a, 661b, and 661c may extend toward the drain electrode 642 (in the x-axis direction). The first field plates 661a, 661b, and 661c may be provided integrally with the source electrode 641. As the first field plates 661a, 661b, and 661c increase in length toward the drain electrode 642 (the x-axis direction), the distance from the channel layer 130 in a vertical direction (the z-axis direction) may increase.
First high-k dielectric layers 671a, 671 b, and 671c may be respectively provided on the first field plates 661a, 661b, and 661c. Here, each of the first high-k dielectric layers 671a, 671b, and 671c may be respectively provided on at least one of a lower surface and a side surface of each of the first field plates 661a, 661b, and 661c. In addition, the first high-k dielectric layers 671a, 671b, and 671c may be respectively provided only on some of the first field plates 661a, 661b, and 661c.
A plurality of second field plates 662a, 662b, and 662c may be provided on the drain electrode 642. Here, the plurality of second field plates 662a, 662b, and 662c may extend toward the gate electrode 130 (in the -x-axis direction). The plurality of second field plates 662a, 662b, and 662c may be provided integrally with the drain electrode 642. As the plurality of second field plates 662a, 662b, and 662c increase in length toward the gate electrode 130 (-x-axis direction), distances from the channel layer 130 in the vertical direction (the z-axis direction) may increase.
Second high-k dielectric layers 672a, 672b, and 672c may be respectively provided on the plurality of second field plates 662a, 662b, and 662c. Here, each of the second high-k dielectric layers 672a, 672b, and 672c may be respectively provided on at least one of a lower surface and a side surface of each of the second field plates 662a, 662b, and 662c. In addition, the second high-k dielectric layers 672a, 672b, and 672c may be respectively provided only on some of the second field plates 662a, 662b, and 662c.
A low-k dielectric layer 650 may be provided between the first and second field plates 661a, 661b, and 661c and 662a, 662b, and 662c and the barrier layer 120. The low-k dielectric layer 650 may fill spaces between the first field plates 661a, 661b, and 661c and spaces between the second field plates 662a, 662b, and 662c.
According to the example embodiments described above, an electric field applied to an edge portion of a gate electrode may be dispersed by providing a field plate extending toward a drain electrode on an upper portion of the gate electrode. In addition, an electric field applied to an edge portion of a gate electrode may be dispersed more effectively by providing a high-k dielectric layer on at least one of a lower surface and a side surface of a field plate. Accordingly, a breakdown voltage may increase and a leakage current may reduce to implement a power device with improved high voltage characteristics and reliability.
Power devices according to example embodiments may be applied to various electronic systems and/or devices.
As an example,
Referring to
As another example,
As shown in
The processing circuitry 1520 may include, and/or may be implemented by, one or more instances of processing circuitry such as hardware including logic circuits, a hardware/software combination such as a processor executing software; or a combination thereof.
In some example embodiments, the electronic device 1500 may include one or more additional components (not shown) coupled to the bus 1510, which may include, for example, a power supply, a light sensor, a light-emitting device, any combination thereof, or the like. In some example embodiments, one or more of the processing circuitry 1520, memory 1530, or one or more additional components may include a power device according to any one of the example embodiments described herein, such as any one of the power devices 100, 200, 300, 400, 500, 500′, and 600 in
One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0036930 | Mar 2022 | KR | national |
