Patent Application
20240292564
The present disclosure relates to printed circuit boards, and particularly to printed circuit boards with power devices embedded therein.
Printed circuit boards (PCBs) are typically used for mechanical support and electrical connection of electronic components using conductive pathways of copper sheets laminated onto a non-conductive substrate. And multi-layer PCBs provide higher capacity and/or density of electronic components in a smaller footprint by incorporating two or more layers. However, the design and/or manufacture of multilayer PCBs can be difficult.
The present disclosure addresses issues related to the manufacture of multi-layer PCBs and other issues related to multi-layer PCBs.
This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features.
In one form of the present disclosure, an assembly includes a cold plate, a power electronics embedded printed circuit board (PCB), and a low thermal resistance (LTR) dielectric layer sandwiched between the cold plate and the power electronics embedded PCB such that the power electronics embedded PCB is bonded to the cold plate via the LTR dielectric layer and forms a highly integrated power electronics embedded PCB—cold plate assembly is formed.
In another form of the present disclosure, a highly integrated power electronics embedded PCB—cold plate assembly includes a cold plate, a power electronics embedded PCB, and a LTR dielectric layer sandwiched between and directly bonded to the cold plate and the power electronics embedded PCB.
In still another form of the present disclosure, a method includes laminating a LTR dielectric layer onto a cold plate fabrication panel, the cold plate fabrication panel including a plurality of individual cold plate units, bonding a power electronics embedded PCB fabrication panel to the LTR dielectric layer using high temperature and high pressure and forming an integrated power electronics PCB—cold plate fabrication panel, and cutting the integrated power electronics PCB—cold plate fabrication panel into a plurality of individual highly integrated power electronics embedded PCB—cold plate units.
Further areas of applicability and various methods of enhancing the above technology will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
The present teachings will become more fully understood from the detailed description and the accompanying drawings, wherein:
It should be noted that the figures set forth herein are intended to exemplify the general characteristics of the methods, devices, and systems among those of the present technology, for the purpose of the description of certain aspects. The figures may not precisely reflect the characteristics of any given aspect and are not necessarily intended to define or limit specific forms or variations within the scope of this technology.
The present disclosure provides highly integrated power electronics embedded PCB—cold plate assemblies with desired heat transfer, and reduced normal and shear stresses, between a cold plate and a power electronics embedded PCB bonded thereto. As used herein, the phrase “highly integrated power electronics embedded PCB” refers to a single multi-layer PCB module or unit with two or more power semiconductor devices (also referred to herein simply as “power device”), control/drive/protection electronic circuitry, and passive components, embedded therein. Also, as used herein, the phrase “power device” refers to a semiconductor device used as a switch or rectifier in power electronics. The cold plate can be fluid cooled such that temperatures of the one or more power device—substrate assemblies during operation remain below a predefined temperature. In addition, the multi-layer PCB with the one or more power device—substrate assemblies embedded therein is electrically isolated from the cold plate via a low thermal resistance dielectric layer.
Referring now to
In some variations, the power layers 110 are formed from a glass reinforced epoxy laminate dielectric material (e.g., FR-4), or other dielectric material, with the conductive material 114 embedded therein. In other variations, the power layers 110 are 3D printed using a dielectric material ink to form the dielectric material 112, with the conductive material 114 embedded therein. And in at least one variation, the conductive material 114 is also 3D printed with a conductive material ink. Non limiting examples of dielectric material inks are inks that include UV-curable dielectric materials such as UV-curable acrylated monomer selected from one or more of an acrylate epoxy, an acrylate polyester, an acrylate urethane, and an acrylate silicone, among others. And non-limiting examples of conductive material inks are inks that include silver nanoparticles and/or graphene nanosheets, among others. It should be understood that the dielectric layers 100 can also be formed from a glass reinforced epoxy laminate dielectric material (e.g., FR-4), or other dielectric material, or 3D printed using a dielectric material ink.
The dielectric layers 100 and the power layers 110 have a predefined average thickness (z-direction). For example, in some variations, the predefined average thickness is between about 50 micrometers (μm) and about 250 μm, for example, between about 75 μm and about 200 μm. And in at least one variation, the predefined thickness is between about 75 μm and about 150 μm, for example, between about 80 μm and about 120 μm.
Referring to
In some variations, the power device—substrate assemblies 30 are totally embedded in the multi-layer PCB 10, i.e., one or more dielectric layers 100 and/or one or more power layers 110 are above (+z direction) the power device—substrate assemblies 30, and one or more dielectric layers 100 and/or one or more power layers 110 are below (−z direction) the power device—substrate assemblies 30. In other variations, the power device—substrate assemblies 30 form at least a portion of the lower surface 22 of the power electronics embedded PCB 20. For example, a lower surface 32 of one or more power device—substrate assemblies 30 is aligned or coplanar with the lower surface 22 of the power electronics embedded PCB 20 (not shown) such that the lower surfaces 22, 32 of the power electronics embedded PCB 20 and power device(s), respectively, are bonded to the cold plate via a low thermal resistance dielectric layer as described below.
The power electronics embedded PCB 20 is bonded to the cold plate 40 such that the power device—substrate assemblies 30 are in thermal communication with the cold plate 40. Accordingly, and during operation of the highly integrated power electronics embedded PCB—cold plate assembly 2, the power device—substrate assemblies 30 are cooled via the flow of heat from the power device—substrate assemblies 30 to the cold plate 40. In some variations, the cold plate 40 is formed form an electrically conductive material (e.g., aluminum) and it is desirable that a bonding interface between the power electronics embedded PCB 20 and the cold plate 40 exhibit desired electrical insulation and thermal conduction properties. And in at least one variation, the cold plate 40 includes an internal fluid chamber 41 with an inlet 44, an outlet 46, and porous, mesh-structured, machined, or cast heat sinks 43 disposed within the fluid chamber 41. As used herein, the phrase “bonding interface” refers to one or more layers employed or used to bond a power electronics embedded PCB to a cold plate. And in at least one variation, the phrase “bonding interface” refers to a low thermal resistance dielectric layer employed or used to bond a power electronics embedded PCB to a cold plate.
Still referring to
The LTR dielectric layer 120 can be formed from any dielectric material and/or dielectric composite material suitable to electrically isolate the power electronics embedded PCB 20 from the cold plate 40. In some variations, the LTR dielectric layer is a ceramic-polymer composite dielectric material such as BaTiO3-polymer dielectric materials, Pb(ZrxTi1-x)O3-polymer dielectric materials (0≤x≤1), and/or SrTiO3 dielectric materials, among others.
In some variations, the LTR dielectric layers according to the teachings of the present disclosure have an average thickness (z direction) less than about 250 μm, for example less than about 200 μm, less than about 150 μm, less than about 100 μm, less than about 50 μm, less than about 40 μm, less than about 30 μm, less than about 20 μm, or less than about 10 μm. In some variations the LTR dielectric layer has an average thickness between about 10 μm and about 50 μm, for example between about 20 μm and about 40 μm, or between about 25 μm and about 35 μm.
In some variations, the LTR dielectric layer 120 is bonded directly to the upper surface 42 of the cold plate 40, i.e., the LTR dielectric layer 120 is in direct contact with the upper surface 42. In at least one variation, the LTR dielectric layer 120 is bonded directly to the lower surface 22 of the power electronics embedded PCB 20. And in some variations, the LTR dielectric layer 120 is bonded directly to the upper surface 42 of the cold plate 40 and the lower surface 22 of the power electronics embedded PCB 20. As used herein, the phrase “directly bonded” refers to one component or layer being bonded to and in direct contact with another component or layer, i.e., without any additional components or layers therebetween. And while not shown in the figures, in some variations, a metallization layer can be included on an upper (+z direction) and/or lower (−z direction) surface of the LTR dielectric layer 120. For example, the cold plate 40 can be formed from an aluminum alloy and an aluminum and/or copper containing metallization layer can be included on the lower surface of the LTR dielectric layer 120. Also, the power electronics embedded PCB 20 can include a copper containing lower surface 22 and an aluminum and/or copper containing metallization layer can be included on the upper surface of the LTR dielectric layer 120.
In order to better illustrate the effectiveness of the highly integrated power electronics embedded PCB—cold plate assemblies disclosed herein, but not limit the scope thereof in any manner, results of thermal and mechanical stress simulations for the highly integrated power electronics embedded PCB—cold plate assembly 2 are provided and discussed below.
Referring to
The highly integrated power electronics embedded PCB—cold plate assembly 2 was modeled as having a power electronics embedded PCB 20 with six (6) SiC MOS power device—substrate assemblies 30 and a bonding interface formed or provided by a LTR dielectric layer 120 with a thermal conductivity of 3 W/m*K and a thickness of about 38 μm. Also, the highly integrated power electronics embedded PCB—cold plate assembly 2 was simulated as operating with six (6) MOSFET power devices and each MOSFET power device had a heat loss level of 286 W.
Regarding thermal simulation of the highly integrated power electronics embedded PCB—cold plate assembly 2 with the LTR dielectric layer 120 bonding interface, the maximum temperature of the SiC MOS power device—substrate assemblies 30 was about 142° C. (
Regarding normal stress simulation of the highly integrated power electronics embedded PCB—cold plate assembly 2 with the LTR dielectric layer 120 bonding interface (
And regarding shear stress simulation of the highly integrated power electronics embedded PCB—cold plate assembly 2 with the LTR dielectric layer 120 bonding interface (
Referring now to
Referring now to
The preceding description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or its uses. Work of the presently named inventors, to the extent it may be described in the background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present technology.
The block and/or flow diagrams in the figures illustrate the architecture, functionality, and/or operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the block diagram may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical “or.” It should be understood that the various steps within a method may be executed in different order without altering the principles of the present disclosure. Disclosure of ranges includes disclosure of all ranges and subdivided ranges within the entire range.
The headings (such as “Background” and “Summary”) and sub-headings used herein are intended only for the general organization of topics within the present disclosure and are not intended to limit the disclosure of the technology or any aspect thereof. The recitation of multiple variations or forms having stated features is not intended to exclude other variations or forms having additional features, or other variations or forms incorporating different combinations of the stated features.
As used herein the term “about” when related to numerical values herein refers to known commercial and/or experimental measurement variations or tolerances for the referenced quantity. In some variations, such known commercial and/or experimental measurement tolerances are +/−10% of the measured value, while in other variations such known commercial and/or experimental measurement tolerances are +/−5% of the measured value, while in still other variations such known commercial and/or experimental measurement tolerances are +/−2.5% of the measured value. And in at least one variation, such known commercial and/or experimental measurement tolerances are +/−1% of the measured value.
The terms “a” and “an,” as used herein, are defined as one or more than one. The term “plurality.” as used herein, is defined as two or more than two. The term “another,” as used herein, is defined as at least a second or more. The terms “including” and/or “having.” as used herein, are defined as comprising (i.e., open language). The phrase “at least one of . . . and . . . ” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. As an example, the phrase “at least one of A, B, and C” includes A only, B only, C only, or any combination thereof (e.g., AB, AC, BC, or ABC).
As used herein, the terms “comprise” and “include” and their variants are intended to be non-limiting, such that recitation of items in succession or a list is not to the exclusion of other like items that may also be useful in the devices and methods of this technology. Similarly, the terms “can” and “may” and their variants are intended to be non-limiting, such that recitation that a form or variation can or may comprise certain elements or features does not exclude other forms or variations of the present technology that do not contain those elements or features.
The broad teachings of the present disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the specification and the following claims. Reference herein to one variation, or various variations means that a particular feature, structure, or characteristic described in connection with a form or variation or particular system is included in at least one variation or form. The appearances of the phrase “in one variation” (or variations thereof) are not necessarily referring to the same variation or form. It should also be understood that the various method steps discussed herein do not have to be conducted in the same order as depicted, and not each method step is required in each variation or form.
The foregoing description of the forms and variations has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular form or variation are generally not limited to that particular form or variation, but, where applicable, are interchangeable and can be used in a selected form or variation, even if not specifically shown or described. The same may also be varied in many ways. Such variations should not be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.
