Power devices in wide bandgap semiconductor

Abstract

An insulated gate field effect transistor is disclosed. The transistor includes a semi-insulating silicon carbide substrate, an epitaxial layer of silicon carbide layer adjacent the semi-insulating substrate for providing a drift region having a first conductivity type, and source and drain regions in the epitaxial layer having the same conductivity type as the drift region. A channel region is in the epitaxial layer, has portions between the source and the drain regions, and has the opposite conductivity type from the source and drain regions. The transistor includes contacts to the epitaxial layer for the source, drain and channel regions, an insulating layer over the channel region of the epitaxial layer, and a gate contact adjacent the insulating layer and the channel region.

Description

BACKGROUND OF THE INVENTION

Patent Abstracts of Japan Publication No. 08213606 (published Aug. 20, 1996) describes a lateral high breakdown strength MOSFET having an n+ substrate. German publication No. 4325804 A1 describes a process for producing high-resistance SiC from low-resistance SiC starting material. U.S. Pat. No. 5,611,955 describes a high resistivity silicon carbide substrate for use in semiconductor devices. U.S. Pat. No. 5,378,912 describes a lateral semiconductor-on-insulator (SOI) device.

SUMMARY OF THE INVENTION

One object of the present invention is to provide devices which allow blocking of very high voltages without the need for a very thick drift region which must be grown by epitaxy.

Another object of the present invention is to provide a lateral power device structure, such as a very high voltage (greater than 1000 v up to and greater than 10000 v) power switching device, fabricated on a junction-isolated or semi-insulating substrate in a wide bandgap semiconductor having a breakdown field substantially greater than silicon.

Another object of the present invention is to provide such lateral power devices in the form of a lateral metal oxide semiconductor field effect transistor (MOSFET) or lateral insulated gate bipolar transistor (IGBT) on silicon carbide.

Accordingly, one preferred embodiment of the invention provides a lateral power device structure fabricated in an epilayer (epitaxially-grown layer) on a semi-insulating substrate, especially a semi-insulating silicon carbide substrate. Such a semi-insulating substrate can be achieved, for instance, by doping, e.g., with vanadium or similar dopant materials. The preferred devices include a semi-insulating silicon carbide substrate, and an epitaxially grown drift region (e.g., N−) adjacent the semi-insulating substrate (e.g., doped at a level of about 2-5×10 15 cm −3 ). A lateral semiconductor device, e.g., an insulated gate field effect transistor (or MOSFET) or IGBT is provided in the epilayer. Such devices include generally source and drain regions (e.g., both N+), an insulating layer (e.g., SiO 2 ), and a gate, e.g., formed of polysilicon. Other conventional semiconductor device features can also be included, as those skilled in the art will appreciate.

Additional objects, embodiments, and features of the invention will be apparent from the following description, and the drawings appended hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a preferred lateral power device of the present invention.

FIG. 2 shows depletion edges for several blocking voltages in an illustrative lateral power device of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

For the purposes of promoting an understanding of the principles of the invention, reference will now be made to certain preferred embodiments thereof and specific language will be used to describe the same.

FIG. 1 shows a preferred lateral power device 11 of the present invention. Device 11 includes a semi-insulating layer 12 , e.g., a semi-insulating silicon carbide substrate. Adjacent to layer 12 is an epitaxially-grown layer providing drift region 13 (e.g., N−). Drift region 13 may be doped, for example, at a level of about 2-5×10 15 at/cm −3 , and may have a thickness of up to about 15 μm, e.g., about 10 to about 15 μm. Provided within layer 13 are source and drain regions 14 and 15 (which of opposite character to drift region 13 , e.g., in the illustrated device N+; or, to provide an IGBT, drain region 15 can be P+), and a channel region 16 . Also provided in device 11 is an insulating layer 17 (e.g., SiO 2 ) covering the channel region 16 , and a gate 18 adjacent the insulating layer 17 , for example formed with polysilicon (doped). Additional features may also be included in the device, for example conductive materials such as metal(s) to provide leads at the source and drain.

In an illustrative device such as that illustrated in FIG. 1 , in the off, or blocking condition, the PN-junction will extend a depletion region about 56 μm into the N− region before avalanche breakdown occurs (assuming a doping of 2×10 15 cm −3 ). This would correspond to a drain voltage of V=Emax/2 V d =5600v. Lateral structures in accordance with the preferred devices of the invention are particularly advantageous, since silicon carbide wafers with epilayers of about 10-15 μm are currently readily available commercially. In the present invention, the semi-insulating substrate ensures that the substrate does not act as an equipotential boundary under the depleted drift region, which would confine the extent of the electric field to the regions under the base (P) region and under the drain (N+) region. Shown in FIG. 2 are approximate depletion edges for several blocking voltages in an illustrative device of the present invention.

Claims

1. A power switching device comprising:a substrate; an epitaxially grown drift region layer on said substrate; a source region, a drain region and a channel region provided within the drift region layer wherein said channel region is U-shaped and encircles the lower boundary of said source region; an insulating layer over portions of said source, drain, and channel regions; and characterized in that said substrate is a semi-insulating substrate.

2. The device of claim 1, wherein said semi-insulating substrate is doped with vanadium.

3. An insulated gate field effect transistor, comprising:a semi-insulating silicon carbide substrate; an epitaxial layer of silicon carbide on said semi-insulating substrate for providing a drift region having a first conductivity type and a first polarity; source and drain regions in said silicon carbide epitaxial layer having the same conductivity type and opposite polarity as said drift region; a channel region, provided within said epitaxial layer, of opposite conductivity type than said source, drain and drift regions, wherein said channel region is U-shaped and encircles the lower boundary of said source region; contacts to said epitaxial layer for said source and drain regions; an insulating layer on said epitaxial layer, laterally extending over a portion of said source, channel and drain regions; and a gate contact on said insulating layer, laterally extending over a portion of said source and channel regions.

4. The device of claim 3, wherein said source and drain are N+, said channel is P, and said drift region is N−.

5. An insulated gate bipolar transistor, comprising:a semi-insulating silicon carbide substrate; an epitaxial layer of silicon carbide on said semi-insulating substrate for providing a drift region having a first conductivity type; source and drain regions in said silicon carbide epitaxial layer having the same conductivity type and opposite polarity as said drift region; a channel region in said silicon carbide epitaxial layer, wherein said channel region is U-shaped and encircles the lower boundary of said source region, and having an opposite conductivity type from said source and drain regions; contacts to said epitaxial layer for said source and drain regions; an insulating layer on said epitaxial layer, laterally extending over a portion of said source, channel, and drain regions; and a gate contact on said insulating layer, laterally extending over a portion of said source and channel regions.

6. The device of claim 5, wherein said source is N+, said channel is P, said drain is N+ and said drift region is N−.

7. The device of claim 5, wherein said semi-insulating substrate is doped with vanadium.