Power MESFET Rectifier

Abstract

A rectifier MESFET includes an N-channel MESFET having its gate connected to its source, and at the same current density having a voltage drop lower than the gate Schottky diode. A Schottky diode may be connected in parallel with the N-channel device to provide over current protection. A Zener may also be connected in parallel to provide reverse voltage protection. A second N-channel device may be connected in parallel. The addition of the second N-channel provides two different operational mode: synchronous rectification where the majority of current flows through the low resistance first N-channel device and asynchronous rectification where the majority of current flows through the somewhat higher resistance first N-channel device.

Description

DESCRIPTION OF FIGURES

FIG. 1 Various rectifier diodes (A) simplified construction of silicon P-N rectifier diode (B) schematic representation of silicon P-N rectifier diode (C) I-V characteristics of silicon P-N rectifier diode (linear scale) (C) simplified construction of metal-to-silicon Schottky rectifier diode (D) schematic representation of metal-to-silicon Schottky rectifier diode (E) I-V characteristics of metal-to-silicon Schottky rectifier diode (linear scale).

FIG. 2 Reverse recovery of rectifier in Buck converter example (A) schematic (B) electrical equivalent circuit during diode recovery (C) switching waveforms.

FIG. 3 Synchronous rectifier MOSFET in synchronous Buck converter example (A) circuit (B) switching waveforms (C) I-V characteristics (D) duty factor limitations vs. frequency.

FIG. 4 Enhancement-mode power MESFET (A) device cross section (B) equivalent schematic (C) I-V characteristics (D) gate-only versus threshold two-terminal I-V characteristics (E) active (three-terminal) vs. threshold-connected I-V characteristics.

FIG. 5 Two-terminal MESFET with integrated power Schottky (A) equivalent schematic (B) I-V characteristics (C) alternate schematic representation (D) cross section (E) cross section with enlarged Schottky.

FIG. 6 Two-terminal MESFET with integrated power Schottky and protection Zener (A) schematic (B) reverse mode with avalanche (C) forward mode with Schottky conduction (D) I-V characteristics.

FIG. 7 Synchronous rectifier MESFET with integrated rectifier MESFET and protection Zener (A) equivalent schematic (B) I-V characteristics (C) paralleling of rectifier and synchronous rectifier MESFETs during break-before-make interval (D) cross section of merged device.

FIG. 8 High frequency synchronous Buck converter comprising MESFET switch, synchronous rectifier MESFET, rectifier MESFET, Zener protection, and gate drive circuitry (A) schematic including minimum pulse width control feature (B) Voltage waveform for normal operation (C) voltage waveform for high duty factor operation (D) voltage waveform for short clock periods.

FIG. 9 Algorithm for synchronous rectifier operation with minimum pulse width control (A) Synchronous rectifier turn-on set by PWM control signal masking (B) Synchronous rectifier turn-on set by timer.

DESCRIPTION OF INVENTION

Adapting MESFETs for efficient, robust, and reliable operation as rectifiers and as synchronous rectifiers for use in switching power supplies requires innovations and inventive matter regarding both their fabrication and their use. These innovations are described in the related patent applications previously identified. The design and fabrication of power MESFETs for low noise, high frequency operation with rugged avalanche characteristics, especially for use as rectifiers and synchronous in switching converters at frequencies beyond that of normal silicon MOSFETs capabilities, requires inventive matter, which is the main subject of this invention disclosure.

In another embodiment of this invention, a new MESFET merged device is optimized and used to perform both two-terminal Schottky rectification and synchronous rectification in the same device. In another embodiment of this invention, a gate control method and algorithm is used to switch between rectifier and synchronous rectifier mode to depending on duty factor and switching frequency to optimize converter efficiency over a wide range of operating conditions.

An Enhancement-Mode MESFET as a Rectifier

From the disclosure background of this application, no silicon based device, be it P-N junction rectifier, Schottky rectifier, or synchronous rectifier MOSFET meets the electronics industry's need to increase frequency in modern DC-to-DC converters and switching voltage regulators. Higher frequency is fundamental to improve transient response and to decrease inductor size in such circuits, but using today's available silicon based devices requires circuit and system designers sacrifice efficiency for the sake of size. While devices such as silicon-carbide, indium phosphide, and other compound semiconductor materials have been discussed academically as possible future power devices, their cost, performance, material issues, and reliability compromises were found to be unacceptable for meeting consumer expectations in today's demanding markets of mobile communication, computing and entertainment.

One device technology platform discarded by the semiconductor industry for power applications (other than RF) was that of the gallium arsenide MESFET. Historically “MESFETs”, an acronym for metal-epitaxial-semiconductor field effect transistor, have been applied as an active device only to radio frequency (RF) power amplification and RF signal routing. In contrast to the insulated-gate silicon MOSFETs, MESFET implementation has been largely achieved with gallium arsenide (GaAs), a man-made semiconductor with good properties for high frequency operation. But since GaAs does not produce a stable high-quality dielectric from thermal oxidation or nitridization, its use in other applications has been ignored for a number or reasons. These reasons include:

• (1) The GaAs MESFET is a normally on, i.e. a depletion mode, device. Power electronics and DC-to-DC switching converters need a normally-off (i.e. an enhancement mode) device to operate safely and reliably.
• (2) GaAs MESFET exhibit destructive avalanche properties and fragility in surviving voltage spikes.
• (3) MESFETs are designed for optimal RF characteristics and minimal capacitance, not for power applications requiring minimum resistance and superior current uniformity.
• (4) In RF applications, MESFETs are traditionally biased at a fixed gate voltage and then varied by introducing a small signal input on top of the DC bias, not switched between on and off states in a digital manner. MESFET gate control for digital operation requires special circuitry not to overdrive the gate and potentially damage the device.
• (5) Even in an enhancement mode MESFET, a zero volt bias may be inadequate to fully turn-off the device to suppress drain leakage current.
• (6) MESFETs are non-isolated devices making it difficult to monolithically integrate multiple devices or to benefit from matched device properties and low parasitics. Isolation requires deep expensive mesa etching resulting in a non planar surface not amenable to metal interconnection.

Without addressing all or most of these issues, MESFETs are not suitable for power electronics, and especially for DC-to-DC conversion. If these issues are collectively addressed, however, the MESFET once adapted for power applications offers numerous advantages over silicon power MOSFETs and other devices, including low gate drive voltages, low input capacitance for a given resistance MESFET switch, and the potential for implementing very high frequency DC-to-DC converters with very small inductors.

In this particular inventive embodiment, the utility of the device for rectification is beneficial for low capacitance, no stored charge, low on-state voltage drop, and the prospect for integration into a synchronous rectifier also implemented using a GaAs MESFET. An example of a power MOSFET applicable for rectification is shown cross FIG. 4A. In device cross section 80, MESFET N+ drain region 84 and drain contact 86 is surrounded by concentric gate comprising trench 83 and Schottky gate metal 89 spaced from trench sidewall by a gap or optionally by a sidewall dielectric. N+ source 85 and source contact 87 surrounds the concentric gate. The channel is formed in epitaxial layer 82 formed atop semi-insulating GaAs layer 81. The thickness of epi layer 82 is adjusted to make the threshold of MESFET 80 slightly positive or near zero volts.

FIG. 4B illustrates a schematic representation of the MESFET including active device 99 and the intrinsic Schottky gate represented as Schottky diode 92 between gate and source, and Schottky 91 between gate and drain. The drain-current versus drain-voltage (I-V) characteristics of the enhancement mode MESFET shown by curve 93 (device B) of FIG. 4C is contrasted to the more conventional depletion mode MESFET characteristic of curve 95 (device A). Avalanche breakdown 94 occurs at a higher voltage but may be destructive.

Adapting an enhancement mode power MESFET into a rectifier involves connecting the device in a two-terminal configuration, where the gate is shorted to either the source or the drain terminal (since the device as shown is symmetric the nomenclature is arbitrary). The resulting conduction characteristic is illustrated by curve 97. For GaAs, this turn on “threshold” characteristic is typically 0.3V. This current comprises two components—a small forward biased gate current and a larger channel current resulting from the forward biasing of the gate. Since the MESFET's channel-current contributes, i.e. adds, to the gate current, the resulting voltage drop is substantially lower than the Schottky gate current itself depicted by curve 96, which may be 0.5 to 0.7 volts. The voltage drop of the two-terminal MESFET rectifier therefore has a lower voltage drop and a power loss less than a Schottky diode constructed with the same material.

The same MESFET driven by an independent gate voltage, i.e. operated as a three terminal device, has still a lower voltage drop for the same drain current as shown by curve 98 in FIG. 4E when compared against the aforementioned two-terminal “threshold” connection of curve 96, but as a rectifier requires accurate control of timing the gate turn-on (i.e. synchronous operation), which as described previously is problematic for high frequency operation.

So in summary, an enhancement mode MESFET adapted for power operation may be used as a two terminal rectifier (requiring no gate control or critical timing) or may be used as a three-terminal synchronous rectifier, both of which exhibit a lower voltage drop and reduced power dissipation compared to a conventional Schottky rectifier—even one constructed of the same semiconductor material as the MESFET itself. Since the MESFET rectifier's current is majority—carrier channel—current, there is no stored charge in the device, and therefore no reverse recovery loss.

The Two-Terminal Power MESFET as Schottky Replacement

The two-terminal MESFET rectifier is represented schematically in FIG. 5A as an N-channel MESFET 100 with a source-to-gate short (labeled as “A” for anode) and with a Schottky diode 102 connected between the gate and the MESFET's drain terminal (labeled as “K” for cathode). Schottky diode 102 includes the Schottky gate intrinsic to the MESFET itself and may optionally include a parallel Schottky. The parallel Schottky may be monolithically integrated (and optionally merged into) MESFET 100, or implemented as a discrete Schottky. Since the gate of the MESFET is internally shorted to the MESFET's source, it does not require an external connection. The resulting device is a two-terminal rectifier.

The electrical characteristics of the MESFET rectifier are illustrated in FIG. 5B. As a rectifier, the device blocks current in one polarity, namely in quadrant III, i.e. for (−V, −I), and conducts in the other polarity, namely in quadrant I, i.e. for (+V, +I). In the conducting direction, the rectifier conducts according to curve 103 (a curve describing the threshold characteristic of the MESFET) and has a forward voltage drop of V_F at a current of I_F. In the blocking direction, the off-state leakage of the enhancement mode MESFET is illustrated by curve 105 and varies inversely with threshold voltage and V_F. In an unprotected device, breakdown voltage 104 may be destructive and therefore should be avoided in operation.

The overall device behavior as illustrated in FIG. 5C is therefore similar to a Schottky diode 102, although in reality, the conduction occurs substantially through MESFET 100.

One possible construction of the MESFET rectifier is illustrated in cross section 110 of FIG. 5D, where gate 114 is shorted to anode (source) 116 by metal 118, concentrically surrounding and enclosing drain 115 and cathode (drain) metal 117. Using a sidewall spacer process described in the US Patent Application entitled “Rugged MESFET for Power Application.”, Schottky gate metal 114 is separated from the trench sidewall by spacer dielectric 119. Alternatively, spacer dielectric 119 can be eliminated and gate metal 114 spaced inside trench 113 using photomasking and etching.

While separation between Schottky gate 114 and cathode (drain) material 115 is critical to suppress device leakage, the space between source 116 and gate 114 is not since they are shorted together. The entire device is fabricated in epitaxial layer 112 grown atop semi-insulating GaAs substrate 111.

In another embodiment of this invention shown in FIG. 5E, Schottky metal area is larger than that required in implementing the MESFET's gate. In cross section 130, Schottky diode 143 is integrated in extra wide trench region 136 with Schottky metal 138, having tens or hundreds of times larger area than the MESFET's gate 137. Schottky metal 138 and metallization layer 139 together comprise the anode of the device while GaAs epi layer 132, N+ region 133 and metallization layer 140 constitute the diode's cathode. In the layout shown, the cathode of the Schottky surrounds the anode. Schottky metal 138 is spaced from the sidewall of trench 136 by dielectric spacer 142 or by photolithographically forming Schottky metal 138 entirely inside of trench 136.

Integrated in the same GaAs epi layer 132 is a MESFET rectifier, the MESFET comprising Schottky gate metal 137 located within trench 135, sidewall spacer 141, cathode (drain) 133 and anode (source) 134. Metalization layer 139 shorts the MESFET's Schottky metal 137 to its source 134, making the MESFET into a two-terminal rectifier. As shown, MESFET trench 135 is comparable to the area of Schottky diode trench 136 but could alternatively be made larger to enhance the MESFET's channel conduction or smaller to increase the percentage of current carried by Schottky conduction.

In this embodiment of the invention, the MESFET rectifier is connected in parallel to Schottky rectifier 143 by sharing cathode 133 for both devices, and by electrically shorting metallization layers 136 and 139. The entire merged device is made in GaAs layer 132 formed atop semi-insulating GaAs substrate 131. In the embodiment shown, the MESFET rectifier circumscribes and surrounds the Schottky diode. Interconnection can be made using metallization on-chip, or using bond wires.

Like device 110, device 130 includes an unprotected MESFET, and is therefore vulnerable to damage from excess reverse voltages and avalanche breakdown, i.e. whenever the diode's cathode is biased positively with respect to its anode. The MESFET rectifier is self protecting in the opposite polarity since diode and MESFET channel conduction occurs, unless the current density is too high and excessive heating occurs.

The Zener Protected Two-Terminal MESFET as Schottky Rectifier

An improved version of the MESFET rectifier is shown schematically in FIG. 6A where in apparatus 150, Zener diode 154 is placed in parallel with MESFET rectifier 151, Schottky gate 152, and optional Schottky diode 153, electrically sharing a common anode. The circuit comprises a Zener-clamped MESFET rectifier.

Operation can be understood by analyzing conduction in two different polarities. In the blocking direction shown in FIG. 6B, an overvoltage condition causes Zener diode 154 to break down and clamp the voltage across MESFET 151, protecting the rectifier and gate Schottky 152 from overvoltage or avalanche.

In the forward biased direction, rectifier Zener diode 154, MESFET rectifier 151, Schottky gate 152, and optional rectifier 153 become forward biased, but since MESFET 151 (and to a lesser extent large area Schottky 153) have lower voltage drops, they carry most of the forward current with no stored charge.

The resulting electrical characteristic is shown in FIG. 6D where the forward conduction voltage V_F shown by curve 160 is lower than the Schottky gate characteristic alone, as illustrated by curve 163. In the reverse direction the device leaks current (curve 161) until it reaches the Zener breakdown voltage 162. The Zener voltage 162 must necessarily be lower than the MESFET's fragile BV_DSS

Since it is difficult to implement a Zener diode in GaAs, its monolithic integration into the rectifier MESFET is problematic. A more straightforward approach is to fabricate the Zener in silicon and to co-package the rectifier MESFET with its Zener protective clamp.

The Schottky Rectifier Mode in a Synchronous Rectifier MESFET

The only way to further reduce the forward voltage drop of the MESFET rectifier device is to integrate it into a synchronous rectifier MESFET as shown in FIG. 7A. In circuit 170, two-terminal MESFET rectifier 171, along with gate Schottky 173, optional Schottky 176 and Zener clamp 177 are wired in parallel with three-terminal MESFET 172. The gate input to MESFET 172 includes intrinsic gate to drain Schottky 174 and gate to source Schottky 175. Ideally synchronous rectifier MESFET 172 and two-terminal rectifier MESFET 171 are monolithically integrated (along with optional Schottky 176). Zener diode, better fabricated in silicon, is connected electrically in parallel to the other components, ideally in a common package.

The electrical characteristics of the merged device are shown in FIG. 7B where the forward conduction (when synchronous rectifier MESFET is off) follows curve 181 and has a forward voltage drop V_F at a current I_F. When the synchronous rectifier MESFET is on, the device conducts according to curve 182, having a voltage drop at a current I_F of I_F·R_DS, a voltage drop lower than the rectifier MESFET's forward voltage V_F. Both curves have a lower voltage drop than the device's Schottky gate alone, shown by curve 180.

In the reverse direction whenever the synchronous rectifier is off, the device has a leakage current 184 and a Zener clamped avalanche voltage 185, which is designed to be lower than the MESFET's potentially destructive BV_DSS breakdown.

Curve 183 illustrates that if the synchronous rectifier MESFET is not turned off before the polarity of the applied voltage across the device reverses direction, the synchronous rectifier will undesirably conduct in the reverse direction, lowering efficiency and increasing power losses to potentially damaging levels.

FIG. 7C illustrates that whenever the synchronous rectifier MESFET 172 is shut off by temporarily connecting its gate to its source, it is electrically wired identically to the hard-wired rectifier MESFET 171. The two parallel MESFETs further reduce the forward voltage drop of the rectifier MESFET, since the voltage drop of the MESFET rectifier scales with its channel width, i.e. the size of the MESFET.

One integrated implementation of circuit 170 (without showing optional Schottky 176 or Zener diode 177) is illustrated in FIG. 7D. Specifically, cross section 200 integrates two-terminal rectifier MESFET 171 and three-terminal synchronous rectifier MESFET 172 monolithically without the need for isolation in a common epitaxial layer 202 grown atop a semi-insulating substrate 201. All MESFETs shown contain a trench gate structure with the Schottky gate metal spaced from the trench sidewall, either by physical separation (photolithographically defined) or by sidewall spacer oxide 206 as shown.

In the cross section shown rectifier MESFET 171 is formed with trenches 203B and 203C, Schottky gate metal 205B and 205C, N+ anode (source) region 204C, and interconnection metal 207D. The structure is circumscribed by cathode (drain) N+ regions 204B and 204D and metallization 207C and 207E. Metallization 207D shorts MESFET source 204C to gates 205B and 205C to form the two-terminal MESFET rectifier structure, with no external gate drive required.

Cathode N+ regions 204B and 204D are also surrounded by and electrically shared with synchronous rectifier MESFET 172. The synchronous rectifier MESFET is a three terminal device comprising trenches 203A and 203D, Schottky gate metal 205A and 205D, gate metallization 207B and 207F, N+ source regions 204A and 204E, and source metallization 207A and 207G. The two devices are paralleled by connecting source metal 207A and 207G to anode metal 207D.

Timing of Synchronous Rectifier MESFET Operation

Whenever synchronous rectification is utilized at high frequencies, especially above a few megahertz, synchronous rectifier MESFET timing and gate control is limited by the “narrow pulse” problem. At multi-megahertz frequencies (where the clock period T is sub-microsecond) a high duty cycle D means switch on time t_sw is a significant fraction of the total clock period T. Under such conditions, the time remaining for break-before-make operation t_BBM (to prevent shoot-through) and for synchronous rectifier conduction t_sr is limited.

Operation of a switching converter where there is inadequate time to turn-on and turn-off the synchronous rectifier in the time allowed can lead to poor regulation, electrical noise, variable frequency EMI, loss of efficiency, large shoot-through conduction currents between the supply and ground, and potentially even result in damage to a converter's power devices. This challenge is exacerbated in converter's using power MESFETs, since these devices can switch at a much higher frequency than can silicon based transistors and MOSFETs.

As described previously, a synchronous switching converter involves alternating conducting through a “switch” (which lets power into the converter's energy storage elements from its input) and a synchronous rectifier (which forces the converter's output to be DC), separated by brief break-before-make intervals of time (to prevent shoot-through conduction) during which current is carried by a rectifier diode.

Once a synchronous converter has been turned-on when there is inadequate time to turn it off, one of two undesirable scenarios may result. First, if the synchronous rectifier is left on or turned off too slowly while the “switch” is already beginning to conduct, the minimum safe break-before-make (BBM) time has been violated and excessive and potentially damaging shoot-through conduction will result. In a second case, the switch is not allowed to turn-on until the synchronous rectifier is fully turned off, i.e. the BBM interval is guaranteed. The result is the clock period T will be extended in a varying and unpredictable manner, and a variable frequency will result. The varying frequency causes increased ripple on the converter's input or output and leads to variable frequency noise—noise difficult to filter or avoid.

The solution is to determine whether there is adequate time to use the synchronous rectifier, i.e. to safely turn it on and off, and if sufficient time is not available, to avoid turning on the synchronous rectifier at all during until it is safe to do so. In other words, if adequate time is not available to use the synchronous rectifier (the narrow pulse problem), leave the synchronous rectifier off and rely on conduction through a two-terminal rectifier which requires no gate control to operate.

In the case of the disclosed power MESFET device and its operation, this approach is made easier by the integration of a two terminal MESFET rectifier inside a three-terminal MESFET synchronous rectifier. The merged device also benefits from lack of stray inductance, allowing switching and state transitions with minimal noise and overvoltage “ringing”.

The challenge lies in how to anticipate whether adequate time exists to use the synchronous rectifier or to leave it off. To accomplish this task, a new “minimum pulse width” drive circuit must be added to the signal path driving the gate of the synchronous rectifier. The goal of this circuit is to prevent undesirable turn-on of the synchronous rectifier. This task is “predictive” since an estimate of the time available in a future clock cycle can only be based on past information. Since prediction of the future based on past data is imperfect, some tolerance for error must be included.

A synchronous Buck converter (for stepping down and regulating DC voltages) using power MESFETs and including the “minimum pulse width” (hereafter MPW) function as described is shown in FIG. 8A. In circuit 250, PWM control 266 drives a high-frequency push-pull power half-bridge comprising N-channel MESFET switch 255, and merged MESFET rectifier and synchronous rectifier 251, where said half-bridge controls the current in inductor 257 to regulate the voltage across output capacitor 258. The PWM (or in some cases PFM) signal output from control circuit 266 drives break-before-make (BBM) circuit 263 which is used to drive the power MESFETs at high frequencies without shoot-through current.

High side drive of power MESFET switch 255 is accomplished by floating gate buffer circuit 260 powered by bootstrap capacitor 261 and bootstrap diode 262. Circuit 260 and bootstrap capacitor 261 are referenced to Vx, the source of high side N-channel MESFET switch 255. MESFET 255 is optionally protected by Zener diode 256. The low-voltage output of BBM circuit 263 is level shifted by circuit 264 to drive the input of gate driver 260. The output of gate driver 260 is limited in voltage so that (V_G2−V_x) is restricted to some predetermined maximum value, e.g. 0.5V or 0.6V. This voltage clamped (or alternatively, current clamped) gate driver is needed to minimize gate drive current and associated power losses, and to avoid damaging the MESFET's Schottky gate input, as further disclosed in US patent application entitled “High Frequency Power MESFET Gate Drive Circuits” included herein by reference.

Low-side drive of power MESFET synchronous rectifier 252 is performed by gate buffer 259 powered directly from the converter's input V_batt. Like gate buffer 260, gate driver 259 is a voltage clamped (or current clamped) high speed gate drive circuit with an output voltage V_G1 limited to some prefixed value, typically 0.5V to 0.6V to prevent overdrive of MESFET 252. Synchronous rectifier 252 is wired in parallel with the two-terminal MESFET rectifier 253 and its intrinsic gate Schottky diode 254, and protected by the parallel connected Zener diode clamp 254 to restrict the maximum drain-to-source voltage imposed across MESFETs 252 and 253. The combination as one protected device is represented by box 251 enclosing GaAs MESFETs 252 and 253, and Zener 254, which is integrated in a silicon IC, not in the GaAs chip. MESFET rectifier 253 clamps the maximum below-ground potential to a value V_f during break before make intervals when synchronous rectifier MESFET 252 is still off.

The input signal for synchronous rectifier 252 comes from PWM circuit 266 through BBM circuit 263 and through said minimum pulse width (MPW) circuit 265. The function of MPW circuit 265 is to prevent buffer 259 from turning on synchronous rectifier 252 unless adequate time exists to do so. Various circuits and algorithms may be used to implement the MPW function including counters, logic gates, sample and hold techniques and more.

The resulting waveforms are shown in the plots of V_x versus time in FIGS. 8B, 8C and 8D. In FIG. 8B where the duty factor is low and the period T is relatively long compared to the break-before-make interval t_BBM, line segment 280 represents the time t_sw when high side switch 255 is on. Line segment 281 illustrates the inductor voltage immediately flies below ground when switch 255 is turned off. Immediately thereafter (segment 282) the two-terminal MESFET rectifier 253 clamps the maximum negative going transient to a voltage V_f for the interval t_BBM before synchronous rectifier 252 can be turned on.

Line segment 283 illustrates conduction of the synchronous rectifier 252 at a voltage I_F·R_DS, which is less than V_F of the rectifier MESFET 253. After a time t_SR, synchronous rectifier is turned off. For a duration t_BBM (segment 285) both MESFETs remain off till the switch is turned back on and the voltage at Vx is pulled high (segment 284).

In contrast to this waveform, in FIG. 8C the on-time for the high side switch t_sw is increased to a larger percentage of the period T, i.e. a high duty factor, so that little time remains for rectification. Since the sum of the break before make interval 290 and 291, consume the whole narrow pulse duration, no time is left for synchronous rectification and so it is never turned on.

Similarly in FIG. 8D the same narrow pulse condition arises, not because an extreme duty factor but just because the converter is operating at a higher frequency, i.e. a shorter period T than the prior examples. Again the sum of break-before make intervals 295 and 296 consume the entire pulse width so no time is left for synchronous rectification and the low side MESFET 252 remains off.

Several algorithms may be employed to implement MPW control of the synchronous rectifier device. Flowchart 300 shown in FIG. 9A illustrates after startup (step 301), the converter “switch” is turned on (step 302) and will remain on as long as the PWM control output stays high (step 303). When the PWM output drops low the switch is turned off (step 304) whereby the inductor forces the node voltage Vx to forward bias the rectifier. To avoid shoot through the synchronous rectifier waits for a time t_BBM (step 305) and if the PWM output is still low (step 306) the synchronous rectifier is turned on (step 307) and remains on until the PWM control changes to a high state. At the time, the synchronous rectifier is turned off (step 308) forcing conduction through the rectifier again. After a time interval of t_BBM (step 309), the converter switch is once again turned on (step 302) and the cycle repeats itself.

In this approach the MPW control is achieved by preventing the turn-on of the synchronous rectifier if the PWM control has changed state during the break-before-make interval.

Another approach to determine if the synchronous rectifier should be turned on (or not) is shown in FIG. 9B. In flowchart 350 similar to the prior algorithm, startup 351 is followed by turning on the switch (step 352) and continuing to keep the switch on till the PWM controller changes state (step 353) and shuts it off (step 354).

At this point, a timer is started (step 356) and the break-before-make shoot-through protection is performed in tandem (step 355). This timer is used to measure the time Δt when the switch is off, i.e. the time duration (T−t_sw). This duration must be measured in a previous cycle for use in the decision making of the current cycle, but on the initial cycle the register can be preloaded with some assumed value.

Next the stored time Δt_n−1 (from the previous n−1 cycle) is compared to twice the break-before make interval (step 357) to determine if

Δt_n−1>2·t_BBM+δ

If the time Δt_n−1 is some interval δ longer than twice the BBM operation, then there is adequate time to turn-on the synchronous rectifier (step 358), and if the PWM control output is still low (step 358) then the synchronous rectifier should be turned on (step 363) and left on until the PWM control signal goes high.

If either Δt_n−1 is shorter than twice the BBM operation (plus some interval δ) or the PWM signal goes high, then the synchronous rectifier is turned off (step 359) and after the break before make interval t_BBM, the timer is stopped (step 361), stored as the time Δt_n (step 362), and the switch is turned on (item 352) to be repeated again.

Alternatively the on time of the switch t_sw can be counted and used to decide if the time is adequate to turn on the synchronous rectifier.

Claims

1. A two-terminal MESFET rectifier which includes: a first drain;a first gate; anda first source electrically connected to the first gate.

2. A rectifier as recited in claim 1 where the MESFET is an enhancement-mode N-channel device.

3. A rectifier as recited in claim 1 that is fabricated using gallium arsenide (GaAs) as a semiconductor material.

4. A rectifier as recited in claim 1 that is fabricated using indium phosphide (InP) as a semiconductor material.

5. A rectifier as recited in claim 1 that further comprises a metallization layer that electrically connects the first gate to the first source.

6. A two-terminal MESFET rectifier which includes: a first drain;a first gate;a first source electrically connected to the first gate; anda Schottky diode connected to the first source and first gate.

7. A rectifier as recited in claim 6 where the MESFET rectifier is an enhancement-mode N-channel device.

8. A rectifier as recited in claim 6 that is fabricated using gallium arsenide (GaAs) as a semiconductor material.

9. A rectifier as recited in claim 6 that is fabricated using indium phosphide (InP) as a semiconductor material.

10. A rectifier as recited in claim 6 that further comprises a metallization layer that electrically connects the first gate to the first source.

11. A two-terminal MESFET rectifier which includes: a first drain;a first gate;first source electrically connected to the first gate; anda Zener diode connected to the first source and first gate.

12. A rectifier as recited in claim 11 where the MESFET rectifier is an enhancement-mode N-channel device.

13. A rectifier as recited in claim 11 that is fabricated using gallium arsenide (GaAs) as a semiconductor material.

14. A rectifier as recited in claim 11 that is fabricated using indium phosphide (InP) as a semiconductor material.

15. A rectifier as recited in claim 11 that further comprises a metallization layer that electrically connects the first gate to the first source.

16. A rectifier as recited in claim 11 where the Zener is fabricated using silicon as a semiconductor material.

17. A rectifier as recited in claim 11 that further comprises a Schottky diode connected to the first source and first drain.

18. A rectifier as recited in claim 11 where the majority of off-state avalanche current flows through the Zener.

19. A rectifier as recited in claim 11 where the breakdown voltage of the Zener diode is substantially less than the avalanche breakdown of the MESFET.

20. A rectifier as recited in claim 11 where the majority of forward bias current is conducted through the MESFET rectifier and not through the forward bias of the Zener diode.

21. A rectifier as recited in claim 11 where the majority of forward bias current is conducted through the parallel combination of MESFET rectifier and Schottky diode.

22. A three-terminal MESFET rectifier that comprises: a first MESFET rectifier that includes: a first drain, a first gate, and a first source electrically connected to the first gate, anda second MESFET synchronous rectifier that includes: a second drain electrically connected to the first drain, a second gate, and a second source electrically connected to the first source.

23. A rectifier as recited in claim 22 where the first MESFET rectifier and second MESFET synchronous rectifier are enhancement-mode N-channel devices.

24. A rectifier as recited in claim 22 where the first MESFET rectifier and second MESFET synchronous rectifier are fabricated using gallium arsenide (GaAs) as a semiconductor material.

25. A rectifier as recited in claim 22 where the first MESFET rectifier and second MESFET synchronous rectifier are fabricated using indium phosphide (InP) as a semiconductor material.

26. A rectifier as recited in claim 22 which further comprises a Zener diode with the anode of the Zener diode connected to the first and second sources and the cathode of the Zener connected to the first and second drains.

27. A rectifier as recited in claim 22 which further comprises a Schottky diode with the anode of the Schottky diode connected to the first and second sources and the cathode of the Schottky connected to the first and second drains.

28. A rectifier as recited in claim 26 where the Zener diode is fabricated using silicon as a semiconductor material.

29. A rectifier as recited in claim 26 where the majority of off-state avalanche current flows through the Zener diode.

30. A rectifier as recited in claim 26 where the breakdown voltage of the Zener diode is substantially less than the avalanche breakdown voltage of the first MESFET rectifier and second MESFET synchronous rectifier.

31. A rectifier as recited in claim 26 where a majority of forward bias current is conducted through the combination of the first MESFET rectifier and second MESFET synchronous rectifier and not through the forward bias of the Zener diode.

32. A rectifier as recited in claim 26 which further comprises a Schottky diode with the anode of the Schottky diode connected to the first and second sources and the cathode of the Schottky connected to the first and second drains where the majority of forward bias current is conducted through the parallel combination of the Schottky diode and the first MESFET rectifier and second MESFET synchronous rectifier and not through the forward bias of the Zener diode.

33. A rectifier as recited in claim 27 where the Schottky diode is fabricated monolithically with the first MESFET rectifier and second MESFET synchronous rectifier.

34. A rectifier as recited in claim 21 where the majority of forward bias current is conducted through the second MESFET synchronous rectifier and not through any other device when the second MESFET synchronous rectifier is biased “on”.

35. A rectifier as recited in claim 21 that further comprises a metallization layer that electrically connects the first gate to the first source.

36. A rectifier as recited in claim 21 that further comprises a metallization layer that electrically connects the first source to the second source and the first drain to the second drain.

37. A DC/DC switching power supply that comprises: a synchronous rectifier MESFET; and a gate drive circuit, the gate drive circuit configured to prevent activation of the synchronous rectifier MESFET for periods of time that are shorter than a predetermined duration.

38. A DC/DC switching power supply as recited in claim 37 in which the predetermined duration is based on a break-before-make time associated with the converter.

39. A DC/DC switching power supply that comprises: a synchronous rectifier MESFET;a pulse width modulation control circuit configured to generate a control signal; anda gate drive circuit, the gate drive circuit configured to activate the synchronous rectifier MESFET if the control signal remains low for a predetermined duration following transition of the control signal to a logical low state.

40. A DC/DC switching power supply that comprises: a main switch;synchronous rectifier MESFET;a gate drive circuit, the gate drive circuit configured to activate the synchronous rectifier MESFET during a cycle n if the main switch remained in an “off” state for a time that exceeds a predetermined period during the previous cycle n−1.

41. A DC/DC switching power supply as recited in claim 37 where the “off” time of the main switch during the previous cycle n−1 is measured using a timer and compared to the break before make interval of the switching power supply.