Claims
- 1. A system comprising:
a carrier substrate; a bus formed in the carrier substrate; first and second agents on the bus to communicate with each other via respective I/O buffer circuitry at a nominal bus speed; and first and second test units coupled to the bus to transfer test information between each other via said respective I/O buffer circuitry, at said nominal bus speed, and during a test session, wherein each test unit is to recognize a start of the test session as being indicated by an assertion and deassertion, for predetermined time intervals, of a signal on the bus.
- 2. The system of claim 1 wherein the bus is a point to point bus.
- 3. The system of claim 1 wherein the bus is a parallel bus and the carrier substrate is a printed wiring board, the system further comprising a third agent on the bus to communicate with the first and second agents via further I/O buffer circuitry, and a third test unit coupled to the bus to receive the test information via said further I/O buffer circuitry during the test session, and to recognize the start of the test session as being indicated by the assertion and deassertion, for predetermined time intervals, of the signal on the bus.
- 4. The system of claim 1 wherein said nominal bus speed is a bus clock frequency greater than 500 MHz.
- 5. The system of claim 3 wherein the first test unit is configured as a master to begin the test session by asserting and then deasserting the signal on the bus, and the second and third test units are configured as slaves for the test session and are to detect the assertion and deassertion of the signal.
- 6. The system of claim 4 wherein the test session refers to first and second bus signal groups, each group being associated with a separate, common clock, control signal,
the first test unit to launch a first set of information elements via the first bus signal group at the start of the test session, for capture by the second agent, the second test unit to launch a second set of information elements via the second bus signal group at the start of the test session, for capture by the first agent.
- 7. The system of claim 1 wherein the control signal is a common clock signal being one of an address strobe signal and a data ready signal of a bus protocol used by the first and second bus agents to one of request a transaction and signal the availability of response data, respectively.
- 8. The system of claim 1 wherein the predetermined time interval during which the signal is to be asserted is one bus clock cycle long, and the predetermined time interval during which the signal is to be deasserted is one bus clock cycle long.
- 9. The system of claim 8 wherein the predetermined time interval during which the signal is to be asserted or deasserted is just one bus clock cycle long.
- 10. The system of claim 8 wherein the bus is a parallel bus, the carrier is a printed wiring board, the first agent is a processor, the second agent is a system chipset, and the system is a high volume manufacturing specimen.
- 11. A method comprising:
signaling, by a built-in test unit of a first primary integrated circuit (IC) component of a computer system having a processor, a system interface, and main memory, the start of a test session by asserting and deasserting, for predetermined time intervals, a signal on a bus of the system; recognizing, by a built-in test unit of a second primary IC component of the system, the start of the test session by detecting said assertion and deassertion of the signal; and transferring test information between said primary components on the parallel bus, at a nominal bus speed, during the test session.
- 12. The method of claim 11 further comprising:
recognizing, by a built-in test unit of a third primary IC component of the system, the start of the test session by detecting said assertion and deassertion of the signal.
- 13. The method of claim 12 wherein the test unit of the first component has been designated as a master to announce the test session by asserting and then deasserting the signal on the bus, and the test units of the second and third components have been designated as slaves for the test session.
- 14. The method of claim 11 wherein the test session is to test first and second source synchronous bus signal groups,
the test unit of the first component to launch a first set of information elements on the first bus signal group at the start of the test session, for capture by the second component, the test unit of the second component to launch a second set of information elements on the second bus signal group at the start of the test session, for capture by the first component.
- 15. The method of claim 11 wherein the signal is a bus control signal that is also used by core function circuitry of the first component for bus communications.
- 16. The method of claim 11 wherein the predetermined time interval during which the signal is asserted is one bus clock cycle long, and the predetermined time interval during which the signal is deasserted is also one bus clock cycle long.
- 17. An article of manufacture comprising:
an integrated circuit (IC) component of a computer system, the component being intended for use as part of a production version of the system, the component having a built-in test unit and core function circuitry that are coupled to transfer information over the same I/O buffer circuitry of the component, the test unit to transfer test information during a test session and to recognize announcement of the test session via an assertion and a deassertion, for predetermined time intervals, of an inter-component signal.
- 18. The article of claim 17 wherein the test unit is designed to recognize said predetermined time intervals as being independent of a bus protocol that is to be used by the core function circuitry during normal operation of the system.
- 19. The article of claim 17 wherein the test unit is to be one of (a) a test master to announce the test session by asserting and then deasserting the signal, and (b) a test slave to monitor the signal for announcement of the test session.
- 20. The article of claim 19 wherein the test unit is to launch, at a nominal bus speed, a first set of information elements on a first bus signal group and capture a second set of information elements on a second bus signal group according to different common clock control signals, at the start of the test session.
- 21. The article of claim 17 wherein the control signal is one of an address strobe signal and a data ready signal that is also used by the core function circuitry to one of request a transaction and signal the availability of response data, respectively.
- 22. The article of claim 17 wherein the test unit understands the predetermined time interval during which the signal is to be asserted as being one bus clock cycle long, and the predetermined time interval during which the signal is to be deasserted is also one bus clock cycle long and immediately follows the assertion.
- 23. The article of claim 22 wherein the predetermined time interval during which the signal is asserted or deasserted is only one bus clock cycle long.
- 24. The article of claim 23 wherein the component is one of a processor and a system chipset.
Parent Case Info
[0001] This application is a continuation in part of U.S. application Ser. No. 10/319,517 filed Dec. 16, 2002 entitled “Testing Methodology and Apparatus for Interconnects” (pending) (P13588)
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10319517 |
Dec 2002 |
US |
Child |
10404949 |
Mar 2003 |
US |