Claims
- 1. A prefetch input driver for an integrated circuit, said prefetch input driver comprising:a data input stage receiving data; an enable stage receiving a corresponding data enable; and a write driver providing said received data to an array responsive to a write signal and the state of said enable stage; wherein said data stage and said enable stage each comprise: an input buffer selectively receiving an input; a first latch holding said received input; a driver selectively passing the contents of said first latch; and a second latch maintaining a previous state of said driver when said driver is not passing the contents of said first latch.
- 2. A prefetch input driver as in claim 1, further comprising:a write driver enable enabling said write driver responsive to a write signal and the state of said enable stage.
- 3. A prefetch input driver as in claim 2, wherein the means for enabling the write driver comprises a NAND gate, the NAND gate receiving the write signal and an output of the enable stage, an output of the NAND gate enabling the write driver.
- 4. A prefetch input driver as in claim 3, wherein the first latch and the second latch each comprise a pair of cross coupled inverters.
- 5. A prefetch input driver as in claim 4, wherein the input buffer and the driver each comprises a three state driver.
- 6. A prefetch input driver as in claim 5, wherein the write driver provides a pair of complementary outputs.
- 7. A prefetch input driver as in claim 6, wherein the write driver comprises a pair of three state output drivers.
- 8. A prefetch input driver as in claim 7, wherein each of the three state output drivers comprises:a first driver device of a first conduction type; a second driver device of a second conduction type connected to a conduction terminal of said first driver device; a first pair of devices of said first conduction type each having a first conduction terminal connected in common, the output of said NAND gate being connected to the gates of said first pair, a second conduction terminal of a first of said first pair being connected to a control gate of the first driver device and a second conduction terminal of the second of said pair being connected to a control gate of the second driver device; a second pair of devices, said second pair of devices being of said second conduction type and having a conduction terminal connected in common to a control gate of said second driver device, an output of said data stage coupled to a control gate of a first of said second pair and the output of said NAND gate being connected to the gate of the second of said second pair; a third device of said first conduction type, the output of said data stage being coupled to a control gate of said third device, one conduction terminal of said third device being connected to the first terminal of the first pair of devices at the common connection; and a third device of said second conduction type connected between the control gates of the first driver device and the control gate of the second driver device.
- 9. A prefetch input driver as in claim 8, each of the three state output drivers further comprising:a fourth device of said first conduction type connected to the control gate of the first driver device, the control gate of said fourth device of said first conduction type being connected to the control gate of the third device of the second conduction type.
- 10. A prefetch input driver as in claim 9, wherein the devices are field effect transistors, the first conduction type is p-type and the second conduction type is n-type.
- 11. A prefetch input driver as in claim 9, wherein the input buffer further comprises a dynamic receiver driving the three state driver.
- 12. A prefetch input driver as in claim 11, further comprising:a reset pulse generator generating a reset pulse responsive to said write signal, said first latch in said enable stage being reset by said reset pulse.
- 13. A prefetch input driver as in claim 12, further comprising:a clock pulse generator generating a clock clocking said dynamic receiver, said clock being generated responsive to said input buffer being disabled.
- 14. A prefetch input driver as in claim 13, wherein said integrated circuit is a random access memory and said array is a memory array.
- 15. A prefetch input driver for an integrated circuit, said prefetch input driver comprising:a data input stage receiving data; an enable stage receiving a corresponding data enable; and a write driver providing said received data to an array responsive to a write signal and the state of said enable stage, wherein said data stage and said enable stage each comprises: a plurality of series connected three state drivers; and a latch at an output of each of said three state drivers.
- 16. A prefetch input driver as in claim 15, wherein the plurality of three state drivers is two drivers.
- 17. A prefetch input driver as in claim 15, wherein the plurality of three state drivers is four drivers.
- 18. A prefetch input driver as in claim 17, wherein the first and second drivers are enabled by opposite phases of a first complementary signal pair and the third and fourth drivers are enabled by opposite phases of a second complementary signal pair.
- 19. A prefetch input driver as in claim 18, wherein the first complementary signal pair is a load data signal and the second complementary signal pair is a write data signal.
- 20. A prefetch input driver as in claim 19, wherein said integrated circuit is a random access memory and said array is a memory array.
- 21. A random access memory (RAM) including a plurality of prefetch input write drivers, each of said prefetch input write drivers comprising:a data input stage including two or more series connected three state drivers and a latch at an output of each of said three state drivers, a first of said three state drivers receiving a data input; an enable stage including two or more series connected three state drivers and a latch at an output of each of said three state drivers, a first of said three state drivers receiving a corresponding data enable; and a write driver providing said received data to a memory array responsive to a write signal and the state a last latch of said enable stage.
- 22. A RAM as in claim 21, further comprising:a NAND gate, the NAND gate receiving the write signal and the state of the last latch, an output of the NAND gate enabling the write driver.
- 23. A RAM as in claim 22, wherein the latches each comprise a pair of cross coupled inverters.
- 24. A RAM as in claim 23, wherein the write driver provides a pair of complementary outputs.
- 25. A RAM as in claim 24, wherein the write driver comprises a pair of three state output drivers.
- 26. A RAM as in claim 25, further comprising:a reset pulse generator generating a reset pulse responsive to said write signal, said first latch in said enable stage being reset by said reset pulse.
- 27. A RAM as in claim 26, wherein the plurality of three state drivers is two drivers.
- 28. A RAM as in claim 26, wherein the plurality of three state drivers is four drivers.
- 29. A RAM as in claim 26, said RAM being a synchronous dynamic RAM (SDRAM), said plurality of prefetch input drivers being at least four prefetch input drivers.
RELATED APPLICATION
The present invention is related to U.S. patent application Ser. No. 09/456,588 entitled “A SDRAM With A Maskable Input” to Hanson et al., assigned to the assignee of the present application, filed coincident herewith and incorporated herein by reference.
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